BIOS flash memory switching device and server

Abstract

The embodiment of the utility model discloses a BIOS flash memory switching device and a server. The BIOS flash memory switching device comprises a data processing circuit with a processor, a demultiplexer and a plurality of BIOS flash memories, the data processing circuit is connected with the input end of the demultiplexer and the first end of each BIOS flash memory; the output ends of the demultiplexer are connected with the second ends, used for receiving the enable signals, of the BIOS flash memories in a one-to-one correspondence mode. According to the BIOS flash memory switching device provided by the embodiment of the invention, the influence of the BIOS flash memory exception on the operation of the server can be reduced, and the reliability of the server is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and particularly relates to a BIOS flash switching device and a server. BACKGROUND

[0002] At present, the design of the motherboard of a server is to connect a processor with a single BIOS (Basic Input Output System) flash memory. When the server is started, the processor and the BIOS flash memory are interacted, and the processor boots firmware from the BIOS flash memory to complete starting. However, if the BIOS flash memory is abnormal, the server cannot run normally, which affects the reliability of the server. CONTENT OF THE UTILITY MODEL

[0003] In view of the above problems, the present application provides a BIOS flash switching device and a server, which can reduce the influence of BIOS flash abnormality on the running of the server and improve the reliability of the server.

[0004] In a first aspect, an embodiment of the present application provides a BIOS flash switching device, which comprises a data processing circuit with a processor, a multi-way distributor and a plurality of BIOS flash memories; the data processing circuit is connected with an input end of the multi-way distributor and a first end of each of the BIOS flash memories; and each output end of the multi-way distributor is connected with a second end of each of the BIOS flash memories for receiving an enable signal.

[0005] In the technical scheme of the embodiment of the present application, the BIOS flash switching device comprises a data processing circuit with a processor, a multi-way distributor and a plurality of BIOS flash memories; the data processing circuit is connected with an input end of the multi-way distributor and a first end of each of the BIOS flash memories; and each output end of the multi-way distributor is connected with a second end of each of the BIOS flash memories for receiving an enable signal. Thus, when a BIOS flash memory interacting with the processor is abnormal, the multi-way distributor can switch other BIOS flash memories to interact with the processor, so as to reduce the possibility that the server cannot run normally due to the BIOS flash abnormality and improve the reliability of the server.

[0006] In some embodiments, the data processing circuit comprises the processor, a change-over switch and a baseboard management controller.

[0007] A first active end of the change-over switch is connected with the processor, and a second active end of the change-over switch is connected with the baseboard management controller.

[0008] A common end of the change-over switch is connected with an input end of the multi-way distributor and a first end of each of the BIOS flash memories.

[0009] In some embodiments, a first output terminal of the baseboard management controller is connected with a control terminal of the multiplexer.

[0010] In some embodiments, a second output terminal of the baseboard management controller is connected with a control terminal of the switch.

[0011] In some embodiments, the data processing circuit further comprises a first level conversion circuit.

[0012] The first level conversion circuit is arranged between the first active terminal of the switch and the processor.

[0013] A low level terminal of the level conversion circuit is connected with the processor, and a high level terminal of the level conversion circuit is connected with the first active terminal of the switch.

[0014] In some embodiments, the data processing circuit further comprises a second level conversion circuit.

[0015] The second level conversion circuit is arranged between the common terminal of the switch and the first terminal of each of the BIOS flash memories.

[0016] A low level terminal of the second level conversion circuit is connected with the common terminal of the switch, and a high level terminal of the second level conversion circuit is connected with the first terminal of each of the BIOS flash memories.

[0017] In some embodiments, the device further comprises a burner.

[0018] A first terminal of the burner is connected with the first terminal of each of the BIOS flash memories.

[0019] In some embodiments, a second terminal of the burner for sending an enable signal is connected with an input terminal of the multiplexer.

[0020] In some embodiments, the device further comprises a trusted platform module.

[0021] A first terminal of the trusted platform module is connected with the first terminal of each of the BIOS flash memories, and a second terminal of the trusted platform module is connected with the processor.

[0022] In a second aspect, the application provides a BIOS flash switching device, comprising a processor, a change-over switch, a baseboard management controller, a multiplexer, a first BIOS flash, a second BIOS flash, a first level conversion circuit, a burner and a trusted platform module; a first active end of the change-over switch is connected with the processor through the first level conversion circuit, a second active end of the change-over switch is connected with the baseboard management controller, a common end of the change-over switch is connected with an input end of the multiplexer and a first end of the first BIOS flash and the second BIOS flash; a first output end of the multiplexer is connected with a second end of the first BIOS flash for receiving an enable signal, a second output end of the multiplexer is connected with a second end of the second BIOS flash for receiving an enable signal; a first output end of the baseboard management controller is connected with a control end of the multiplexer, a second output end of the baseboard management controller is connected with a control end of the change-over switch; a low level end of the level conversion circuit is connected with the processor, a high level end of the first level conversion circuit is connected with the first active end of the change-over switch; a first end of the burner is connected with the first end of the first BIOS flash and the second BIOS flash, a second end of the burner for sending an enable signal is connected with the input end of the multiplexer; a first end of the trusted platform module is connected with the first end of the first BIOS flash and the second BIOS flash, a second end of the trusted platform module is connected with the processor.

[0023] In a third aspect, the application provides a server comprising the BIOS flash switching device provided in the first aspect or the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments and are incorporated in and constitute a part of this application. Throughout the drawings, like reference numerals represent similar structures, components, or functions. In the drawings:

[0025] Figure 1 A first structural diagram of the BIOS flash switching device of some embodiments of the application;

[0026] Figure 2 A second structural diagram of the BIOS flash switching device of some embodiments of the application;

[0027] Figure 3 A third structural diagram of the BIOS flash switching device of some embodiments of the application;

[0028] Figure 4 A fourth structural diagram of the BIOS flash switching device of some embodiments of the application;

[0029] Figure 5 Fifth structural diagram of a BIOS flash switching device for some embodiments of the present application;

[0030] Figure 6 Sixth structural diagram of a BIOS flash switching device for some embodiments of the present application;

[0031] Figure 7 Seventh structural diagram of a BIOS flash switching device for some embodiments of the present application.

[0032] Some of the drawings in the detailed description are as follows:

[0033] 10 - data processing circuit; 20 - multiplexer; 30 - BIOS flash; 100 - processor; 101 - conversion switch; 102 - baseboard management controller; 103 - first level conversion circuit; 104 - second level conversion circuit; 40 - burner; 50 - trusted platform module. DETAILED DESCRIPTION

[0034] The embodiments of the technical solutions of the present application will be described in detail below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.

[0036] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0037] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] In the description of the embodiments of the present application, the term "and / or" is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are in an "or" relationship.

[0039] In the description of the embodiments of the present application, the term "a plurality of" means two or more (including two), and similarly, "a plurality of" means two or more (including two).

[0040] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanical connection, or it can be electrical connection; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0041] BIOS is a set of programs fixed to a ROM (Read-Only Memory) chip on the motherboard of a computer, responsible for hardware initialization, self-checking and booting operating system when the computer starts. In related technologies, the motherboard design of the server is to connect the processor with a single BIOS flash memory, and when the server starts, the processor interacts with the BIOS flash memory, and the processor boots the firmware from the BIOS flash memory to complete the startup.

[0042] However, if the BIOS flash memory is abnormal, it will cause the server to run abnormally, affecting the reliability of the server.

[0043] To solve the above technical problems, the embodiments of the present application provide a BIOS flash memory switching device, including a data processing circuit of a processor, a multiplexer and a plurality of BIOS flash memories; the data processing circuit is connected with the input end of the multiplexer and the first end of each BIOS flash memory, and each output end of the multiplexer is connected with the second end of each BIOS flash memory for receiving an enable signal. Thus, when a BIOS flash memory interacting with the processor is abnormal, the multiplexer can switch other BIOS flash memories to interact with the processor, reducing the possibility of server running abnormally due to BIOS flash memory abnormality, and improving the reliability of the server.

[0044] According to some embodiments of the present application, a BIOS flash memory switching device is provided, which includes a data processing circuit of a processor, a multiplexer and a plurality of BIOS flash memories. Figure 1As shown, the BIOS flash memory 30 switching device includes a data processing circuit 10 with a processor 100, a multiplexer 20, and a plurality of BIOS flash memories 30; the data processing circuit 10 is connected with the input end of the multiplexer 20 and the first end of each of the BIOS flash memories 30; each output end of the multiplexer 20 is connected with the second end for receiving an enable signal of each of the BIOS flash memories 30 one by one.

[0045] In some embodiments, the data processing circuit 10 can be a processor 100. The multiplexer 20 has a single input port and a plurality of input ports, and the number of its output ports can be determined according to the number of the BIOS flash memories 30. For example, if the number of the BIOS flash memories 30 is two, a multiplexer 20 with two input ports can be selected.

[0046] The connection between the data processing circuit 10 and the input end of the multiplexer 20 can be direct electrical connection, or indirect electrical connection, for example, other circuits or components can be connected between the data processing circuit 10 and the input end of the multiplexer 20. The connection between the data processing circuit 10 and the first end of the BIOS flash memory 30 can be direct electrical connection, or indirect electrical connection. The connection between the output end of the multiplexer 20 and the second end of the BIOS flash memory 30 can be direct electrical connection, or indirect electrical connection.

[0047] In some embodiments, the communication port of the data processing circuit 10, for example, the SPI (Serial Peripheral Interface) of the processor 100, accesses the first port D0 of each BIOS flash memory 30 for data communication, so that each BIOS flash memory 30 can share the clock and data signals of the SPI bus. Meanwhile, the communication port of the data processing circuit 10, for example, the SPI of the processor 100, also accesses the input port A of the multiplexer 20 to transmit data signals with enable signals to the multiplexer 20. Different output ends of the multiplexer 20 access the second end D1 of different BIOS flash memories 30 for receiving enable signals, that is, access the enable end of different BIOS flash memories 30 respectively. For example, if each BIOS flash memory 30 includes a BIOS flash memory FLASH0 and a BIOS flash memory FLASH1, and the multiplexer 20 includes output ends B0 and B1, the output end B0 is connected with the second end D1 of the FLASH0, and the output end B1 is connected with the second end D1 of the FLASH1.

[0048] In some embodiments, a certain output end can be selected to be connected with the input end by the multiplexer 20, at this time, the enable signal in the data signal output by the data processing circuit 10 can be transmitted to the second end of the BIOS flash memory 30 connected with the output end through the multiplexer 20, so that the BIOS flash memory 30 starts to run in response to the enable signal, at this time, the processor 100 can interact with the BIOS flash memory 30 to complete the boot process of the server.

[0049] If the BIOS flash memory 30 interacting with the data processing circuit 10 is abnormal, such as the BIOS flash memory 30 firmware is damaged, another output end can be selected to be connected with the input end by the multiplexer 20, at this time, the abnormal BIOS flash memory 30 is closed, the data signal with the enable signal output by the data processing circuit 10 can be transmitted to the second end of the BIOS flash memory 30 connected with the other output end through the multiplexer 20, so that the BIOS flash memory 30 connected with the other output end starts to run in response to the enable signal, at this time, the processor 100 can interact with the BIOS flash memory 30 to realize the switching of the BIOS flash memory 30, so that the server can normally complete the boot process.

[0050] If the abnormal BIOS flash memory 30 is firmware damaged, after completing the boot process, the multiplexer 20 can be switched to the BIOS flash memory 30 with the damaged firmware, at this time, the BIOS file that has been completed burning can be directly burned to the BIOS flash memory 30 with the damaged firmware to repair the BIOS flash memory 30 with the damaged firmware.

[0051] A BIOS flash memory 30 switching device is provided, which includes a data processing circuit 10 of a processor 100, a multiplexer 20 and a plurality of BIOS flash memories 30; the data processing circuit 10 is connected with the input end of the multiplexer 20 and the first end of each BIOS flash memory 30, and each output end of the multiplexer 20 is connected with the second end of each BIOS flash memory 30 for receiving the enable signal. Therefore, when a certain BIOS flash memory 30 interacting with the processor 100 is abnormal, the other BIOS flash memory 30 can be switched to interact with the processor 100 by the multiplexer 20, so as to reduce the possibility that the server cannot normally run due to the abnormal BIOS flash memory 30 and improve the reliability of the server.

[0052] In order to further improve the reliability of the server, in some embodiments, the multiplexer 20 can be connected with the data processing circuit 10 and the BIOS flash memories 30 through the processor 100, so that the processor 100 can control the multiplexer 20 to switch the BIOS flash memory 30 interacting with the processor 100. Figure 2As shown, the data processing circuit 10 includes the processor 100, the switch 101, and the baseboard management controller 102; the first active terminal of the switch 101 is connected to the processor 100, and the second active terminal of the switch 101 is connected to the baseboard management controller 102; the common terminal of the switch 101 is connected to the input terminal of the multiplexer 20 and the first terminal of each of the BIOS flash memory 30.

[0053] Among them, the baseboard management controller 102 is a controller used to monitor and manage the server. It can be used to realize remote control and management of the server, such as powering on / off, restarting, maintenance, firmware updates and system installation.

[0054] The first active terminal of the switch 101 can be directly electrically connected to the processor 100 or indirectly electrically connected to the processor 100. The second active terminal of the switch 101 can be directly electrically connected to the baseboard management controller 102 or indirectly electrically connected to the baseboard management controller 102. The common terminal of the switch 101 can be directly electrically connected to the input terminal of the multiplexer 20 and the first terminal of the BIOS flash memory 30, or indirectly connected to the input terminal of the multiplexer 20 and the first terminal of the BIOS flash memory 30.

[0055] In some embodiments, the changeover switch 101 can be a 2-to-1 high-speed switch having a first active terminal A1, a second active terminal A2, and a common terminal C, such as a 2-to-1 low-resistance high-bandwidth bidirectional analog switch chip, which can be used to select one of the first active terminal A1 or the second active terminal A2 to be connected to the common terminal C.

[0056] like Figure 2 As shown, the first active terminal A1 of the switch 101 can be connected to the SPI of the processor 100, and the second active terminal A2 of the switch 101 can be connected to the SPI of the baseboard management controller 102. The common terminal C of the switch 101 is connected to the input port A of the multiplexer 20, and to the first port D0 of each BIOS flash memory 30 used for data communication.

[0057] In some embodiments, the first active terminal A1 of the selector switch 101 is connected to the common terminal C of the selector switch 101 by default, so as to complete the server boot process through the BIOS flash memory 30 selected by the processor 100 and the multiplexer 20. When the BIOS flash memory 30 selected by the multiplexer 20 needs firmware update, the selector switch 101 can be switched to the second active terminal A2 connected to the common terminal C of the selector switch 101, so as to perform firmware update on the BIOS flash memory 30 selected by the multiplexer 20 through the baseboard management controller 102. This improves the convenience of firmware update of the BIOS flash memory 30, and further improves the reliability of the server.

[0058] To improve the convenience of switching the output end of the multiplexer 20, as shown in Figure 3 some embodiments, the first output end of the baseboard management controller 102 is connected to the control end of the multiplexer 20, so that the baseboard management controller 102 controls the switching of the output end of the multiplexer 20.

[0059] The first output end of the baseboard management controller 102 can be a GPIO (General-purpose input / output) interface. The baseboard management controller 102 can send a level signal to the control end of the multiplexer 20 through the GPIO interface to control the output end of the multiplexer 20 to be turned on.

[0060] For example, as shown in Figure 3 the multiplexer 20 includes an input end A, an output end B0, an output end B1, and a control end S for receiving a level signal. The input end A is connected to the common end C of the changeover switch 101, the output end B0 is connected to the second end D1 of the FLASH0, the output end B1 is connected to the second end D1 of the FLASH1, and the control end S is connected to the first output end of the baseboard management controller 102. The baseboard management controller 102 selects the output end B0 or the output end B1 of the multiplexer 20 to be turned on by outputting a high level or a low level to the control end S of the multiplexer 20. If the level signal output by the first output end of the baseboard management controller 102 is a high level, the output end B0 of the multiplexer 20 is turned on with the input end A. If the level signal output by the first output end of the baseboard management controller 102 is a low level, the output end B1 of the multiplexer 20 is turned on with the input end A. Thus, the level signal output by the baseboard management controller 102 can be used to quickly select the output end of the multiplexer 20 to be turned on, thereby improving the convenience of switching the output end of the multiplexer 20.

[0061] To improve the convenience of switching the active end of the changeover switch 101, as shown in Figure 3 some embodiments, the second output end of the baseboard management controller 102 is connected to the control end of the changeover switch 101.

[0062] The second output end of the baseboard management controller 102 can also be a GPIO interface. The baseboard management controller 102 can send a level signal to the control end of the changeover switch 101 through the GPIO interface to control the active end of the changeover switch 101 to be turned on.

[0063] For example, as shown in Figure 3As shown, the switch 101 includes a first active end A1, a second active end A2, a common end C, and a control end S1 for receiving a level signal. The first active end A1 is connected to the SPI of the processor 100, and the second active end A2 is connected to the SPI of the baseboard management controller 102. The common end C is connected to the input port A of the multiplexer 20, and to the first port D0 of each BIOS flash memory 30 for data communication. The control end S1 is connected to the second output end of the baseboard management controller 102. The second output end of the baseboard management controller 102 selects the first active end A1 or the second active end A2 of the switch 101 to be connected to the common end C by outputting a high level or a low level to the control end S1 of the switch 101. When the level signal output by the second output end of the baseboard management controller 102 is high, the first active end A1 of the switch 101 is connected to the common end C; when the level signal output by the second output end of the baseboard management controller 102 is low, the second active end A2 of the switch 101 is connected to the common end C. The second output end of the baseboard management controller 102 outputs a high level by default, and outputs a low level when it is necessary to update the firmware of the BIOS flash memory 30 selected by the multiplexer 20. Thus, the level signal output by the baseboard management controller 102 can be used to quickly select the active end of the switch 101 to be connected, thereby improving the convenience of switching the active end of the switch 101.

[0064] In view of the fact that the level of the SPI signal output by the processor 100 is 1.8V and the transmission distance is short, in some embodiments, as shown in Figure 4 As shown, the data processing circuit 10 further includes a first level conversion circuit 103. The first level conversion circuit 103 is arranged between the first active end of the switch 101 and the processor 100. The low level end of the level conversion circuit is connected to the processor 100, and the high level end of the level conversion circuit is connected to the first active end of the switch 101.

[0065] For example, the first level conversion circuit 103 can include a level converter, such as a bidirectional level converter that converts a 1.8V level to a 3.3V level. The low level end of the level converter is connected to the SPI of the processor 100, and the high level end of the level converter is connected to the first active end A1 of the switch 101. Thus, the level of the SPI signal output by the processor 100 can be converted, and the transmission distance of the SPI signal output by the processor 100 can be increased, so that the wiring mode of the switch 101, the multiplexer 20, or the BIOS flash memory 30 can be more flexible.

[0066] Alternatively, in some embodiments, as shown in Figure 5As shown, the data processing circuit 10 further comprises a second level conversion circuit 104; the second level conversion circuit 104 is arranged between the common terminal of the conversion switch 101 and the first terminal of each BIOS flash memory 30; the low level terminal of the second level conversion circuit 104 is connected with the common terminal of the conversion switch 101, and the high level terminal of the second level conversion circuit 104 is connected with the first terminal of each BIOS flash memory 30.

[0067] For example, the second level conversion circuit 104 can comprise a level converter, such as a bidirectional level converter for converting 1.8V level to 3.3V level. The low level terminal of the level converter can be connected with the common terminal C of the conversion switch 101, and the high level terminal can be connected with the first terminal D0 of each BIOS flash memory 30. Thus, the SPI signal output by the processor 100 at the common terminal C of the conversion switch 101 can be level converted, and the transmission distance of the SPI signal output by the processor 100 can be increased, so that the wiring mode of the conversion switch 101, the multiplexer 20 or the BIOS flash memory 30 can be more flexible.

[0068] In order to further improve the reliability of the server, in some embodiments, as shown in Figure 6 As shown, the BIOS flash memory 30 switching device further comprises a burner 40; the first terminal of the burner 40 is connected with the first terminal of each BIOS flash memory 30.

[0069] The burner 40 is a hardware device for writing or burning programs into integrated circuits. As shown in Figure 6 As shown, the first terminal of the burner 40 can be a communication port D0 for transmitting data signals. The first terminal of the burner 40 is connected with the first terminal of each BIOS flash memory 30, so that the burner 40 can be used to program the BIOS flash memory 30.

[0070] For example, when the burner 40 needs to program a certain BIOS flash memory 30, the multiplexer 20 can be used to select a certain output terminal to be connected with its input terminal at this time. At this time, the enable signal in the data signal output by the data processing circuit 10 will be transmitted to the second terminal of the BIOS flash memory 30 connected with the output terminal through the multiplexer 20, so that the BIOS flash memory 30 starts to run in response to the enable signal. At this time, the burner 40 can be used to program the BIOS flash memory 30.

[0071] In order to more effectively program the BIOS flash memory 30, in some embodiments, as shown in Figure 6 As shown, the second terminal of the burner 40 for transmitting the enable signal is connected with the input terminal of the multiplexer 20. The second terminal of the burner 40 can be a port S# for transmitting the enable signal.

[0072] When the burner 40 needs to program the BIOS flash memory 30, the output end can be selected to be connected to the input end through the multiplexer 20, at this time, the enable signal output by the burner 40 will be transmitted to the second end of the BIOS flash memory 30 connected to the output end through the multiplexer 20, so that the BIOS flash memory 30 starts to run in response to the enable signal, at this time, the BIOS flash memory 30 can be programmed by the burner 40.

[0073] In some embodiments, as shown in Figure 7 The BIOS flash memory 30 switching device can also include a trusted platform module 50, the first end of the trusted platform module 50 is connected to the first end of each BIOS flash memory 30, and the second end of the trusted platform module 50 is connected to the processor 100.

[0074] The trusted platform module 50 is a chip implanted in the computer to provide a trusted root for the computer, which can realize key management, secure boot, platform verification and encryption operation, and can effectively protect the device from security.

[0075] The first end of the trusted platform module 50 can be a communication port D0 for transmitting data signals, and the first end of each BIOS flash memory 30 can be connected to the second end of the trusted platform module 50. The second end of the trusted platform module 50 can also be an enable port S# for receiving an enable signal, which can be connected to the port TPM_CS of the processor 100 for sending an enable signal, so as to start the trusted platform module 50 in response to the enable signal when receiving the enable signal sent by the processor 100, and protect the data interaction in the BIOS flash memory 30 switching device.

[0076] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be described clearly and completely. In some embodiments, as shown in Figure 7 The processor 100, the change-over switch 101, the baseboard management controller 102, the multiplexer 20, the plurality of BIOS flash memories 30, the first level conversion circuit 103, the burner 40 and the trusted platform module 50 are included.

[0077] The first active end A1 of the change-over switch 101 is connected with the processor 100 through the first level conversion circuit 103, and the second active end of the change-over switch 101 is connected with the baseboard management controller 102; the common end C of the change-over switch 101 is connected with the input end of the multiplexer 20 and the first end of each BIOS flash memory 30, such as the common end C of the change-over switch 101 is connected with the input end of the multiplexer 20 and the first end of the first BIOS flash memory FLASH0 and the second BIOS flash memory FLASH1; each output end of the multiplexer 20 is connected with the second end of each BIOS flash memory 30 for receiving an enable signal in a one-to-one correspondence, such as the first output end of the multiplexer 20 is connected with the second end of the first BIOS flash memory FLASH0 for receiving an enable signal, and the second output end of the multiplexer 20 is connected with the second end of the second BIOS flash memory FLASH1 for receiving an enable signal; the first output end of the baseboard management controller 102 is connected with the control end of the multiplexer 20; the second output end of the baseboard management controller 102 is connected with the control end of the change-over switch 101; the low-level end of the level conversion circuit is connected with the processor 100, and the high-level end of the first level conversion circuit 103 is connected with the first active end of the change-over switch 101; the first end of the burner 40 is connected with the first end of each BIOS flash memory 30, such as the first end of the burner 40 is connected with the first end of the first BIOS flash memory FLASH0 and the second BIOS flash memory FLASH1; the second end of the burner 40 for sending an enable signal is connected with the input end of the multiplexer 20; the first end of the trusted platform module 50 is connected with the first end of each BIOS flash memory 30, such as the first end of the trusted platform module 50 is connected with the first end of the first BIOS flash memory FLASH0 and the second BIOS flash memory FLASH1, and the second end of the trusted platform module 50 is connected with the processor 100.

[0078] The initial state of the baseboard management controller 102 is by default to output a high level to the control end of the change-over switch 101 through the second output end, so that the change-over switch 101 is by default to make the first active end of the change-over switch 101 conduct with the common end C of the change-over switch 101. The baseboard management controller 102 outputs a high level to the control end of the multiplexer 20 through the first output end, so that the input end of the multiplexer 20 is conductive with the output end B0 of the first BIOS memory FALSH0 accessed by the multiplexer 20 in each BIOS memory 30, so that the enable signal in the data signal output by the common end C of the change-over switch 101 can be output to the second end of the first BIOS memory FALSH0 through the output end B0, and the first BIOS memory FALSH0 is opened. At this time, the processor 100 can interact with the first BIOS memory FALSH0 for data, and complete the server boot process.

[0079] If the first BIOS memory FALSH0 is abnormal, the baseboard management controller 102 can output a low level to the control end of the multiplexer 20 through the first output end, so that the input end of the multiplexer 20 is connected to the output end B1 of the second BIOS memory FALSH1 in each BIOS memory 30 accessed by the multiplexer 20, and the enable signal in the data signal output by the common end of the conversion switch 101 is output to the second end of the second BIOS memory FALSH1 through the output end B1, so that the second BIOS memory FALSH1 is started, the processor 100 can interact with the second BIOS memory FALSH1, and the switching of the BIOS flash memory 30 is realized, so that the server can normally complete the boot process.

[0080] If the first BIOS memory FALSH0 is damaged, after the boot process is completed, the baseboard management controller 102 outputs a high level to the control end of the multiplexer 20 through the first output end, so as to switch to the first BIOS memory FALSH0 through the multiplexer 20 again, and the BIOS file that has been completed burning can be directly burned to the first BIOS memory FALSH0, and the first BIOS memory FALSH0 is repaired.

[0081] If it is necessary to update a BIOS memory 30, for example, it is assumed that the firmware of the first BIOS memory FALSH0 is updated, the baseboard management controller 102 can output a high level to the control end of the multiplexer 20 through the first output end, so that the input end of the multiplexer 20 is connected to the output end B0 of the first BIOS memory FALSH0 in each BIOS memory 30 accessed by the multiplexer 20, and a low level is output to the control end of the conversion switch 101 through the second output end, so that the conversion switch 101 is switched to the second active end and the common end of the conversion switch 101 is connected. At this time, the data signal output by the common end of the conversion switch 101 is the data signal of the baseboard management controller 102. The enable signal in the data signal can be output to the second end of the first BIOS memory FALSH0 through the output end B0, so that the first BIOS memory FALSH0 is started, and the baseboard management controller 102 can interact with the first BIOS memory FALSH0, so as to realize the firmware update of the first BIOS memory FALSH0.

[0082] Alternatively, the baseboard management controller 102 can output a high level to the control end of the multiplexer 20 through the first output end, so that the input end of the multiplexer 20 is connected to the output end B0 of the first BIOS memory FALSH0 in the BIOS memories 30 accessed by the multiplexer 20. At the same time, the enable signal is sent from the second end of the burner 40 to the input end of the multiplexer 20, and the enable signal can be sent to the first BIOS memory FALSH0 through the output end B0 of the multiplexer 20 to start the first BIOS memory FALSH0. At this time, the burner 40 can interact with the first BIOS memory FALSH0 through the first end to realize the firmware update or burning of the first BIOS memory FALSH0 by the burner 40.

[0083] The embodiments of the present application also provide a server, which comprises the BIOS flash switching device as described in the above embodiments.

[0084] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the specification of the present application. Especially, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A BIOS flash switch apparatus, comprising: The device comprises a data processing circuit with a processor, a multiplexer and a plurality of BIOS flash memories; the data processing circuit is connected with the input end of the multiplexer and the first end of each BIOS flash memory; each output end of the multiplexer is connected with the second end of each BIOS flash memory for receiving an enable signal.

2. The BIOS flash switch apparatus of claim 1, wherein, The data processing circuit comprises the processor, a change-over switch and a baseboard management controller; the first active end of the change-over switch is connected with the processor, and the second active end of the change-over switch is connected with the baseboard management controller; the common end of the change-over switch is connected with the input end of the multiplexer and the first end of each BIOS flash memory.

3. The BIOS flash switch apparatus of claim 2, wherein, The first output end of the baseboard management controller is connected with the control end of the multiplexer.

4. The BIOS flash switch apparatus of claim 2 or 3, wherein, The second output end of the baseboard management controller is connected with the control end of the change-over switch.

5. The BIOS flash switch apparatus of claim 2, wherein, The data processing circuit further comprises a first level conversion circuit; the first level conversion circuit is arranged between the first active end of the change-over switch and the processor; the low level end of the level conversion circuit is connected with the processor, and the high level end of the level conversion circuit is connected with the first active end of the change-over switch.

6. The BIOS flash switch apparatus of claim 2, wherein, The data processing circuit further comprises a second level conversion circuit; the second level conversion circuit is arranged between the common end of the change-over switch and the first end of each BIOS flash memory; the low level end of the second level conversion circuit is connected with the common end of the change-over switch, and the high level end of the second level conversion circuit is connected with the first end of each BIOS flash memory.

7. The BIOS flash switch apparatus of any of claims 1-3, 5-6, wherein, The device further comprises a burner; the first end of the burner is connected with the first end of each BIOS flash memory.

8. The BIOS flash switch apparatus of claim 7, wherein, The second end of the burner for sending an enable signal is connected with the input end of the multiplexer.

9. The BIOS flash switch apparatus of any of claims 1-3, 5, 6, or 8, wherein, The device further comprises a trusted platform module; the first end of the trusted platform module is connected with the first end of each BIOS flash memory, and the second end of the trusted platform module is connected with the processor.

10. A BIOS flash switch apparatus, comprising: The device comprises a processor, a change-over switch, a baseboard management controller, a multiplexer, a first BIOS flash memory, a second BIOS flash memory, a first level conversion circuit, a burner and a trusted platform module; the first active end of the change-over switch is connected with the processor through the first level conversion circuit, the second active end of the change-over switch is connected with the baseboard management controller, and the common end of the change-over switch is connected with the input end of the multiplexer and the first end of the first BIOS flash memory and the second BIOS flash memory; the first output end of the multiplexer is connected with the second end of the first BIOS flash memory for receiving an enable signal, and the second output end of the multiplexer is connected with the second end of the second BIOS flash memory for receiving an enable signal; the first output end of the baseboard management controller is connected with the control end of the multiplexer, and the second output end of the baseboard management controller is connected with the control end of the change-over switch. The low level end of the level conversion circuit is connected with the processor, and the high level end of the first level conversion circuit is connected with the first active end of the conversion switch; The first end of the burner is connected with the first end of the first BIOS flash memory and the second BIOS flash memory, and the second end of the burner for sending an enable signal is connected with the input end of the multiplexer; The first end of the trusted platform module is connected with the first end of the first BIOS flash memory and the second BIOS flash memory, and the second end of the trusted platform module is connected with the processor.

11. A server, characterized by The BIOS flash memory switching device comprises the BIOS flash memory switching device according to any one of claims 1-10.

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