Board-level hardware structure

Abstract

The utility model provides a board-level hardware structure, which comprises a DCU chip, a first OAM standard connector, a second OAM standard connector and a power conversion tree module, the DCU chip is respectively connected with the first OAM standard connector and the second OAM standard connector, and the power conversion tree module is connected with the DCU chip and the first OAM standard connector. The second OAM standard connector is connected with the first OAM standard connector and used for converting an external power supply accessed by the first OAM standard connector and then providing the converted external power supply to the DCU chip, the first OAM standard connector is connected with a connector meeting the OAM standard on the mainboard in a matched mode and used for achieving interconnection between the DCU chip and uplink equipment on the mainboard, and the second OAM standard connector is connected with other DCU chips and used for achieving interconnection of multiple DCU chips. According to the utility model, the expansibility of the DCU chip can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit technical field especially relates to a board level hardware structure. BACKGROUND

[0002] With the development of artificial intelligence application, the role of computing power, algorithm and big data is more and more important, and the computing power is the support of algorithm and big data, and the heterogeneous computing chip is the cornerstone of the development of computing-intensive application industries such as artificial intelligence, and it is also one of the key cores to break the choke point of China.

[0003] Among them, the deep computing processor DCU (Deep-learning Computing) chip for realizing heterogeneous computing is a computing power chip mainly applied to data centers, and it is also a PCIe EP (Peripheral Component Interconnect Express Endpoint) device, which needs to be connected to the PCIe Host (Peripheral Component Interconnect Express Host), such as CPU (Central Processing Unit).

[0004] The existing DCU chip can only interact with the PCIe Host after being integrated into the mainboard, and the expansion performance is low. UTILITY MODEL CONTENTS

[0005] To solve the above problems, the board level hardware structure provided by the utility model can improve the expansibility of the DCU chip by setting the first OAM standard connector, the second OAM standard connector and the power conversion tree module on the DCU chip.

[0006] The utility model provides a kind of board level hardware structure, and board level hardware structure includes: DCU chip, first OAM standard connector, second OAM standard connector and power conversion tree module, DCU chip is connected with first OAM standard connector and second OAM standard connector respectively, power conversion tree module is connected with DCU chip and first OAM standard connector, for providing DCU chip after converting external power supply connected by first OAM standard connector, wherein, first OAM standard connector is connected with the connector meeting OAM standard on mainboard, for realizing the interconnection of DCU chip and uplink device on mainboard, second OAM standard connector is connected with other DCU chip, for realizing the interconnection of multiple DCU chips.

[0007] Optionally, PCIe uplink interface and multiple expansion interfaces are arranged on the DCU chip.

[0008] The DCU chip is configured to connect a PCIe upstream device through a PCIe upstream interface and connect multiple extension devices through multiple extension interfaces.

[0009] Optionally, the multiple extension interfaces include seven groups of xHCL x8 interfaces.

[0010] The PCIe upstream interface includes a group of PCIe x16 interfaces, and the PCIe x16 interfaces support an xHCL protocol.

[0011] Optionally, the PCIe upstream interface further includes a group of PCIe fallback interfaces.

[0012] When the DCU chip is configured to connect an external device supporting the xHCL protocol through the PCIe x16 interface, the DCU chip is configured to connect the PCIe upstream device through the PCIe fallback interface.

[0013] Optionally, a MISC (Miscellaneous) signal interface is further arranged on the DCU chip.

[0014] The MISC signal interface includes at least one of an SPI (Serial Peripheral Interface) interface, an SMBUS (System Management Bus) interface, a GPIO (General-purpose input / output) interface, and a power management interface.

[0015] Optionally, a core clock interface, a PCIe clock interface, and an xHCL clock interface are further arranged on the DCU chip.

[0016] The core clock interface is configured to provide a clock signal for a core of the DCU chip, the PCIe clock interface is configured to provide a clock signal for the PCIe upstream interface, and the xHCL clock interface is configured to provide a clock signal for the multiple xHCL interfaces.

[0017] Optionally, a WAFL (Wide Area Functional Link) management interface is arranged on the DCU chip.

[0018] The DCU chip is further configured to connect an extension device through the WAFL management interface.

[0019] Optionally, the power conversion tree module includes a controller and a voltage conversion unit.

[0020] The DCU chip is connected to the controller, the controller is electrically connected to the voltage conversion unit, the voltage conversion unit is electrically connected to the first OAM standard connector and the DCU chip, and the DCU chip adjusts the voltage output of the voltage conversion unit through the controller to adapt to the DCU chip.

[0021] Optionally, the DCU chip is provided with multiple power interfaces;

[0022] The voltage conversion unit is electrically connected to multiple power interfaces.

[0023] Optionally, the power conversion tree module further includes: a first power conversion unit;

[0024] The voltage conversion unit connects to the first OAM standard connector via the first power conversion unit;

[0025] The first OAM standard connector provides a first fixed voltage to the voltage conversion unit through the first power conversion unit.

[0026] Optionally, the power conversion tree module further includes: a second power conversion unit and a third power conversion unit;

[0027] The voltage conversion unit is electrically connected to the first OAM standard connector via the second power conversion unit and the third power conversion unit, respectively.

[0028] The first OAM standard connector provides a second fixed voltage to the voltage conversion unit through the second power conversion unit, and provides a third voltage to the voltage conversion unit through the third power conversion unit.

[0029] Optionally, the DCU chip is also provided with multiple power supply units, and the power conversion tree module is electrically connected to the multiple power supply units respectively;

[0030] The power conversion tree module is used to connect to an external power source and convert the voltage provided by the external power source into an operating voltage that is compatible with multiple power supply units.

[0031] Optionally, the multiple power supply units include: core power supply, on-chip system power supply, memory system power supply and memory I / O (Input Output) power supply;

[0032] The power conversion tree module is electrically connected to the core power supply, on-chip system power supply, memory system power supply and memory I / O power supply respectively;

[0033] The power conversion tree module provides voltage to the core power supply, on-chip system power supply, memory system power supply, and memory I / O power supply, respectively.

[0034] Optionally, the voltage conversion unit includes: a first voltage conversion unit, a second voltage conversion unit, a third voltage conversion unit, and a fourth voltage conversion unit;

[0035] The first voltage conversion unit is electrically connected with the core power supply and provides a voltage of any value in the first voltage range to the core power supply.

[0036] The second voltage conversion unit is electrically connected with the system on chip power supply and provides a voltage of any value in the second voltage range to the system on chip power supply.

[0037] The third voltage conversion unit is electrically connected with the memory system power supply and provides a voltage of any value in the third voltage range to the memory system power supply.

[0038] The fourth voltage conversion unit is electrically connected with the memory IO power supply and provides a voltage of any value in the fourth voltage range to the memory IO power supply.

[0039] Optionally, the first power conversion unit is electrically connected with the first voltage conversion unit, the second voltage conversion unit, the third voltage conversion unit and the fourth voltage conversion unit respectively.

[0040] The first power conversion unit provides a first fixed voltage to the first voltage conversion unit, the second voltage conversion unit, the third voltage conversion unit and the fourth voltage conversion unit.

[0041] Optionally, the second power conversion unit is electrically connected with the first voltage conversion unit and the second voltage conversion unit respectively, and the third power conversion unit is electrically connected with the third voltage conversion unit and the fourth voltage conversion unit respectively.

[0042] The second power conversion unit provides a second fixed voltage to the first voltage conversion unit and the second voltage conversion unit, and the third power conversion unit provides a third fixed voltage to the third voltage conversion unit and the fourth voltage conversion unit.

[0043] Optionally, the controller comprises a first controller and a second controller.

[0044] The first controller and the second controller are both electrically connected with the DCU chip, the first controller is electrically connected with the first voltage conversion unit and the second voltage conversion unit respectively, and the second controller is electrically connected with the third voltage conversion unit and the fourth voltage conversion unit respectively.

[0045] The board-level hardware structure provided by the embodiment of the utility model, through setting first OAM standard connector, second OAM standard connector and power conversion tree module in DCU chip, make DCU chip can pass through first OAM standard connector and be electrically connected with uplink device, pass through second OAM standard connector and be electrically connected with DCU chip, improved the expansibility of DCU chip. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings that need to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0047] Figure 1 A schematic structural diagram of a board-level hardware structure of an embodiment of the present application;

[0048] Figure 2 A schematic partial circuit diagram of a board-level hardware structure of an embodiment of the present application;

[0049] Figure 3 A schematic partial circuit diagram of a board-level hardware structure of an embodiment of the present application;

[0050] Figure 4 A schematic partial circuit diagram of a board-level hardware structure of an embodiment of the present application;

[0051] Figure 5 A schematic partial circuit diagram of a board-level hardware structure of an embodiment of the present application.

[0052] Reference signs:

[0053] 1, DCU chip; 2, horizontal connector; 3, power conversion tree module; 311, first controller; 312, second controller; 32, VR unit group; 321, first voltage conversion unit; 322, second voltage conversion unit; 323, third voltage conversion unit; 324, fourth voltage conversion unit; 325, first power conversion unit; 326, second power conversion unit; 327, third power conversion unit; 4, FLASH memory chip; 5, CPLD. DETAILED DESCRIPTION

[0054] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0056] An embodiment of the present application provides a board-level hardware structure, as shown inFigure 1 The board-level hardware structure comprises a DCU chip 1, a first OAM standard connector, a second OAM standard connector and a power conversion tree module 3. The first OAM standard connector and the second OAM standard connector are both horizontal connectors 2.

[0057] The DCU chip 1 is connected with the first OAM standard connector and the second OAM standard connector respectively, and the power conversion tree module 3 is connected with the DCU chip 1 and the first OAM standard connector, and is used for converting an external power connected with the first OAM standard connector and providing the converted power to the DCU chip 1. The first OAM standard connector is connected with a connector on a mainboard in a matched mode to realize the interconnection between the DCU chip 1 and an uplink device on the mainboard. The second OAM standard connector is connected with other DCU chips 1 to realize the interconnection between the DCU chips 1.

[0058] The board-level hardware structure provided in the embodiment can realize the electrical connection between the DCU chip 1 and the uplink device through the first OAM standard connector, and the electrical connection between the DCU chip 1 and the expansion device through the second OAM standard connector, thereby improving the expansibility of the DCU chip 1. The expansion device comprises other DCU chips 1. The power conversion tree module 3 can convert the voltage provided by the external power into a working voltage suitable for the DCU chip 1, so as to meet the power demand of the DCU chip 1.

[0059] Based on the above Figure 1 Corresponding to the embodiment, the utility model discloses another board-level hardware structure, and in this embodiment, the board-level hardware structure comprises a DCU chip 1. The DCU chip 1 is provided with a PCIe uplink interface and a plurality of expansion interfaces.

[0060] The DCU chip 1 is used for connecting a PCIe uplink device through the PCIe uplink interface and connecting a plurality of expansion devices through the plurality of expansion interfaces.

[0061] The PCIe uplink device is a PCIe Host, which comprises but is not limited to a CPU. The expansion device can be a DCU chip 1 having the same structure as the DCU chip 1 in the embodiment or a different DCU chip 1, or can be a Switch chip system supporting an xHCL protocol, but is not limited thereto. In addition, the plurality of expansion interfaces can be a plurality of xHCL interfaces. The xHCL interface can realize specific communication functions by using a corresponding private protocol, and the embodiment does not make specific limitation thereto.

[0062] In the embodiment, the plurality of expansion interfaces include seven groups of xHCL x8 interfaces, which are G0 to G6 interfaces on the DCU chip 1 respectively. The PCIe upstream interface includes one group of PCIe x16 interfaces, which is P1 interface on the DCU chip 1.

[0063] The PCIe x16 interface supports the xHCL protocol. It can be understood that the PCIe x16 interface supports both the PCIe protocol and the xHCL protocol, so that the DCU chip 1 can be connected to a CPU supporting the PCIe protocol or the xHCL protocol, thereby improving the compatibility of the DCU chip 1.

[0064] The board-level hardware structure further includes a horizontal connector 2. The DCU chip 1 is electrically connected to the horizontal connector 2. The DCU chip 1 is configured to be connected to the PCIe upstream device and the expansion device through the horizontal connector 2.

[0065] In the embodiment, the board-level hardware structure complies with the OAM (Ocp Accelerator Module) standard; the horizontal connector 2 is a high-density horizontal connector 2 defined by the OAM standard connector signal, and the number is two, which are CON-0 and CON-1, i.e., a first OAM standard connector and a second OAM standard connector. The G0 to G5 interfaces are electrically connected to the CON-1, and the G6 interface and the P1 interface are electrically connected to the CON-0.

[0066] By using the high-density horizontal connector 2 to connect the DCU chip 1 and the peripheral device, when the DCU chip 1 needs to be disassembled from the mainboard, the DCU chip 1 can be quickly disassembled without a special soldering maintenance table, thereby reducing the cost of repairing the DCU chip 1, facilitating the operation of upgrading the DCU chip 1, and solving the problem of system height, which is particularly suitable for some large data centers or supercomputing centers with limited height and high integration requirements. In addition, compared with the connection mode of the golden finger, the use of the high-density horizontal connector 2 to connect the DCU chip 1 and the peripheral device can increase the number of signal interconnections of the peripheral device of the DCU chip 1, and increase the stability of the entire board-level hardware structure.

[0067] The PCIe upstream interface further includes one group of PCIe backup interfaces, which is P0 interface on the DCU chip 1. The PCIe backup interface supports the PCIe protocol. In the embodiment, the PCIe backup interface is a PCIe x4 interface; the P0 interface is electrically connected to the CON-0; and the P0 interface and the P1 interface share one PCIe controller. When the DCU chip 1 connects an external device supporting the xHCL protocol through the PCIe x16 interface, the DCU chip 1 connects the PCIe upstream device through the PCIe backup interface.

[0068] The DCU chip 1 is further provided with a MISC signal interface. The MISC signal interface is used to realize the interaction of the DCU chip 1 with peripheral devices for MISC signals. The MISC signals include, but are not limited to, RESETn (reset), GPIO, SMBUS and other sideband signals, for the setting management of the peripheral circuit of the DCU chip 1. The MISC signal interface includes at least one of an SPI interface, an SMBUS interface, a GPIO interface and a power management interface.

[0069] In the embodiment, the MISC signal interface includes, but is not limited to, a RESETn interface, an SPI interface, an SMBUS interface, a GPIO interface and a power management interface; the DCU chip 1 is electrically connected with a FLASH (flash memory) storage chip 4 through the SPI interface.

[0070] The DCU chip 1 is further provided with an SPI interface, an SMBUS interface, a GPIO interface and a power management interface. The RESETn interface and the SMBUS interface on the DCU chip 1 respectively connect the RESETn signal and the SMBUS signal to the CON-0 high-density horizontal connector 2 defined by the OAM standard according to the PCIe standard specification, so as to manage and communicate with the mainboard.

[0071] The DCU chip 1 is provided with a WAFL management interface. The DCU chip 1 is connected with a CON-1 connection expansion device through the WAFL management interface, so as to realize the interconnection transmission initialization management data among multiple DCU chips 1. The process of transmitting the initialization management data involves multiple key steps, including data collection and arrangement, data verification and testing, data backup and recovery, data security and permission setting, etc., which will not be described in detail in the embodiment.

[0072] The DCU chip 1 is further provided with a core clock interface, a PCIe clock interface and an xHCL clock interface. The core clock interface provides a clock signal for the core of the DCU chip 1, the PCIe clock interface provides a clock signal for the PCIe uplink interface, and the xHCL clock interface provides a clock signal for multiple xHCL interfaces.

[0073] In the embodiment, the PCIe clock interface includes a first PCIe clock sub-interface and a second PCIe clock sub-interface. The first PCIe clock sub-interface shares a P1 interface with the PCIe x16 interface to provide a clock signal PCIe REF CLK for the data transmitted by the PCIe x16 interface; the second PCIe clock sub-interface shares a P0 interface with the PCIe x4 interface to provide a clock signal PCIe REF CLK for the data transmitted by the PCIe x4 interface. In addition, the DCU chip 1 further externally connects a WAFL signal WAFL REF CLK through the CON-1.

[0074] In combination Figure 1 And Figure 2 The board-level hardware structure further comprises a power conversion tree module 3 and a CPLD (Complex Programmable Logic Device) 5. The power conversion tree module 3 comprises a VR (Voltage Regulator) unit group 32. A plurality of power supply units are also provided on the DCU chip 1, and the VR unit group 32 is electrically connected to the plurality of power supply units respectively; the VR unit group 32 is used to be electrically connected to an external power supply through a first OAM standard connector, and convert the voltage provided by the external power supply into a working voltage suitable for the plurality of power supply units. The GPIO interface on the DCU chip 1 connects the GPIO signal to the VR unit group 32 according to the requirement, so as to realize the peripheral auxiliary functions of the DCU chip 1, such as LED (Light Emitting Diode) indication and the like.

[0075] The CPLD 5 is electrically connected to the DCU chip 1 and the VR unit group 32. The CPLD 5 manages the power-on and power-off timing of all the power supplies in the power conversion tree module 3, and controls all the power supplies in the power conversion tree module 3 to power on in the order required by the DCU chip 1. Among them, the power-on and power-off timing of the VR unit group 32 is included, but not limited to. In addition, the CPLD 5 also needs to handle some other abnormal situations, such as the DCU chip 1 detects abnormal phenomena and needs to be powered off urgently, that is, the MISC signal of the DCU chip 1 is connected to the CPLD 5, and the CPLD 5 is told about the abnormal situation of the DCU chip 1 through the MISC signal. After receiving the MISC signal, the CPLD 5 closes the VR unit group 32 in turn and powers off the DCU chip 1. In addition, the CPLD 5 is also responsible for some logic signal processing and expansion of the peripheral circuit of the DCU chip 1, such as management of the LED indication function and the like.

[0076] The plurality of power supply units comprise a core power supply, a system-on-chip power supply, a memory system power supply and a memory IO (Input Output) power supply. Among them, the core power supply is used to supply power for the core on the DCU chip 1; the system-on-chip power supply is used to supply power for the elements on the DCU chip 1 except the core; the memory system power supply is used to supply power for the memory work in the board-level hardware structure; the memory IO power supply is used to supply power for the interface connected to the outside of the memory for signal transmission, and its functions include but are not limited to providing signal level and the like.

[0077] The power conversion tree module 3 is electrically connected to the core power supply, the system-on-chip power supply, the memory system power supply and the memory IO power supply respectively. The power conversion tree module 3 provides voltage to the core power supply, the system-on-chip power supply, the memory system power supply and the memory IO power supply through the VR unit group 32 respectively.

[0078] Further, the VR unit group 32 includes a first voltage conversion unit 321, a second voltage conversion unit 322, a third voltage conversion unit 323, and a fourth voltage conversion unit 324.

[0079] The first voltage conversion unit 321 is electrically connected to the core power supply and provides a voltage of any value ranging from 12V to 1V to the core power supply; the second voltage conversion unit 322 is electrically connected to the system-on-chip power supply and provides a voltage of any value ranging from 12V to 1V to the system-on-chip power supply; the third voltage conversion unit 323 is electrically connected to the memory system power supply and provides a voltage of any value ranging from 12V to 0.75V to the memory system power supply; and the fourth voltage conversion unit 324 is electrically connected to the memory IO power supply and provides a voltage of any value ranging from 12V to 1.35V to the memory IO power supply.

[0080] The VR unit group 32 further includes a first power conversion unit 325. The first power conversion unit 325 is electrically connected to the first voltage conversion unit 321, the second voltage conversion unit 322, the third voltage conversion unit 323, and the fourth voltage conversion unit 324, respectively. The first power conversion unit 325 provides a voltage of 12V to the first voltage conversion unit 321, the second voltage conversion unit 322, the third voltage conversion unit 323, and the fourth voltage conversion unit 324.

[0081] The first power conversion unit 325 is electrically connected to an external power supply which provides a 3.3V auxiliary voltage (3.3V_AUX) and at least one of a 12V main voltage (12V_Main) and a 48V main voltage (48V_Main) through the CON-0.

[0082] In the embodiment, the first power conversion unit 325 is a power conversion unit which converts an input 48V voltage into a 12V voltage and outputs the 12V voltage; and the external power supply provides a 3.3V auxiliary voltage and a 48V main voltage through the CON-0. After the 3.3V auxiliary voltage is connected to the CPLD 5, the system is always powered when the system is in a sleep state or a working state, i.e., the CPLD 5 is always in a working state, so that the function of managing the power-on and power-off timing of all power supplies can be realized.

[0083] The CPLD 5 includes a first controller 311 and a second controller 312. The first controller 311 and the second controller 312 are both VR controllers.

[0084] The first controller 311 and the second controller 312 are electrically connected with the DCU chip 1. The first controller 311 is electrically connected with the first voltage conversion unit 321 and the second voltage conversion unit 322 respectively, so as to control the output voltage of the first voltage conversion unit 321 and the second voltage conversion unit 322. The second controller 312 is electrically connected with the third voltage conversion unit 323 and the fourth voltage conversion unit 324 respectively, so as to control the output voltage of the third voltage conversion unit 323 and the fourth voltage conversion unit 324.

[0085] It can be understood that the DCU chip 1 is connected with the SVI (Serial VID Interface, Serial Voltage Identification Interface) of the VR controller, so as to realize real-time dynamic adjustment of the output voltage of the VR unit group 32. The DCU chip 1 has two groups of SVI serial power voltage adjustment control interfaces, which are also called power management interfaces.

[0086] Each group of SVI serial power voltage adjustment control interfaces supports two protocols of SVI2 and SVI3. The SVI2 protocol is suitable for one-to-one interface, that is, the DCU chip 1 can only externally connect and manage one VR controller with an SVI2 interface through the SVI serial power voltage adjustment control interface supporting only the SVI2 protocol. The SVI3 protocol is suitable for one-to-many interface, that is, the DCU chip 1 can externally connect and manage multiple VR controllers with SVI3 interfaces through the SVI serial power voltage adjustment control interface supporting only the SVI3 protocol, and can support more power dynamic management.

[0087] In the embodiment, a VR controller supporting two protocols of SVI2 and SVI3 supports output of two power supply paths, and can independently dynamically adjust the power supply units on each path respectively, so as to realize power consumption ratio optimization of the DCU chip 1. It should be noted that, in the utility model, the power consumption management method and the computer program involved in the dynamic management of the power consumption of multiple power supply units by the DCU chip 1 through the VR controller and the VR unit group 32 can be realized by using the prior art, and the embodiment does not make specific limitation on this.

[0088] In addition, in the embodiment, the VR unit group 32 further includes multiple power supply units providing fixed voltages to the DCU chip 1, so as to ensure stable operation of the system, which mainly includes a VCCIO_3V3 power supply unit, a VCCIO_1V8 power supply unit, a VPP_2V5 power supply unit, a VDDIO_xHCL power supply unit, a VDDIO_WAFL power supply unit, a VDDAN_0V75 power supply unit and the like, so as to supply power to corresponding IO interface modules on the DCU chip 1 respectively.

[0089] The input ends of the VCCIO_3V3 power supply unit, the VCCIO_1V8 power supply unit, the VPP_2V5 power supply unit, the VDDIO_xHCL power supply unit, the VDDIO_WAFL power supply unit and the VDDAN_0V75 power supply unit can be electrically connected with the output end of the first power conversion unit 325 or can be electrically connected with the 12V_Main end of the external power supply that can provide a 12V voltage, so as to convert the 12V voltage into a corresponding voltage value for output, for example, the VCCIO_3V3 power supply unit can convert the 12V voltage into a 3.3V voltage and provide the voltage to the corresponding IO interface module.

[0090] In the embodiment, the VCCIO_3V3 power supply unit, the VCCIO_1V8 power supply unit, the VPP_2V5 power supply unit, the VDDIO_xHCL power supply unit, the VDDIO_WAFL power supply unit and the VDDAN_0V75 power supply unit are electrically connected with the output end of the first power conversion unit 325. The two groups of SVI serial power voltage adjustment control interfaces on the DCU chip 1 are respectively an SVI2 0 interface and an SVI2 1 interface, and the SVI2 0 interface and the SVI2 1 interface both support only the SVI2 protocol. The DCU chip 1 is electrically connected with the first controller 311 through the SVI2 0 interface and is electrically connected with the second controller 312 through the SVI2 1 interface.

[0091] The board-level hardware structure provided in the embodiment has the PCIe uplink interface and the plurality of expansion interfaces arranged on the DCU chip 1, so that the DCU chip 1 can be electrically connected with the PCIe uplink device through the PCIe uplink interface and can be electrically connected with the plurality of expansion devices through the expansion interfaces, the expansibility of the DCU chip 1 is improved, and meanwhile, the board-level hardware structure can be applied not only to the OAM card form but also to a similar self-defined horizontal card form, and the embodiment does not make too much redundancy.

[0092] Another embodiment of the utility model also provides a board-level hardware structure, which combines Figure 3 the board-level hardware structure and the board-level hardware structure in the above Figure 2 Corresponding embodiment are different in that in the embodiment, a group of SVI serial power voltage adjustment control interfaces are arranged on the DCU chip 1, which are SVI3 interfaces, and the SVI3 interfaces support only the SVI3 protocol. The DCU chip 1 is electrically connected with the first controller 311 and the second controller 312 through the SVI3 interfaces.

[0093] Still another embodiment of the utility model also provides a board-level hardware structure, which combines Figure 4 the board-level hardware structure and the board-level hardware structure in the above Figure 2The difference between the board-level hardware structure in the corresponding embodiment and the board-level hardware structure in the above embodiment is that, in the embodiment, the power conversion tree module 3 has two power conversion units, which are a second power conversion unit 326 and a third power conversion unit 327.

[0094] The second power conversion unit 326 is electrically connected with the first voltage conversion unit 321 and the second voltage conversion unit 322 respectively, and the third power conversion unit 327 is electrically connected with the third voltage conversion unit 323, the fourth voltage conversion unit 324 and a plurality of power units for providing fixed voltages to the DCU chip 1 respectively.

[0095] The second power conversion unit 326 provides a voltage of 5V to the first voltage conversion unit 321 and the second voltage conversion unit 322. The third power conversion unit 327 provides a voltage of 12V to the third voltage conversion unit 323, the fourth voltage conversion unit 324 and a plurality of power units for providing fixed voltages to the DCU chip 1.

[0096] The utility model also has an embodiment which provides a board-level hardware structure, which is combined with Figure 5 The board-level hardware structure is the same as the above Figure 2 The difference between the board-level hardware structure in the corresponding embodiment and the board-level hardware structure in the above embodiment is that, in the embodiment, the power conversion tree module 3 has two power conversion units, which are a second power conversion unit 326 and a third power conversion unit 327.

[0097] The second power conversion unit 326 is electrically connected with the first voltage conversion unit 321 and the second voltage conversion unit 322 respectively, and the third power conversion unit 327 is electrically connected with the third voltage conversion unit 323, the fourth voltage conversion unit 324 and a plurality of power units for providing fixed voltages to the DCU chip 1 respectively.

[0098] The second power conversion unit 326 provides a voltage of 5V to the first voltage conversion unit 321 and the second voltage conversion unit 322. The third power conversion unit 327 provides a voltage of 12V to the third voltage conversion unit 323, the fourth voltage conversion unit 324 and a plurality of power units for providing fixed voltages to the DCU chip 1.

[0099] Meanwhile, in the embodiment, a group of SVI serial power voltage adjustment control interfaces are arranged on the DCU chip 1, which are SVI3 interfaces, and the SVI3 interfaces only support the SVI3 protocol. The DCU chip 1 is electrically connected with the first controller 311 and the second controller 312 through the SVI3 interfaces.

[0100] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the description of the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.

[0101] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0102] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent scope of the present application. It should be pointed out that, for ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, which belongs to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A board level hardware structure, characterized by, The board-level hardware structure comprises a DCU chip, a first OAM standard connector, a second OAM standard connector and a power conversion tree module, the DCU chip is connected with the first OAM standard connector and the second OAM standard connector respectively, and the power conversion tree module is connected with the DCU chip and the first OAM standard connector, and is used for converting an external power connected with the first OAM standard connector and providing the converted power to the DCU chip, wherein the first OAM standard connector is connected with a connector on a mainboard in a pairing mode, and is used for realizing interconnection between the DCU chip and an uplink device on the mainboard, and the second OAM standard connector is connected with other DCU chips, and is used for realizing interconnection between the DCU chips.

2. The board-level hardware structure of claim 1, wherein, The DCU chip is provided with a PCIe uplink interface and a plurality of expansion interfaces. The DCU chip is used for connecting a PCIe uplink device through the PCIe uplink interface and connecting a plurality of expansion devices through the plurality of expansion interfaces.

3. The board-level hardware structure of claim 2, wherein, The plurality of expansion interfaces comprise seven groups of xHCLx8 interfaces. The PCIe uplink interface comprises a group of PCIe x16 interfaces, and the PCIe x16 interfaces support an xHCL protocol.

4. The board-level hardware structure of claim 3, wherein, The PCIe uplink interface further comprises a group of PCIe substitute interfaces. When the PCIe x16 interfaces are connected with external devices supporting the xHCL protocol, the DCU chip is used for connecting the PCIe uplink device through the PCIe substitute interfaces.

5. The board-level hardware structure of claim 1, wherein, The DCU chip is further provided with a MISC signal interface. The MISC signal interface comprises at least one of an SPI interface, an SMBUS interface, a GPIO interface and a power management interface.

6. The board-level hardware structure of claim 1, wherein, The DCU chip is further provided with a core clock interface, a PCIe clock interface and an xHCL clock interface. The core clock interface is used for providing a clock signal for a core of the DCU chip, the PCIe clock interface is used for providing a clock signal for the PCIe uplink interface, and the xHCL clock interface is used for providing a clock signal for a plurality of xHCL interfaces.

7. The board-level hardware structure of claim 1, wherein, The DCU chip is provided with a WAFL management interface. The DCU chip is further used for connecting an expansion device through the WAFL management interface.

8. The board-level hardware structure of claim 1, wherein, The power conversion tree module comprises a controller and a voltage conversion unit. The DCU chip is connected with the controller, the controller is electrically connected with the voltage conversion unit, the voltage conversion unit is electrically connected with the first OAM standard connector and the DCU chip, and the DCU chip adjusts a voltage size output by the voltage conversion unit through the controller to adapt to the DCU chip.

9. The board-level hardware structure of claim 8, wherein, The DCU chip is provided with a plurality of power interfaces. The voltage conversion unit is electrically connected with the plurality of power interfaces.

10. The board-level hardware structure of claim 9, wherein, The power conversion tree module further comprises a first power conversion unit. The voltage conversion unit is connected with the first OAM standard connector through the first power conversion unit. The first OAM standard connector provides a first fixed voltage to the voltage conversion unit through the first power conversion unit.

11. The board-level hardware structure of claim 9, wherein, The power conversion tree module further comprises a second power conversion unit and a third power conversion unit; The voltage conversion unit is electrically connected with the first OAM standard connector through the second power conversion unit and the third power conversion unit respectively; The first OAM standard connector provides a second fixed voltage to the voltage conversion unit through the second power conversion unit and provides a third voltage to the voltage conversion unit through the third power conversion unit.

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