Video time sequence information extraction circuit
By designing a video timing information extraction circuit and utilizing the cooperation of a power supply module, impedance matching module, filtering module, coupling module, and separation module, the problem of low efficiency caused by differences in component parameters was solved, and efficient and stable video timing information extraction was achieved.
Patent Information
- Application Number
- CN202423232850.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-26
AI Technical Summary
In existing technologies, when using basic electronic components to extract video timing information, parameter differences result in long adjustment times and low efficiency, failing to meet user needs.
Design a video timing information extraction circuit, including a power supply module, a video impedance matching module, an input filtering module, an input coupling module, a bias module, and a timing separation module. Through the cooperation of these modules, the circuit automatically completes the input, impedance matching, filtering, and timing information extraction of video signals.
It improves the efficiency and quality of video signal timing information extraction, reduces power consumption, extends service life, and enhances stability and reliability.
Smart Images
Figure CN223613385U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to video processing technical field especially relates to a video time sequence information extraction circuit. BACKGROUND
[0002] With the continuous development of video technology, the demand for video signal processing is also growing. In video signal processing, it is often necessary to extract key timing information from video signals.
[0003] The prior art extracts video timing information by basic electronic components. However, there are certain differences in the parameters of different batches of basic electronic components. Using basic electronic components to extract timing information requires a lot of time to adjust component parameters, resulting in low efficiency of video processing and unable to meet user needs. UTILITY MODEL CONTENT
[0004] Therefore, it is necessary to provide a video timing information extraction circuit to solve the problem of the existing video timing information extraction method.
[0005] A video timing information extraction circuit, comprising: a power module, a video impedance matching module, an input filter module, an input coupling module, a bias module and a timing separation module;
[0006] The video impedance matching module is connected to the input filter module, and the input filter module is connected to the input coupling module and the timing separation module, respectively. The input coupling module, the bias module and the power module are connected to the timing separation module;
[0007] The power module is used to power the timing separation module;
[0008] The video impedance matching module is used to access video signals and match the impedance of the accessed video signals. The video signals after impedance matching are sent to the input filter module;
[0009] The input filter module is used to low-pass filter the video signals, and the video signals after low-pass filtering are sent to the input coupling module;
[0010] The input coupling module is used to filter high-frequency noise in the video signals, and the video signals after filtering high-frequency noise are sent to the timing separation module;
[0011] The timing separation module is used to extract timing information from the video signals, and to control the input filter module according to the type of the video signals;
[0012] The bias module is used to provide a stable working point for the timing separation module.
[0013] In one embodiment, the output current limiting module and the buffer driving module are further included;
[0014] The output current limiting module is connected to the timing separation module, and the buffer driving module is connected to the output current limiting module and the power supply module respectively;
[0015] The timing separation module is further configured to deliver the extracted timing information to the output current limiting module;
[0016] The output current limiting module is configured to limit current and provide the timing information delivered by the timing separation module to the buffer driving module;
[0017] The buffer driving module is configured to perform signal enhancement on the timing information provided by the output current limiting module and provide the timing information to an external circuit;
[0018] The power supply module is further configured to supply power to the buffer driving module.
[0019] In one embodiment, the video impedance matching module includes a first resistor, the input filter module includes a second resistor, a first capacitor, a second capacitor, a triode and a third resistor, and the input coupling module includes a third capacitor;
[0020] One end of the first resistor is configured to access a video signal, and the other end of the first resistor is connected to one end of the second resistor, and the other end of the first resistor is grounded;
[0021] The other end of the second resistor is connected to one end of the first capacitor, one end of the second capacitor and one end of the third capacitor respectively, and the other end of the third capacitor is connected to the timing separation module;
[0022] The other end of the first capacitor is grounded, the other end of the second capacitor is connected to the collector of the triode, the other end of the third capacitor is connected to the timing separation module, the emitter of the triode is grounded, one end of the third resistor is connected to the base of the triode, and the other end of the third resistor is connected to the timing separation module.
[0023] In one embodiment, the timing separation module includes a first chip, and the biasing module includes a fourth resistor;
[0024] A first pin of the first chip is connected to one end of the fourth resistor, a second pin is grounded, a third pin is connected to the positive terminal of the power supply module, a fourth pin is connected to the other end of the third capacitor, a fifth pin is connected to the other end of the third resistor, a sixth pin, a seventh pin, an eighth pin, a ninth pin and a tenth pin are connected to the output current limiting module respectively, and the other end of the fourth resistor is grounded.
[0025] In one of the embodiments, the output current limiting module comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor;
[0026] One end of the fifth resistor is connected to the tenth pin of the first chip, and the other end is connected to an external circuit;
[0027] One end of the sixth resistor is connected to the ninth pin of the first chip, and the other end is connected to the buffer driving module;
[0028] One end of the seventh resistor is connected to the eighth pin of the first chip, and the other end is connected to an external circuit;
[0029] One end of the eighth resistor is connected to the seventh pin of the first chip, and the other end is connected to the buffer driving module;
[0030] One end of the ninth resistor is connected to the sixth pin of the first chip, and the other end is connected to an external circuit.
[0031] In one of the embodiments, the buffer driving module comprises a second chip;
[0032] The second pin and the third pin of the second chip are respectively connected to the other end of the sixth resistor, the fourth pin and the fifth pin are respectively connected to the other end of the eighth resistor, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the thirteenth pin and the fourteenth pin are left floating, the first pin and the twentieth pin are respectively connected to the positive pole of the power module, the tenth pin and the nineteenth pin are respectively connected to the negative pole of the power module, and the fifteenth pin, the sixteenth pin, the seventeenth pin and the eighteenth pin are respectively connected to an external circuit.
[0033] In one of the embodiments, the first chip comprises a video signal type detection unit and a timing information extraction unit, and the video signal type detection unit is connected to the timing information extraction unit.
[0034] The video signal type detection unit is configured to determine type information of a video signal and send the type information to the timing information extraction unit.
[0035] The timing information extraction unit is configured to extract timing information in the video signal according to the type information.
[0036] In one of the embodiments, the first chip adopts LMH1980 or LMH1981.
[0037] In one of the embodiments, the second chip adopts 74HC245.
[0038] In one of the embodiments, the triode is an NPN type triode.
[0039] The video timing information extraction circuit comprises a power module, a video impedance matching module, an input filtering module, an input coupling module, a biasing module and a timing separation module, the video impedance matching module is connected to the input filtering module, the input filtering module is connected to the input coupling module and the timing separation module respectively, and the input coupling module, the biasing module and the power module are connected to the timing separation module respectively. When the video timing information extraction circuit works, the video signal is inputted by the video impedance matching module first, and the inputted video signal is impedance matched, and then the video signal after impedance matching is transmitted to the input filtering module; then the video signal is low-pass filtered by the input filtering module, and then the video signal after low-pass filtering is transmitted to the input coupling module; then the high-frequency noise in the video signal is filtered by the input coupling module, and then the video signal after filtering the high-frequency noise is transmitted to the timing separation module; then the timing information in the video signal is extracted by the timing separation module; the biasing module can provide a stable working point for the timing separation module, the timing separation module can also control the input filtering module according to the type of the video signal, and the power module can supply power for the timing separation module. Through the cooperation of the power module, the video impedance matching module, the input filtering module, the input coupling module, the biasing module and the timing separation module, the video timing information extraction circuit can automatically complete the input of the video signal, the impedance matching of the video signal, the filtering of the video signal, the coupling of the video signal and the extraction of the timing information of the video signal, thereby improving the efficiency and quality of the extraction of the timing information of the video signal. BRIEF DESCRIPTION OF DRAWINGS
[0040] Figure 1 It is a structural schematic view of the video timing information extraction circuit according to an embodiment of the present application.
[0041] Figure 2 It is a structural schematic view of the video timing information extraction circuit according to another embodiment of the present application.
[0042] Figure 3 It is a circuit principle view of the circuit shown in the figure. Figure 2 DETAILED DESCRIPTION
[0043] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.
[0044] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. As used herein the terms "vertical", "horizontal", "left", "right", and the like are merely used for the purpose of illustration and are not intended to be limiting.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0046] The utility model discloses a kind of video time sequence information extraction circuits.
[0047] As Figure 1 As shown in the figure, the video time sequence information extraction circuit includes power module, video impedance matching module, input filter module, input coupling module, bias module and time sequence separation module.
[0048] Video impedance matching module connects input filter module, and input filter module is connected with input coupling module and time sequence separation module respectively, and input coupling module, bias module and power module are connected with time sequence separation module respectively;Power module is used to power supply for time sequence separation module;Video impedance matching module is used to access video signal, and impedance matching is carried out for the video signal accessed, and the video signal after impedance matching is delivered to input filter module;Input filter module is used to carry out low-pass filtering to video signal, and the video signal after low-pass filtering is delivered to input coupling module;Input coupling module is used to filter high-frequency noise in video signal, and the video signal after filtering high-frequency noise is delivered to time sequence separation module;Time sequence separation module is used to extract time sequence information in video signal, and the input filter module is controlled according to the type of video signal;Bias module is used to provide stable operating point for the separation module.
[0049] The video timing information extraction circuit comprises a power module, a video impedance matching module, an input filtering module, an input coupling module, a biasing module and a timing separation module. The video impedance matching module is connected to the input filtering module. The input filtering module is connected to the input coupling module and the timing separation module respectively. The input coupling module, the biasing module and the power module are connected to the timing separation module respectively. When the video timing information extraction circuit is in operation, the video signal is first input into the video impedance matching module, which matches the impedance of the input video signal and then sends the video signal with matched impedance to the input filtering module. Then the input filtering module performs low-pass filtering on the video signal and sends the video signal with low-pass filtered to the input coupling module. Then the input coupling module filters the high-frequency noise in the video signal and sends the video signal with filtered high-frequency noise to the timing separation module. Then the timing separation module extracts the timing information in the video signal. The biasing module provides a stable working point for the timing separation module. The timing separation module can also control the input filtering module according to the type of the video signal. The power module supplies power to the timing separation module. Through the cooperation of the power module, the video impedance matching module, the input filtering module, the input coupling module, the biasing module and the timing separation module, the video timing information extraction circuit can automatically complete the input of the video signal, the impedance matching of the video signal, the filtering of the video signal, the coupling of the video signal and the extraction of the timing information of the video signal, thereby improving the efficiency and quality of the extraction of the timing information of the video signal.
[0050] As shown in Figure 2 The video timing information extraction circuit further comprises an output current limiting module and a buffer driving module. The output current limiting module is connected to the timing separation module. The buffer driving module is connected to the output current limiting module and the power module respectively. The timing separation module is further used to send the extracted timing information to the output current limiting module. The output current limiting module is used to limit the current and provide the timing information sent by the timing separation module to the buffer driving module. The buffer driving module is used to enhance the signal of the timing information provided by the output current limiting module and provide it to the external circuit. The power module is further used to supply power to the buffer driving module.
[0051] Through the current limiting effect of the output current limiting module, the output power consumption of the video timing information extraction circuit is reduced, the heat is reduced, and the service life of the video timing information extraction circuit is prolonged. Further, through the signal enhancement effect of the buffer driving module, the stability and reliability of the video timing information extraction circuit can be improved, and the signal attenuation caused by the external circuit unable to identify the timing information of the video signal can be avoided.
[0052] As shown in Figure 3As shown, the video impedance matching module comprises a first resistor R1, the input filter module comprises a second resistor R2, a first capacitor C1, a second capacitor C2, a triode Q1 and a third resistor R3, and the input coupling module comprises a third capacitor C3; one end of the first resistor R1 is used for connecting the video signal SYNC_IN, one end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the first resistor R1 is grounded; the other end of the second resistor R2 is connected to one end of the first capacitor C1, one end of the second capacitor C2 and one end of the third capacitor C3 respectively, and the other end of the third capacitor C3 is connected to the timing separation module; the other end of the first capacitor C1 is grounded, the other end of the second capacitor C2 is connected to the collector of the triode Q1, the other end of the third capacitor C3 is connected to the timing separation module, the emitter of the triode Q1 is grounded, one end of the third resistor R3 is connected to the base of the triode Q1, and the other end of the third resistor R3 is connected to the timing separation module.
[0053] Preferably, the resistance value of the first resistor R1 is 75Ω. By setting the resistance value of the first resistor R1 to 75Ω, multiple video signal types such as SD (Standard Definition) video and HD (High Definition) video can be compatible. Further, the cut-off frequency of the input filter module is preferably 2.79MHz, the resistance value of the second resistor R2 is 100Ω, the first capacitor C1 is used as a high-frequency noise filter, the first capacitor C1 is selected to be a small capacitor of 0.1uF, and the capacitance value of the second capacitor C2 is 560pF. Further, the triode Q1 is an NPN type triode, and the third capacitor C3 is selected to be a small capacitor of 0.1uF.
[0054] Further, the timing separation module comprises a first chip U1, and the biasing module comprises a fourth resistor R4; the first pin of the first chip U1 is connected to one end of the fourth resistor R4, the second pin is grounded, the third pin is connected to the positive terminal VDD of the power module, the fourth pin is connected to the other end of the third capacitor C3, the fifth pin is connected to the other end of the third resistor R3, the sixth pin, the seventh pin, the eighth pin, the ninth pin and the tenth pin are respectively connected to the output current limiting module, and the other end of the fourth resistor R4 is grounded.
[0055] The first chip U1 can control the conduction and shutdown of the triode Q1 by controlling whether the fifth pin outputs a low level or a high level. Further, when the first chip U1 judges that the type of the video signal is SD video, the triode Q1 is turned on by outputting a high level through the fifth pin, so as to turn on the chroma filter function; when the first chip U1 judges that the type of the video signal is HD video, the triode Q1 is turned off by outputting a low level through the fifth pin, so as to turn off the chroma filter function. By turning on and off the chroma filter function according to different video types, the video timing information extraction circuit has stronger compatibility.
[0056] Preferably, the first chip U1 adopts LMH1980 or LMH1981. The resistance value of the fourth resistor R4 is 10kΩ, and the precision is 1%. The LMH1980 / LMH1981 chip is widely used in video interface processing, especially in application scenarios that require automatic detection of SD, HD and PC video synchronization. Due to its automatic detection function, it can provide higher flexibility and reliability in video processing systems.
[0057] Further, the output current limiting module includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9. One end of the fifth resistor R5 is connected to the tenth pin of the first chip U1, and the other end is connected to the external circuit. One end of the sixth resistor R6 is connected to the ninth pin of the first chip U1, and the other end is connected to the buffer driving module. One end of the seventh resistor R7 is connected to the eighth pin of the first chip U1, and the other end is connected to the external circuit. One end of the eighth resistor R8 is connected to the seventh pin of the first chip U1, and the other end is connected to the buffer driving module. One end of the ninth resistor R9 is connected to the sixth pin of the first chip U1, and the other end is connected to the external circuit. Through the current limiting effect of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9, the output power consumption of the video timing information extraction circuit is reduced, the heat is reduced, and the service life of the video timing information extraction circuit is prolonged.
[0058] Further, the buffer driving module includes a second chip U2. The second pin and the third pin of the second chip U2 are respectively connected to the other end of the sixth resistor R6, the fourth pin and the fifth pin are respectively connected to the other end of the eighth resistor R8, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the thirteenth pin and the fourteenth pin are left floating, the first pin and the twentieth pin are respectively connected to the positive electrode VDD of the power module, the tenth pin and the nineteenth pin are respectively connected to the negative electrode of the power module, and the fifteenth pin, the sixteenth pin, the seventeenth pin and the eighteenth pin are respectively connected to the external circuit.
[0059] Preferably, the second chip U2 adopts 74HC245. The 74HC245 chip is a kind of bidirectional buffer, mainly used for realizing data transmission between two buses. It has the characteristics of high speed, low power consumption, good reliability and strong interface compatibility, and is widely used in microcontroller systems, computer peripherals and communication equipment fields. Through the signal enhancement effect of the second chip U2, the stability and reliability of the video timing information extraction circuit can be improved, and the signal attenuation caused by the external circuit unable to identify the timing information of the video signal can be avoided.
[0060] Further, the first chip U1 comprises a video signal type detection unit and a timing information extraction unit, the video signal type detection unit is connected with the timing information extraction unit; the video signal type detection unit is used for determining type information of the video signal, and sends the type information to the timing information extraction unit; the timing information extraction unit is used for extracting timing information in the video signal according to the type information. Through the mutual cooperation of the video signal type detection unit and the timing information extraction unit, the first chip U1 can automatically detect SD, HD and PC video, so that the video timing information extraction circuit has higher flexibility and reliability.
[0061] The technical features of the above-described embodiments can be combined in any manner. To make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.
[0062] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A video timing information extraction circuit, characterized by comprising: The application relates to a video signal processing circuit, which comprises the following modules: a power module, a video impedance matching module, an input filter module, an input coupling module, a bias module and a time sequence separation module. The video impedance matching module is connected with the input filter module, the input filter module is connected with the input coupling module and the time sequence separation module respectively, and the input coupling module, the bias module and the power module are connected with the time sequence separation module respectively. The power module is used for supplying power for the time sequence separation module. The video impedance matching module is used for connecting a video signal and performing impedance matching on the connected video signal, and the video signal after the impedance matching is transmitted to the input filter module. The input filter module is used for performing low-pass filtering on the video signal, and the video signal after the low-pass filtering is transmitted to the input coupling module. The input coupling module is used for filtering high-frequency noise in the video signal, and the video signal after the filtering of the high-frequency noise is transmitted to the time sequence separation module. The time sequence separation module is used for extracting time sequence information in the video signal and controlling the input filter module according to the type of the video signal. The bias module is used for providing a stable working point for the time sequence separation module. The application further comprises an output current limiting module and a buffer driving module.
2. The video timing information extraction circuit according to claim 1, characterized by, The output current limiting module is connected with the time sequence separation module, and the buffer driving module is connected with the output current limiting module and the power module respectively. The time sequence separation module is further used for transmitting the extracted time sequence information to the output current limiting module. The output current limiting module is used for limiting current and providing the time sequence information transmitted by the time sequence separation module to the buffer driving module. The buffer driving module is used for performing signal enhancement on the time sequence information provided by the output current limiting module and providing the time sequence information to an external circuit. The power module is further used for supplying power for the buffer driving module. The video impedance matching module comprises a first resistor, the input filter module comprises a second resistor, a first capacitor, a second capacitor, a triode and a third resistor, and the input coupling module comprises a third capacitor.
3. The video timing information extraction circuit according to claim 2, wherein One end of the first resistor is used for connecting a video signal, and the other end of the first resistor is connected with one end of the second resistor, and the other end of the first resistor is grounded. The other end of the second resistor is connected with one end of the first capacitor, one end of the second capacitor and one end of the third capacitor respectively, and the other end of the third capacitor is connected with the time sequence separation module. The other end of the first capacitor is grounded, the other end of the second capacitor is connected with the collector of the triode, the other end of the third capacitor is connected with the time sequence separation module, the emitter of the triode is grounded, one end of the third resistor is connected with the base of the triode, and the other end of the third resistor is connected with the time sequence separation module. The time sequence separation module comprises a first chip, and the bias module comprises a fourth resistor.
4. The video timing information extraction circuit according to claim 3, wherein The first pin of the first chip is connected with one end of the fourth resistor, the second pin is connected with the ground, the third pin is connected with the positive terminal of the power module, the fourth pin is connected with the other end of the third capacitor, the fifth pin is connected with the other end of the third resistor, the sixth pin, the seventh pin, the eighth pin, the ninth pin and the tenth pin are connected with the output current limiting module respectively, and the other end of the fourth resistor is connected with the ground.
5. The video timing information extraction circuit according to claim 4, characterized by, The output current limiting module comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor. One end of the fifth resistor is connected with the tenth pin of the first chip, and the other end is connected with an external circuit. One end of the sixth resistor is connected with the ninth pin of the first chip, and the other end is connected with the buffer driving module. One end of the seventh resistor is connected with the eighth pin of the first chip, and the other end is connected with an external circuit. One end of the eighth resistor is connected with the seventh pin of the first chip, and the other end is connected with the buffer driving module. One end of the ninth resistor is connected with the sixth pin of the first chip, and the other end is connected with an external circuit.
6. The video timing information extraction circuit according to claim 5, wherein, The buffer driving module comprises a second chip. The second pin and the third pin of the second chip are connected with the other end of the sixth resistor respectively, the fourth pin and the fifth pin are connected with the other end of the eighth resistor respectively, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the eleventh pin, the twelfth pin, the thirteenth pin and the fourteenth pin are left floating, the first pin and the twentieth pin are connected with the positive terminal of the power module respectively, the tenth pin and the nineteenth pin are connected with the negative terminal of the power module respectively, and the fifteenth pin, the sixteenth pin, the seventeenth pin and the eighteenth pin are connected with an external circuit.
7. The video timing information extraction circuit according to any one of claims 4 to 6, wherein, The first chip comprises a video signal type detection unit and a timing information extraction unit, and the video signal type detection unit is connected with the timing information extraction unit. The video signal type detection unit is used for determining type information of a video signal and sending the type information to the timing information extraction unit. The timing information extraction unit is used for extracting timing information in the video signal according to the type information.
8. The video timing information extraction circuit according to claim 7, wherein, The first chip adopts an LMH1980 or an LMH1981.
9. The video timing information extraction circuit according to claim 6, wherein, The second chip adopts a 74HC245.
10. The video timing information extraction circuit according to any one of claims 3 to 6, wherein, The transistor adopts an NPN type transistor.