Miniaturized high-speed signal processing SiP integrated device

Abstract

The utility model discloses a miniaturized high-speed signal processing SiP integrated device, which belongs to the technical field of electronics and comprises a broadband high-speed signal processing SiP micro module, a power conversion module, a clock generation and distribution module, an ADC / DAC front-end module, a photoelectric conversion module and a data input / output interface module. The broadband high-speed signal processing SiP micromodule comprises a clock input port, a digital-analog / analog-digital converter, an FPGA (Field Programmable Gate Array), a FLASH, a GTH interface and an IO (Input / Output) interface. According to the utility model, the integration density of traditional signal processing hardware is improved, miniaturization, standardization and modularization of high-speed signal processing hardware are realized, unmanned and lightweight development requirements of equipment in the field of communication and radar electronic countermeasure can be met, and the high engineering application value is realized.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, specifically to a miniaturized high-speed signal processing SiP integrated device. Background Technology

[0002] Traditional broadband high-speed digital-to-analog signal processing devices are mainly based on high-speed ADCs, high-speed DACs, FPGAs, Flash memory, and resistors and capacitors, using FR4 circuit boards as the carrier and constructing the signal processing circuit board through cascading. Electronic components are soldered onto the FR4 circuit board manually or through reflow soldering. This circuit board and implementation method are simple, but the overall structure is large, with low integration, low reliability, and poor standardization, which can no longer meet the current development requirements of miniaturization, modularization, and standardization of systems.

[0003] The failure of Moore's Law has given rise to System-in-a-Package (SiP) technology, which has become one of the important approaches to microsystem integration. SiP technology integrates important or critical components into a single packaged module, achieving high integration, high reliability, and high-efficiency production of micro-modules. Full-function devices based on SiP micro-module integration can better meet the development needs of equipment miniaturization, standardization, and modularization. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a miniaturized high-speed signal processing SiP integrated device, which improves the integration density of traditional signal processing hardware and realizes the miniaturization, standardization and modularization of high-speed signal processing hardware. It can meet the needs of unmanned and lightweight development of equipment in the fields of communication and radar electronic countermeasures, and has strong engineering application value.

[0005] The technical solution of this utility model is as follows:

[0006] A miniaturized high-speed signal processing SiP integrated device includes:

[0007] The broadband high-speed signal processing SiP micro-module includes a power conversion module, a clock generation and distribution module, an ADC / DAC front-end module, a photoelectric conversion module, and a data input / output interface module. The broadband high-speed signal processing SiP micro-module includes a clock input port, a digital-to-analog converter module, a GTH interface, and an IO interface.

[0008] The power conversion module's power input terminal is connected to an external power input terminal, accepts external power input, and converts it into various DC power supplies required by the SiP integrated device to provide power to the device.

[0009] The output of the clock generation and distribution module is connected to the clock input port of the broadband high-speed signal processing SiP micromodule to complete the generation and distribution of the clock.

[0010] The signal input / output terminals of the ADC / DAC front-end module are connected to the signal input / output terminals of the digital-to-analog converter module.

[0011] The photoelectric conversion module is connected to the GTH interface of the broadband high-speed signal processing SiP micro-module to complete the data interaction between the SiP integrated device and the external optical fiber signal.

[0012] The data input / output interface is connected to the GTH interface 2 and IO interface of the SiP micromodule to complete the data interaction between the SiP integrated device and the external high-speed serial bus and IO circuit signals.

[0013] Furthermore, the broadband high-speed signal processing SiP micromodule specifically includes an ADC chip, an FPGA chip, a DAC chip, and a Flash chip;

[0014] The FPGA configuration uses bare Flash chips that have been converted to FC form through RDL rewiring and are directly connected to the BANK0 section of the FPGA bare chip; the ADC chip uses a finished ADC chip and the DAC chip uses bare chips, which are respectively connected to the GTH interface and BANK I / O section of the FPGA bare chip. At the same time, the FPGA provides GTH and I / O interfaces as well as a clock input port for interconnection with external modules.

[0015] Furthermore, the power conversion module includes: DC / DC power chips D1, D2, D3, and D4, providing 1.0V, 1.8V, and 3.3V respectively, and 1.8V and 3.3V respectively; and LDO power chips N1, N2, N3, and N4, providing 1.2V, 3.3V, 2.5V, and 1.25V respectively.

[0016] Power chip D1 connects to the AVDD 1.0V power port of the SiP micromodule; power chip D2 connects to the VDD 1.8V power port of the SiP micromodule, the 1.8V power port of power chip N1, the 3.6V port of power chip N2, and the 3.3V power port of the photoelectric conversion module; power chip D3 connects to the 1.8V and 3.3V power ports of the SiP micromodule, the 3.0V port of power chip N3, and the 1.5V port of power chip N4; power chip D4 connects to the 1.8V and 3.3V power ports of the SiP micromodule.

[0017] Power chips N1, N3, and N4 are connected to the 1.2V, 2.5V, and 1.25V power ports of the SiP micromodule, respectively; power chip N2 is connected to the 3.3V power port of the clock generation and distribution module.

[0018] Furthermore, the clock generation and distribution module includes three parts: a reference clock, a clock buffer, and a phase-locked loop (PLL). The reference clock and the clock buffer are connected to generate multiple clocks and distribute them to the PLL and the SiP micromodule. The PLL is configured by the SiP micromodule to perform frequency multiplication and division operations on the clock sent from the clock buffer to generate the corresponding JESD204B reference clock, ADC sampling reference clock, DAC sampling reference clock, and SYS_REF system-associated reference clock, which are then sent to the SiP micromodule.

[0019] Furthermore, the ADC / DAC front-end module includes: an RF connector, an RF transformer, a π-attenuation circuit, a filter, a 50Ω RC matching circuit, and an amplifier. In the ADC front-end link, the RF connector is connected to the RF transformer, the transformer is connected to the 50Ω RC matching circuit, and the matching circuit is connected to the SiP micromodule ADC input interface. In the DAC front-end link, the SiP micromodule is connected to the RF transformer, the transformer is connected to the π-attenuation circuit, and then the signal is connected to the RF amplifier after passing through the filter. The signal is amplified and then output through the RF connector.

[0020] Furthermore, the photoelectric conversion module includes a JESD204B data interface, and the SiP micromodule is interconnected with the JESD204B data interface of the photoelectric conversion module through a GTH interface.

[0021] Furthermore, the data input / output interface includes a GTH interface 3 and a general IO interface. The GTH interface 3 is interconnected with the photoelectric conversion module and the VPX connector. The general IO interface is interconnected with the photoelectric conversion module, the clock phase-locked loop, and the VPX connector.

[0022] Furthermore, the generation and distribution of the completed clock specifically involves the generation and distribution of the high-speed ADC / DAC sampling clock, the high-speed serial bus reference clock, the fiber optic data communication reference clock, and the digital signal processing reference clock.

[0023] Furthermore, the signal input / output terminals of the digital-to-analog / analog-to-digital converter module include analog signal output terminals and digital signal input terminals.

[0024] Furthermore, the digital-to-analog / analog-to-digital conversion module includes 8 ADCs and 2 DACs. The 2 DACs are connected to the analog signal output terminal and to the analog signal input terminal of the ADC / DAC front-end module. The 8 ADCs are connected to the digital signal input terminal and to the digital signal output terminal of the ADC / DAC front-end module.

[0025] Compared with existing technologies, the beneficial effects of this utility model are:

[0026] (1) This utility model constructs a miniaturized high-speed signal processing SiP integrated device, which has high-speed signal processing capability and improves the integration density of traditional signal processing hardware. It realizes the miniaturization, standardization and modularization of high-speed signal processing hardware, meets the needs of unmanned and lightweight development of equipment in the fields of communication and radar electronic countermeasures, and can solve the problems of large size, poor standardization, low integration, low reliability and low yield of existing high-speed digital signal processing devices. It has strong engineering application value.

[0027] (2) The device of this utility model has been tested and found that it can achieve 8-channel synchronous sampling and 2-channel DAC output at a sampling rate of 1 GSPS. Its performance indicators are as follows:

[0028] Sampling reception: SNR≥55dBFS, SFDR≥65dBFS, sampling bit width≥14 bits;

[0029] Signal generation: Output power ≥ -3dBm, harmonic suppression ≥ 50dBc, spurious suppression ≥ 55dBc, noise floor ≤ -100dBm;

[0030] (3) Based on SiP technology integration, the size of the device can be reduced from the traditional VPX standard 6U module to half the area of ​​the 3U module, saving more than 70% of the circuit area.

[0031] (4) The device of this utility model adopts high-speed signal processing SiP integrated construction, realizing the miniaturization and standardization design of broadband high-speed signal processing system. At the same time, the structural design of the device can reduce the difficulty of process implementation, shorten the processing cycle, improve the production yield, and facilitate its widespread use in engineering. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the miniaturized high-speed signal processing SiP integrated device of this utility model.

[0033] Figure 2 This is a schematic diagram of the internal structure of the broadband high-speed signal processing SiP micromodule of this utility model.

[0034] Figure 3 This is a connection diagram of the power conversion module of this utility model;

[0035] Figure 4 This is a schematic diagram showing the connection of the clock generation and distribution module of this utility model;

[0036] Figure 5 This is a schematic diagram of the ADC / DAC front-end module connection of this utility model;

[0037] Figure 6 This is a schematic diagram of the connection of the photoelectric conversion module of this utility model;

[0038] Figure 7 This is a schematic diagram of the data input / output interface of this utility model;

[0039] Figure 8 This is a circuit diagram of the miniaturized high-speed signal processing SiP integrated device of this utility model. Detailed Implementation

[0040] The technical solution of this utility model is further described in detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to what is described below. Any feature disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is merely one example of a series of equivalent or similar features.

[0041] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0042] Before describing the embodiments, some necessary terms need to be explained. For example:

[0043] If terms such as "first" and "second" are used to describe various elements in this application, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of this utility model. It should be understood that when an element is referred to as "connected" or "linked" to another element, it may be directly connected or directly linked to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly linked" to another element, there is no intermediate element.

[0044] The various terms appearing in this application are used for the purpose of describing particular embodiments only and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0045] When the terms “comprising” and / or “including” are used in this specification, these terms indicate the presence of the said feature, integral, step, operation, element and / or component, but do not exclude the presence and / or addition of more than one other feature, integral, step, operation, element, component and / or group thereof.

[0046] In a preferred embodiment, the miniaturized high-speed signal processing SiP integrated device provided by this utility model mainly includes a broadband high-speed signal processing SiP micro-module, a power conversion module, a clock generation and distribution module, an ADC / DAC front-end module, a photoelectric conversion module, and a data input / output interface, such as... Figure 1 As shown in the diagram. The functions and connections of each module are as follows: The power conversion module receives external power input and converts it into various DC power supplies required by the SiP integrated device to power the device; the clock generation and distribution module is used to generate and distribute high-speed ADC / DAC sampling clocks, high-speed serial bus reference clocks, fiber optic data communication reference clocks, and digital signal processing reference clocks; this module is connected to the clock input port of the SiP micromodule; the ADC / DAC front-end module mainly completes the matching, coupling, filtering, and impedance transformation of external input RF analog signals, and the impedance transformation, coupling, filtering, and amplification of output RF analog signals; it is connected to the SiP micromodule; the optoelectronic conversion module mainly completes the electro-optic and optoelectronic conversion of FPGA-related high-speed serial signals; it is connected to the GTH interface of the SiP micromodule to complete the data interaction between the integrated device and external fiber optic signals; the data input / output interface is connected to the GTH and IO interfaces of the SiP micromodule, mainly completing the data interaction between the integrated device and external high-speed serial bus and IO circuit signals.

[0047] Building upon the above embodiments, the broadband high-speed signal processing SiP micromodule further comprises four finished ADC chips, one FPGA die, two DAC dies, and one Flash die. The connection relationships are as follows: the FPGA configuration SPI uses a bare Flash die, which is converted from WB format to FC format via RDL rewiring and directly connected to the BANK0 section of the FPGA die. The ADCs are finished chips, and the DACs are bare dies, connected to the GTH interface and BANK I / O section of the FPGA die, respectively. The SiP micromodule also provides GTH and I / O interfaces, as well as a clock input port for external interconnection. The broadband high-speed signal processing SiP micromodule connection is as follows: Figure 2 As shown.

[0048] More specifically, the overall circuit implementation of the miniaturized high-speed signal processing SiP integrated device according to the embodiments of this utility model is as follows: Figure 8As shown. Among them, in the broadband high-speed signal processing SiP micro-module, the main control FPGA uses one domestic SMQ7VX690T bare die (with performance similar to the imported V7-690T), the ADC converter uses four domestic SAD9680 finished chips, the DAC converter uses two domestic JAD9739 bare dies, and the Flash memory uses one domestic MX25U51245GWS100 bare die. The SiP micromodule uses a flat architecture to flip-chip solder ADC chips, FPGA bare dies, and DAC bare dies onto the front side of the plastic package substrate. The Flash bare die has its pads led out to the back side of the redistribution layer based on the redistribution layer, and then fanned out by BGA pads to form a Flash RDL micro-assembly with a PBGA80 package. It is then flip-chip soldered onto a 10-layer high-density plastic package substrate. Resistors and capacitors are surface-mount soldered to the front side of the plastic package substrate, and the BGA pads on the back side of the plastic package substrate are fanned out by external BGA solder balls to form a broadband high-speed signal processing SiP micromodule with dimensions of 45mm*45mm*3.72mm3 and a PBGA1927 package.

[0049] Based on the above embodiments, the power conversion module further includes DC / DC power chips (D1\D2\D3\D4) providing 1.0V / 1.8V / 3.3V&1.8V / 3.3V&1.8V respectively, and LDO power chips (N1\N2\N3\N4) providing 1.2V / 3.3V / 2.5V / 1.25V respectively. The connection relationships are as follows: Power chip D1 is connected to the SiP micromodule's AVDD 1.0V; power chip D2 is connected to the SiP micromodule's VDD 1.8V, power chip N1's 1.8V, power chip N2's 3.6V, and the photoelectric conversion module's 3.3V; power chip D3 is connected to the SiP micromodule's 1.8V and 3.3V, power chip N3's 3.0V, and power chip N4's 1.5V; power chip D4 is connected to the SiP micromodule's 1.8V and 3.3V; power chips N1, N3, and N4 are connected to the SiP micromodule's 1.2V, 2.5V, and 1.25V, respectively; power chip N2 is connected to the clock generation and distribution module's 3.3V; the connection relationships are as follows. Figure 3 As shown.

[0050] More specifically, in the power conversion module, one domestically produced SM4630MPY DC / DC power chip can generate two power channels to complete D1; three SM4644MPY chips can generate six power channels to complete D2, D3, and D4; and four SM74401RGW LDO chips can generate four power channels to complete N1, N2, N3, and N4. The DC / DC power conversion circuit converts the +12V input power into the required power, and the LDO converts the DC / DC converted power into a low-ripple power supply.

[0051] Based on the above embodiments, the clock generation and distribution module further selects the domestically produced temperature-compensated crystal oscillator TC75B-NAGHC-20MHz as the clock source, the clock buffer adopts the domestically produced GM8545 from Zhenxin Technology, and the phase-locked loop adopts the domestically produced SM7044.

[0052] More specifically, the clock generation and distribution module comprises three parts: a reference clock, a clock buffer, and a phase-locked loop (PLL). The reference clock and clock buffer are connected, generating multiple clock signals which are distributed to the PLL and the SiP micromodule. The PLL circuit is configured by the SiP micromodule, which performs frequency multiplication and division operations on the clock signal from the clock buffer. It generates the corresponding JESD204B reference clock, ADC sampling reference clock, DAC sampling reference clock, and SYS_REF system-associated reference clock as needed, and sends them to the SiP micromodule. Their connections are as follows: Figure 4 As shown.

[0053] Building upon the above embodiments, the ADC / DAC front-end module further includes an RF connector, an RF transformer, a π-attenuation circuit, a filter, a 50Ω RC matching circuit, an amplifier, and an attenuator. The connections are as follows: In the ADC front-end link, the RF connector connects to the RF transformer, the transformer connects to the 50Ω RC matching circuit, and the matching circuit connects to the SiP micromodule's ADC input interface; in the DAC front-end link, the SiP micromodule connects to the RF transformer, the transformer connects to the π-attenuation circuit, and then, after passing through the filter, connects to the RF amplifier. The amplified signal then enters the RF connector output. The connections are as follows: Figure 5 As shown.

[0054] More specifically, in the ADC / DAC front-end module, the domestic SMP-KWHD RF connector is selected as the input and output interface of the RF signal, the transformer of model JRFT-1-1T-A is selected, the matching circuit is composed of 0603 packaged resistors and capacitors, the π attenuation circuit is composed of 0603 resistors, the filter is ZHLF-530, and the amplifier is the domestic BR9112.

[0055] Based on the above embodiments, the photoelectric conversion module further includes a photoelectric conversion module, a SiP micromodule that configures the operating parameters of the photoelectric conversion module through an IO interface, and an interconnection between the SiP micromodule and the JESD204B data interface of the photoelectric conversion module through a GTH high-speed interface, as shown in the diagram. Figure 6 As shown.

[0056] More specifically, the photoelectric conversion module uses the domestically produced JM200Z-12M8123500-T5REL045.

[0057] Building upon the above embodiments, the data input / output interface further includes a high-speed GTH interface and a general-purpose I / O interface. The GTH interface is interconnected with the photoelectric conversion module and the VPX connector, while the general-purpose I / O interface is interconnected with the photoelectric conversion module, the clock phase-locked loop, and the VPX connector. The connection relationships are as follows: Figure 7 As shown.

[0058] More specifically, the data input / output interface is implemented using domestically produced ruggedized VPX connectors, model number: VPX-51T8aAgp8AAgD8-B-02.

[0059] In summary, the high-speed signal processing implementation process of the miniaturized high-speed signal processing SiP integrated device provided by this utility model is as follows: the power conversion module provides various DC / DC power supply conversions according to the device's requirements; the clock generation and distribution module generates various clock signals according to the requirements of the ADC sampling rate, DAC sampling rate, photoelectric conversion module, and data input / output interface; the ADC / DAC front-end module completes the coupling impedance matching of the front-end RF input analog signal, and simultaneously completes the coupling impedance matching, attenuation, filtering, and amplification of the output RF analog signal; the input RF analog signal can be sampled by up to 8 channels of analog RF signal ADC by the SiP micro-module and then sent to the FPGA for signal preprocessing; at the same time, the SiP micro-module can use the FPGA to complete the digital synthesis of up to 2 channels of signal and generate analog RF signal output through DAC; the photoelectric conversion module and data input / output interface can complete the data information interaction between this device and external devices according to the project's usage requirements.

[0060] Based on the miniaturized high-speed signal processing SiP integrated device provided by this utility model, it can capture relevant signals with full probability within a certain frequency band for detection and identification, high-speed frequency hopping splicing, demodulation and decoding, multi-channel data fusion, and broadband high-speed signal processing functions such as rapid waveform generation.

[0061] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

Claims

1. A miniaturized high-speed signal processing SiP integrated device, characterized in that, include: The broadband high-speed signal processing SiP micro-module includes a power conversion module, a clock generation and distribution module, an ADC / DAC front-end module, a photoelectric conversion module, and a data input / output interface module. The broadband high-speed signal processing SiP micro-module includes a clock input port, a digital-to-analog / analog-to-digital conversion module, a GTH interface, and an IO interface. The power conversion module's power input terminal is connected to an external power input terminal, accepts external power input, and converts it into various DC power supplies required by the SiP integrated device to provide power to the device. The output of the clock generation and distribution module is connected to the clock input port of the broadband high-speed signal processing SiP micromodule to complete the generation and distribution of the clock. The signal input / output terminals of the ADC / DAC front-end module are connected to the signal input / output terminals of the digital-to-analog / analog-to-digital converter module. The photoelectric conversion module is connected to the GTH interface of the broadband high-speed signal processing SiP micro-module to complete the data interaction between the SiP integrated device and the external optical fiber signal. The data input / output interface module is connected to the GTH interface 2 and IO interface of the SiP micromodule to complete the data interaction between the SiP integrated device and the external high-speed serial bus and IO circuit signals.

2. The miniaturized high-speed signal processing SiP integrated device according to claim 1, characterized in that, The broadband high-speed signal processing SiP micromodule specifically includes an ADC chip, an FPGA chip, a DAC chip, and a Flash chip. The FPGA configuration uses bare Flash chips that have been converted to FC form through RDL rewiring and are directly connected to the BANK0 section of the FPGA bare chip; the ADC chip uses a finished ADC chip and the DAC chip uses bare chips, which are respectively connected to the GTH interface and BANK I / O section of the FPGA bare chip. At the same time, the FPGA provides GTH and I / O interfaces as well as a clock input port for interconnection with external modules.

3. The miniaturized high-speed signal processing SiP integrated device according to claim 2, characterized in that, The power conversion module includes: DC / DC power chips D1, D2, D3, and D4, providing 1.0V, 1.8V, 3.3V, and 1.8V respectively; and LDO power chips N1, N2, N3, and N4, providing 1.2V, 3.3V, 2.5V, and 1.25V respectively. Power chip D1 connects to the AVDD 1.0V power port of the SiP micromodule; power chip D2 connects to the VDD 1.8V power port of the SiP micromodule, the 1.8V power port of power chip N1, the 3.6V port of power chip N2, and the 3.3V power port of the photoelectric conversion module; power chip D3 connects to the 1.8V and 3.3V power ports of the SiP micromodule, the 3.0V port of power chip N3, and the 1.5V port of power chip N4; power chip D4 connects to the 1.8V and 3.3V power ports of the SiP micromodule. Power chips N1, N3, and N4 are connected to the 1.2V, 2.5V, and 1.25V power ports of the SiP micromodule, respectively; power chip N2 is connected to the 3.3V power port of the clock generation and distribution module.

4. The miniaturized high-speed signal processing SiP integrated device according to claim 1, characterized in that, The clock generation and distribution module includes three parts: a reference clock, a clock buffer, and a phase-locked loop (PLL). The reference clock and the clock buffer are connected to generate multiple clocks and distribute them to the PLL and the SiP micromodule. The PLL is configured by the SiP micromodule to perform frequency multiplication and division operations on the clock sent from the clock buffer to generate the corresponding JESD204B reference clock, ADC sampling reference clock, DAC sampling reference clock, and SYS_REF system-associated reference clock, which are then sent to the SiP micromodule.

5. The miniaturized high-speed signal processing SiP integrated device according to claim 1, characterized in that, The ADC / DAC front-end module includes: an RF connector, an RF transformer, a π-attenuation circuit, a filter, a 50Ω RC matching circuit, and an amplifier. In the ADC front-end link, the RF connector is connected to the RF transformer, the transformer is connected to the 50Ω RC matching circuit, and the matching circuit is connected to the SiP micromodule ADC input interface. In the DAC front-end link, the SiP micromodule is connected to the RF transformer, the transformer is connected to the π-attenuation circuit, and then the signal is connected to the RF amplifier after passing through the filter. The signal is amplified and then output through the RF connector.

6. The miniaturized high-speed signal processing SiP integrated device according to claim 1, characterized in that, The photoelectric conversion module includes a JESD204B data interface, and the SiP micro-module is interconnected with the JESD204B data interface of the photoelectric conversion module through a GTH interface.

7. The miniaturized high-speed signal processing SiP integrated device according to claim 4, characterized in that, The data input / output interface module includes a GTH interface 3 and a general IO interface. The GTH interface 3 is interconnected with the photoelectric conversion module and the VPX connector. The general IO interface is interconnected with the photoelectric conversion module, the clock phase-locked loop, and the VPX connector.

8. The miniaturized high-speed signal processing SiP integrated device according to claim 1, characterized in that, The generation and distribution of the completed clocks specifically involves the generation and distribution of high-speed ADC / DAC sampling clocks, high-speed serial bus reference clocks, fiber optic data communication reference clocks, and digital signal processing reference clocks.

9. The miniaturized high-speed signal processing SiP integrated device according to claim 2, characterized in that, The signal input / output terminals of the digital-to-analog / analog-to-digital converter module include analog signal output terminals and digital signal input terminals.

10. The miniaturized high-speed signal processing SiP integrated device according to claim 9, characterized in that, The digital-to-analog / analog-to-digital conversion module includes 8 ADCs and 2 DACs. The 2 DACs are connected to the analog signal output terminal and to the analog signal input terminal of the ADC / DAC front-end module. The 8 ADCs are connected to the digital signal input terminal and to the digital signal output terminal of the ADC / DAC front-end module.

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