Level conversion circuit

Abstract

The utility model discloses a level conversion circuit. The level conversion circuit comprises an input stage, a latch stage and an output stage, the input stage is used for performing level conversion on a first input signal and a second input signal to generate a first output signal from a second voltage domain, and outputting the first output signal to a first output node or a second output node; the latch stage is used for receiving and latching the first output signal and generating corresponding output signals from a second voltage domain on a first output node and a second output node; the output stage outputs a third input signal and a fourth input signal of the second voltage domain based on the control of the output signal. According to the level conversion circuit provided by the utility model, the input stage receives the signal of the first voltage domain, and the latch stage and the output stage are matched to output the signal of the second voltage domain, so that signal conversion of different voltage domains is realized; the level conversion circuit is suitable for level conversion between a fixed level domain and a floating level domain.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and specifically relates to a level conversion circuit. Background Technology

[0002] A level shifter is a circuit that spans different voltage domains, enabling the conversion of signals from one voltage domain to another in multi-voltage domain designs. The voltage domains involved vary across different system applications, and traditional level shifters present significant challenges in converting between floating voltage domains.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a level conversion circuit that can realize signal conversion between fixed voltage domain and floating voltage domain, between fixed voltage domain and fixed voltage domain, and between floating voltage domain and floating voltage domain.

[0005] To achieve the above objectives, a specific embodiment of this utility model provides a level conversion circuit, including: an input stage, a latching stage, and an output stage.

[0006] The input stage has a first output node and a second output node. The input stage is used to receive a first input signal and a second input signal from a first voltage domain and a third input signal from a second voltage domain, to perform level conversion on the first input signal and the second input signal to generate a first output signal from the second voltage domain, and to output the first output signal to the first output node or the second output node. The latching stage is connected to the first output node and the second output node of the input stage and a fourth input signal from the second voltage domain. It is used to receive and latch the first output signal and generate corresponding output signals from the second voltage domain at the first output node and the second output node. The output stage is connected to the first output node, the second output node, and the third and fourth input signals of the second voltage domain to output the third and fourth input signals of the second voltage domain based on the control of the output signals at the first output node and the second output node.

[0007] In one or more embodiments of this utility model, the input stage includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first current limiting unit, and a second current limiting unit;

[0008] The control terminal of the first transistor is used to receive a first input signal, the first terminal of the first transistor is used to receive a reference voltage, the second terminal of the first transistor is connected to the first terminal of the first current limiting unit, the second terminal of the second current limiting unit is connected to the second terminal of the second transistor, the control terminal of the second transistor is used to receive a third input signal, the first terminal of the second transistor is connected to the first output node, the control terminal of the third transistor is used to receive a second input signal, the first terminal of the third transistor is used to receive a reference voltage, the second terminal of the third transistor is connected to the first terminal of the second current limiting unit, the second terminal of the second current limiting unit is connected to the second terminal of the fourth transistor, the control terminal of the fourth transistor is used to receive a third input signal, and the first terminal of the fourth transistor is connected to the second output node.

[0009] In one or more embodiments of this utility model, the first current limiting unit includes a first resistor, a first terminal of the first resistor being connected to a second terminal of a first transistor, and a second terminal of the first resistor being connected to a second terminal of a second transistor; and / or

[0010] The second current limiting unit includes a second resistor, the first end of which is connected to the second end of the third transistor, and the second end of which is connected to the second end of the fourth transistor.

[0011] In one or more embodiments of the present invention, the latch stage includes a fifth transistor and a sixth transistor, wherein the control terminal of the fifth transistor and the second terminal of the sixth transistor are connected to a second output node, the control terminal of the sixth transistor and the second terminal of the fifth transistor are connected to a first output node, and the first terminal of the fifth transistor and the first terminal of the sixth transistor are connected to a fourth input signal.

[0012] In one or more embodiments of the present invention, the output stage includes a first output unit and a second output unit. The first output unit is connected to a first output node and a third input signal and a fourth input signal of a second voltage domain. The second output unit is connected to a second output node and a third input signal and a fourth input signal of a second voltage domain. The first output unit outputs the third input signal and the fourth input signal based on the control of the output signal on the first output node, and the second output unit outputs the third input signal and the fourth input signal based on the control of the output signal on the second output node, respectively.

[0013] In one or more embodiments of the present invention, the first output unit includes a first inverter and a second inverter connected in series.

[0014] In one or more embodiments of the present invention, the second output unit includes a third inverter and a fourth inverter connected in series.

[0015] In one or more embodiments of this utility model, the first output unit includes a first inverter and a second inverter connected in series, the second output unit includes a third inverter and a fourth inverter connected in series, and the output stage further includes a first coupling unit and a second coupling unit. The first end of the first coupling unit is connected to the input end of the first inverter and the first output node, the second end of the first coupling unit is connected to the output end of the third inverter and the input end of the fourth inverter, the first end of the second coupling unit is connected to the output end of the first inverter and the input end of the second inverter, and the second end of the second coupling unit is connected to the second output node and the input end of the third inverter.

[0016] In one or more embodiments of the present invention, the first coupling unit includes a first capacitor, and / or the second coupling unit includes a second capacitor.

[0017] In one or more embodiments of the present invention, the first coupling unit includes a third resistor, and / or the second coupling unit includes a fourth resistor.

[0018] Compared with the prior art, the level conversion circuit of this utility model receives the signal of the first voltage domain through the input stage and outputs the signal of the second voltage domain through the cooperation of the latch stage and the output stage, thereby realizing the signal conversion between different voltage domains. The level conversion circuit of this utility model is applicable to level conversion between both fixed and floating level domains. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of a level conversion circuit in one embodiment. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0022] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0023] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0024] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0025] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0026] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0027] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0028] like Figure 1 As shown in the figure, a level conversion circuit in this embodiment of the present invention includes: an input stage, a latching stage, and an output stage.

[0029] The input stage has a first output node Q1 and a second output node Q2. The input stage is used to receive a first input signal AVDDL and a second input signal AVSSL from a first voltage domain and a third input signal AVDDH from a second voltage domain. The input stage performs level conversion on the first input signal AVDDL and the second input signal AVSSL to generate a first output signal from the second voltage domain, and outputs the first output signal to the first output node Q1 or the second output node Q2.

[0030] The latching stage is connected to the first output node Q1 and the second output node Q2 of the input stage and the fourth input signal AVSSH from the second voltage domain. It is used to receive and latch the first output signal and generate corresponding output signals from the second voltage domain at the first output node Q1 and the second output node Q2.

[0031] The output stage is connected to the first output node Q1, the second output node Q2, and the third input signal AVDDH and the fourth input signal AVSSH of the second voltage domain, so as to output the third input signal AVDDH and the fourth input signal AVSSH of the second voltage domain based on the control of the output signals on the first output node Q1 and the second output node Q2.

[0032] like Figure 1 As shown, in one embodiment, the input stage includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first current limiting unit, and a second current limiting unit.

[0033] The control terminal of the first transistor M1 (i.e., the first input terminal VIP of the input stage for receiving input signals from the first voltage domain) is used to receive the first input signal AVDDL. The first terminal of the first transistor M1 is used to receive a reference voltage. In one embodiment, the reference voltage is the first input signal AVDDL from the first voltage domain. The second terminal of the first transistor M1 is connected to the first terminal of the first current limiting unit. The second terminal of the second current limiting unit is connected to the second terminal of the second transistor M2. The control terminal of the second transistor M2 is used to receive the third input signal AVDDH. The first terminal of the second transistor M2 is connected to the first output node Q1. The control terminal of the third transistor M3 (i.e., the second input terminal VIN of the input stage for receiving input signals from the first voltage domain) is used to receive the second input signal AVSSL. The first terminal of the third transistor M3 is used to receive the reference voltage. The second terminal of the third transistor M3 is connected to the first terminal of the second current limiting unit. The second terminal of the second current limiting unit is connected to the second terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is used to receive the third input signal AVDDH. The first terminal of the fourth transistor M4 is connected to the second output node Q2.

[0034] In other embodiments, the first current limiting unit and the second current limiting unit may not be provided, and the second transistor M2 and the fourth transistor M4 may not be provided.

[0035] In one embodiment, the first current limiting unit includes a first resistor R1, and the second current limiting unit includes a second resistor R2. The first terminal of the first resistor R1 is connected to the second terminal of the first transistor M1, and the second terminal of the first resistor R1 is connected to the second terminal of the second transistor M2. The first terminal of the second resistor R2 is connected to the second terminal of the third transistor M3, and the second terminal of the second resistor R2 is connected to the second terminal of the fourth transistor M4. In other embodiments, the first current limiting unit and the second current limiting unit may be other circuit structures.

[0036] like Figure 1 As shown, in one embodiment, the latch stage includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the fifth transistor M5 and the second terminal of the sixth transistor M6 are connected to the second output node Q2. The control terminal of the sixth transistor M6 and the second terminal of the fifth transistor M5 are connected to the first output node Q1. The first terminal of the fifth transistor M5 and the first terminal of the sixth transistor M6 are connected to the fourth input signal AVSSH.

[0037] The output stage includes a first output unit and a second output unit. The first output unit is connected to the first output node Q1 and the third input signal AVDDH and the fourth input signal AVSSH of the second voltage domain. The second output unit is connected to the second output node Q2 and the third input signal AVDDH and the fourth input signal AVSSH of the second voltage domain. The first output unit outputs the third input signal AVDDH and the fourth input signal AVSSH based on the control of the output signal on the first output node Q1, and the second output unit outputs the third input signal AVDDH and the fourth input signal AVSSH based on the control of the output signal on the second output node Q2, respectively.

[0038] like Figure 1 As shown, in one embodiment, the first output unit includes a first inverter and a second inverter connected in series. The second output unit includes a third inverter and a fourth inverter connected in series.

[0039] The first inverter includes the seventh transistor M7 and the eighth transistor M8, the second inverter includes the ninth transistor M9 and the tenth transistor M10, the third inverter includes the eleventh transistor M11 and the twelfth transistor M12, and the fourth inverter includes the thirteenth transistor M13 and the fourteenth transistor M14.

[0040] The first terminal of the seventh transistor M7, the first terminal of the ninth transistor M9, the first terminal of the eleventh transistor M11, and the first terminal of the thirteenth transistor M13 are connected to the third input signal AVDDH. The first terminal of the eighth transistor M8, the first terminal of the tenth transistor M10, the first terminal of the twelfth transistor M12, and the first terminal of the fourteenth transistor M14 are connected to the fourth input signal AVSSH.

[0041] The control terminals of the seventh transistor M7 and the eighth transistor M8 are connected to form the input terminal of the first inverter and are connected to the first output node Q1. The second terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8 are connected to form the output terminal of the first inverter. The control terminals of the ninth transistor M9 and the tenth transistor M10 are connected to form the input terminal of the second inverter and are connected to the output terminal of the first inverter. The second terminal of the ninth transistor M9 and the second terminal of the tenth transistor M10 are connected to form the output terminal of the second inverter (that is, the output terminal VOUTN of the first output unit).

[0042] The control terminals of the eleventh transistor M11 and the twelfth transistor M12 are connected to form the input terminal of the third inverter and are connected to the second output node Q2. The second terminal of the eleventh transistor M11 and the second terminal of the twelfth transistor M12 are connected to form the output terminal of the third inverter. The control terminals of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to form the input terminal of the fourth inverter and are connected to the output terminal of the third inverter. The second terminal of the thirteenth transistor M13 and the second terminal of the fourteenth transistor M14 are connected to form the output terminal of the fourth inverter (that is, the output terminal VOUTP of the second output unit).

[0043] like Figure 1 As shown, the output stage also includes a first coupling unit and a second coupling unit. The first end of the first coupling unit is connected to the input terminal of the first inverter and the first output node Q1. The second end of the first coupling unit is connected to the output terminal of the third inverter and the input terminal of the fourth inverter. The first end of the second coupling unit is connected to the output terminal of the first inverter and the input terminal of the second inverter. The second end of the second coupling unit is connected to the second output node Q2 and the input terminal of the third inverter.

[0044] In one embodiment, the first coupling unit includes a first capacitor C1, and the second coupling unit includes a second capacitor C2. The first terminal of the first capacitor C1 is connected to the input terminal of the first inverter and the first output node Q1, and the second terminal of the first capacitor C1 is connected to the output terminal of the third inverter and the input terminal of the fourth inverter. The first terminal of the second capacitor C2 is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the second terminal of the second capacitor C2 is connected to the second output node Q2 and the input terminal of the third inverter.

[0045] In other embodiments, the first coupling unit may also be a third resistor or other circuit structure, and the second coupling unit may be a fourth resistor or other circuit structure.

[0046] In one embodiment, the first transistor M1, the third transistor M3, the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the thirteenth transistor M13 are P-channel MOSFETs, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12, and the fourteenth transistor M14 are N-channel MOSFETs. In other embodiments, the first transistor M1, the third transistor M3, the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the thirteenth transistor M13 can be N-channel MOSFETs, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12, and the fourteenth transistor M14 are P-channel MOSFETs.

[0047] The first terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are the sources; the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M14 are the sources. The control terminals of transistors M8, M9, M10, M11, M12, M13, and M14 are gates; the second terminals of transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14 are drains.

[0048] In other embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and / or the fourteenth transistor M14 can be NPN or PNP type transistors.

[0049] like Figure 1 As shown, the first input terminal VIP and the second input terminal VIN receive the first input signal AVDDL and the second input signal AVSSL from the first voltage domain. In one embodiment, the first input signal AVDDL and the second input signal AVSSL are fixed signals and are inverted signals. That is, at the same time, only one of the first transistor M1 and the third transistor M3 is turned on. If the second input signal AVSSL is input from the control terminal of the first transistor M1, the first transistor M1 is turned on. The signal output from the second terminal of the first transistor M1 passes through the first resistor R1 and the second transistor M2 and is used as the input to the control terminal of the sixth transistor M6 and the output signal of the first output node Q1 as the control signal of the first inverter. The signal at the first terminal of the sixth transistor M6 is the fourth input signal AVSSH. When the sixth transistor M6 is turned on, the output signal generated at the second terminal of the sixth transistor M6 (i.e., the second output node Q2) serves as the control signal for the third inverter. The output signal of the third inverter serves as the control signal for the fourth inverter. Finally, the signal output from the output terminal VOUTP is either the third input signal AVDDH or the fourth input signal AVSSH. Similarly, the signal output from the output terminal VOUTN is either the third input signal AVDDH or the fourth input signal AVSSH. The signals output from the output terminals VOUTN and VOUTP are inverted signals. In one embodiment, the third input signal AVDDH and the fourth input signal AVSSH are floating signals. In other embodiments, the first input signal AVDDL and the second input signal AVSSL can also be floating signals, and the third input signal AVDDH and the fourth input signal AVSSH can also be fixed signals.

[0050] The first resistor R1 and the second resistor R2 are path current-limiting resistors for current limiting. The main function of the second transistor M2 and the fourth transistor M3 is to isolate the first voltage domain and the second voltage domain (for example, if there is a high voltage difference, the second transistor M2 and the fourth transistor M3 can play a role in resisting high voltage). The fifth transistor M5 and the sixth transistor M6 form a cross-coupled latch structure to ensure that the logic level is latched correctly. The first capacitor C1 is used for positive feedback of the two in-phase signals between the input of the first inverter and the output of the third inverter, so that the signal at the input of the first inverter can pass through the uncertain level stage faster, avoiding logic flipping errors and speeding up the flipping speed. The second capacitor C2 is used for positive feedback of the two in-phase signals between the input of the third inverter and the output of the first inverter, and the principle is the same as that of the first capacitor C1.

[0051] This application also discloses a chip including the level conversion circuit described above.

[0052] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0053] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A level conversion circuit, characterized in that, include: An input stage has a first output node and a second output node. The input stage is used to receive a first input signal and a second input signal from a first voltage domain and a third input signal from a second voltage domain, to perform level conversion on the first input signal and the second input signal to generate a first output signal from the second voltage domain, and to output the first output signal to the first output node or the second output node. The latching stage, connected to the first and second output nodes of the input stage and the fourth input signal from the second voltage domain, is used to receive and latch the first output signal and generate corresponding output signals from the second voltage domain at the first and second output nodes. as well as The output stage is connected to the first output node, the second output node, and the third and fourth input signals of the second voltage domain, so as to output the third and fourth input signals of the second voltage domain based on the control of the output signals on the first and second output nodes.

2. The level conversion circuit according to claim 1, characterized in that, The input stage includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first current limiting unit, and a second current limiting unit; The control terminal of the first transistor is used to receive a first input signal, the first terminal of the first transistor is used to receive a reference voltage, the second terminal of the first transistor is connected to the first terminal of the first current limiting unit, the second terminal of the second current limiting unit is connected to the second terminal of the second transistor, the control terminal of the second transistor is used to receive a third input signal, the first terminal of the second transistor is connected to the first output node, the control terminal of the third transistor is used to receive a second input signal, the first terminal of the third transistor is used to receive a reference voltage, the second terminal of the third transistor is connected to the first terminal of the second current limiting unit, the second terminal of the second current limiting unit is connected to the second terminal of the fourth transistor, the control terminal of the fourth transistor is used to receive a third input signal, and the first terminal of the fourth transistor is connected to the second output node.

3. The level conversion circuit according to claim 2, characterized in that, The first current limiting unit includes a first resistor, a first terminal of which is connected to a second terminal of a first transistor, and a second terminal of which is connected to a second terminal of a second transistor; and / or The second current limiting unit includes a second resistor, the first end of which is connected to the second end of the third transistor, and the second end of which is connected to the second end of the fourth transistor.

4. The level conversion circuit according to claim 1, characterized in that, The latch stage includes a fifth transistor and a sixth transistor. The control terminal of the fifth transistor and the second terminal of the sixth transistor are connected to a second output node. The control terminal of the sixth transistor and the second terminal of the fifth transistor are connected to a first output node. The first terminals of the fifth transistor and the sixth transistor are connected to a fourth input signal.

5. The level conversion circuit according to claim 1, characterized in that, The output stage includes a first output unit and a second output unit. The first output unit is connected to a first output node and a third and a fourth input signal of the second voltage domain. The second output unit is connected to a second output node and a third and a fourth input signal of the second voltage domain. The first output unit outputs the third and fourth input signals based on the control of the output signal on the first output node, and the second output unit outputs the third and fourth input signals based on the control of the output signal on the second output node, respectively.

6. The level conversion circuit according to claim 5, characterized in that, The first output unit includes a first inverter and a second inverter connected in series.

7. The level conversion circuit according to claim 5, characterized in that, The second output unit includes a third inverter and a fourth inverter connected in series.

8. The level conversion circuit according to claim 5, characterized in that, The first output unit includes a first inverter and a second inverter connected in series. The second output unit includes a third inverter and a fourth inverter connected in series. The output stage also includes a first coupling unit and a second coupling unit. The first end of the first coupling unit is connected to the input end of the first inverter and the first output node. The second end of the first coupling unit is connected to the output end of the third inverter and the input end of the fourth inverter. The first end of the second coupling unit is connected to the output end of the first inverter and the input end of the second inverter. The second end of the second coupling unit is connected to the second output node and the input end of the third inverter.

9. The level conversion circuit according to claim 8, characterized in that, The first coupling unit includes a first capacitor, and / or the second coupling unit includes a second capacitor.

10. The level conversion circuit according to claim 8, characterized in that, The first coupling unit includes a third resistor, and / or the second coupling unit includes a fourth resistor.

Images