LDO (Low Dropout Regulator) circuit capable of suppressing overshoot and shortening output stabilization time

Abstract

The utility model discloses an improved LDO (Low Dropout Regulator) circuit, which can restrain overshoot and shorten the time for output voltage to recover to be stable, and comprises an LDO unit 101 used for outputting voltage VOUT1; the current mirror unit 102 is used for providing bias current for the branch; the voltage stabilizing unit 103 is used for fixing the grid voltage and reducing the power consumption of the circuit in a non-load state; the protection unit 104 is used for inhibiting overshoot of the output voltage VOUT2; and a transistor MP5. Compared with the prior art, by introducing the protection unit, the overshoot amplitude and the undershoot amplitude of the output voltage VOUT2 are reduced, and the output response speed is further improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to low pressure linear voltage stabilizer technical field, concretely relates to a kind of LDO circuit not only can inhibit overshoot and the output voltage stabilization time shortening. BACKGROUND

[0002] Low pressure linear voltage stabilizer (Low Dropout Liner Regulator, LDO) is widely used in electronic circuit due to the characteristics of output voltage stabilization, small noise, small area etc., but when the load of LDO switches from light load to heavy load or from heavy load to light load, overshoot phenomenon will occur in output voltage. When overshoot occurs, the time of LDO output voltage recovery to stable will be prolonged, so that the output response speed is slowed down. On the other hand, when the voltage drop is too large due to overshoot, the instantaneous current will also be large accordingly, so the current will damage the circuit noise, especially when the output produces overshoot, the output voltage is too large to possibly exceed the withstand voltage value of load end electronic device, resulting in tube damage, which seriously affects the service life of electronic device.

[0003] In order to solve the problem of LDO output voltage overshoot, the disclosed method is to introduce resistance or off-chip capacitance in the output voltage section. The method of introducing resistance in the output voltage section will increase the static power consumption of LDO, because the new introduced resistance has large current flowing through the path. Although the method of introducing off-chip capacitance can suppress overshoot, it will prolong the time of output voltage recovery to stable, so the speed is slow. In addition, when the capacitance is large, the cost of chip will be increased. Therefore, it is necessary to provide a kind of LDO circuit which can not only suppress overshoot but also has fast output voltage response speed.

[0004] The patent application with the publication number CN114063695A discloses a three-loop LDO circuit without external capacitor based on FVF, which suppresses overshoot and undershoot through an AC-Couple loop and a voltage suppression circuit, thereby improving the output response speed, but the circuit still has certain defects and cannot meet the requirements of electronic products with high output precision and high power consumption. On the one hand, the transistor MP5 and the transistor MP9 constitute a current mirror structure, and under the condition that the size and current ratio of the MOS tube are the same, it can be inferred that V1=VOUT. Since the current of the transistor MP9 is mainly determined by the current of the transistor MN9, and the current of the transistor MN9 is copied from the transistor MN6, when the output voltage VOUT changes, the change will be coupled to the gate of the transistor MP6 through the capacitor C2, and the current of the transistor MP6 also changes. The currents of the transistors MN9 and MP9 are changing, while the current of the transistor MP5 is constant, so the voltage value deviation of the circuit output VOUT and V1 will increase. On the other hand, the VOUT voltage is coupled to the gates of the transistors MN7 and MP6 through capacitors C1 and C2, respectively. When there is no load output VOUT=1.2V, the gate voltages of the transistors MN7 and MP6 are at an intermediate potential between VDD and GND, at this time, the transistors MN7 and MP6 are in the on state, so that the static power consumption increases. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] For the LDO circuit, when the load switches from light load to heavy load or from heavy load to light load, the output voltage will overshoot, and the time for the output voltage to stabilize will be longer, and the response will be slower.

[0007] The utility model discloses a kind of improved LDO circuits, can suppress overshoot and shorten the time for output voltage to recover stable.

[0008] TECHNICAL PROBLEM SOLUTION

[0009] The utility model provides an improved LDO circuit, and the circuit comprises:

[0010] LDO unit 101, for output voltage VOUT1;

[0011] Current mirror unit 102, for providing bias current for branch;

[0012] Voltage stabilizing unit 103, for fixing gate voltage, and reducing the power consumption of circuit in no-load state;

[0013] Protection unit 104, for suppressing overshoot of output voltage VOUT2;

[0014] And transistor MP5.

[0015] Further, the protection unit 104 comprises transistors MP4, MP6, MN5, MN7, and capacitor C1, wherein the source of the transistor MP4 is connected to the power supply, the drain is connected to the source of the transistor MP6, and the gate is connected to the common terminal of the drain of MP3 and the drain of MN5; the drain of the transistor MP6 is connected to the drain of MN7, the gate of MP6 is connected to the gate of MP5, the drain of MN7 is connected to the common terminal of the drain of MP4 and the source of MP6, the source of MN7 is connected to the ground, the gate of MN7 is connected to the common terminal of the source of MN5 and the drain of MN6, and the gate of MN7 is also connected to the common terminal of the drain of MP6 and the drain of MN7; the upper plate of the capacitor C1 is connected to the gate of MP4, and the lower plate is connected to the common terminal of the drain of MP4 and the source of MP6.

[0016] Further, the drain of the transistor MN4 in the voltage stabilizing unit 103 is connected to the power supply, the source is connected to the drain of the transistor MN3, and the gate is connected to the drain of MN4; the gate of the transistor MN3 is connected to its drain, and the source is connected to the ground.

[0017] Further, the current mirror unit 102 comprises transistors MP1, MP2, MP3, MN1, MN2, MN6, and MN7, the sources of the transistors MP1, MP2, and MP3 are all connected to the ground, the drain of the transistor MP1 is connected to the drain of the transistor MN1, the source of the transistor MN1 is connected to the ground, the gate of MN1 is connected to the gate of MN2, and the drain of MN1 is connected to the common terminal of the gate of MN1 and the gate of MN2.

[0018] The source of MN6 is connected to the ground, and the gate is connected to the drain of MN1; the source of MN7 is connected to the ground, and the gate is connected to the drain of MN1.

[0019] Further, the LDO unit 101 comprises an operational amplifier AMP, a resistor R1, and a resistor R2, one end of the resistor R1 is connected to the output of the operational amplifier AMP, the resistor R1 and the resistor R2 are connected in series, the other end of the resistor R2 is connected to the ground, the common terminal of the resistor R1 and the resistor R2 is connected to the negative input of the operational amplifier, the positive input of the operational amplifier AMP is connected to the reference voltage VREF, the A terminal of the operational amplifier is connected to the power supply, and the B terminal is connected to the ground.

[0020] The source of the transistor MP5 is connected to the output of the operational amplifier AMP, the drain is connected to the drain of the transistor MN2, the gate is connected to the gate of the transistor MP6, and the gate of MP5 is connected to the drain.

[0021] Advantages

[0022] Compared with the existing LDO circuit, the improved LDO circuit of the utility model introduces the protection unit, the transistor MP6 and the transistor MN7 play the overshoot inhibition function, the current flowing through MN7 is adjusted, thereby inhibiting the overshoot of the output voltage VOUT2. On the other hand, the loop formed by the capacitor C1 and the transistor MP4 can improve the transient response speed, when the output voltage VOUT2 changes, the change is coupled to the gate of the transistor MP4 through the capacitor C1, the voltage at this place is adjusted, the output voltage overshoot is inhibited, so that the output voltage can be quickly stabilized, the time of the output voltage stabilization is shortened. In addition, the potential of VGN7 is adjusted by adjusting the Vgs voltage of the transistor MN5, so as to adjust the Vgs voltage of MN7, which can reduce the power consumption of the circuit in the no-load state. BRIEF DESCRIPTION OF DRAWINGS

[0023] The drawings provided herein are used to further illustrate the embodiments of the utility model, so as to facilitate understanding, and do not constitute the limitation of the embodiments of the utility model.

[0024] Figure 1 It is the structure schematic diagram of the improved LDO circuit of the utility model;

[0025] Figure 2 It is the action timing chart of the improved LDO circuit of the utility model;

[0026] Figure 3 It is the LDO circuit of prior art introducing resistance and the LDO circuit introducing off-chip capacitor;

[0027] Figure 4 It is the test result of the output voltage change of the improved LDO circuit of the utility model when the load current switches;

[0028] Figure 5 It is the test result of the output voltage change of the LDO circuit of prior art introducing resistance when the load current switches;

[0029] Figure 6 It is the test result of the output voltage change of the LDO circuit of prior art introducing off-chip capacitor when the load current switches. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the utility model more clear and obvious, the utility model will be further described in detail below in combination with embodiments and drawings, the illustrative embodiment of the utility model and its description are only used to explain the utility model, and do not constitute the limitation of the utility model. In order to be brief, this paper will not describe the technology known in the art, if the process is not particularly described, it is that the person skilled in the art can realize according to the prior art.

[0031] Figure 3The prior art shows that the LDO circuit is improved to suppress the overshoot of the output voltage, a resistor R3 is introduced in the output voltage section of the LDO, or an off-chip capacitor is used in the output voltage section of the LDO. Both of the two ways of suppressing the overshoot of the output voltage have defects. The introduction of the resistor R3 causes a large current to pass through the R3 path, thus increasing the static power consumption of the LDO, in addition, the resistor R3 is easy to affect the stability of the output voltage, and increase the deviation between the VOUT voltage value and the design value. The introduction of the off-chip capacitor prolongs the time for the output voltage to recover to stable after the overshoot occurs, and slows down the output response speed.

[0032] The utility model discloses in view of the defects of prior art, propose an improved LDO circuit, through protection unit to suppress the overshoot of output voltage, adopt current mirror fixed output voltage, make the whole circuit have good stability.

[0033] Figure 1 The utility model discloses improved LDO circuit structure, as shown in the figure, the circuit includes:

[0034] LDO unit 101 for output voltage VOUT1;

[0035] Current mirror unit 102 for providing bias current for branch;

[0036] Voltage stabilizing unit 103 for fixing gate voltage and reducing power consumption of circuit in no load state;

[0037] Protection unit 104 for suppressing the overshoot of output voltage VOUT2;

[0038] And transistor MP5.

[0039] LDO unit 101 includes operational amplifier AMP, resistance R1, resistance R2, and the output end of operational amplifier AMP is connected with one end of resistance R1, resistance R1 and resistance R2 are connected in series, the other end of resistance R2 is connected with ground, and the common end of resistance R1 and resistance R2 is connected with the negative input end of operational amplifier, the positive input end of operational amplifier AMP is connected with reference voltage VREF, the A end of operational amplifier is connected with power supply, and the B end is connected with ground.

[0040] Current mirror unit 102 includes transistors MP1, MP2, MP3, MN1, MN2, MN6, MN7, the source of transistors MP1, MP2 and MP3 is connected with ground, the drain of transistor MP1 is connected with the drain of transistor MN1, the source of transistor MN1 is connected with ground, the gate of MN1 is connected with the gate of MN2, and the drain of MN1 is connected with the common end of the gate of MN1 and the gate of MN2.

[0041] The source of MN6 is connected with ground, and the gate is connected with the drain of MN1;The source of MN7 is connected with ground, and the gate is connected with the drain of MN1.

[0042] In the voltage stabilizing unit 103, the drain of the transistor MN4 is connected to the power supply, the source is connected to the drain of the transistor MN3, and the gate is connected to the drain of MN4; the gate of the transistor MN3 is connected to its drain, and the source is connected to the ground.

[0043] The protection unit 104 comprises transistors MP4, MP6, MN5, MN7, and capacitor C1, wherein the source of the transistor MP4 is connected to the power supply, the drain is connected to the source of the transistor MP6, and the gate is connected to the common terminal of the drain of MP3 and the drain of MN5; the drain of the transistor MP6 is connected to the drain of MN7, the gate of MP6 is connected to the gate of MP5, the drain of MN7 is connected to the common terminal of the drain of MP4 and the source of MP6, the source of MN7 is connected to the ground, the gate of MN7 is connected to the common terminal of the source of MN5 and the drain of MN6, and is also connected to the common terminal of the drain of MP6 and the drain of MN7; the upper plate of the capacitor C1 is connected to the gate of MP4, and the lower plate is connected to the common terminal of the drain of MP4 and the source of MP6.

[0044] The source of the transistor MP5 is connected to the output terminal of the operational amplifier AMP, the drain is connected to the drain of the transistor MN2, and the gate is connected to the gate of the transistor MP6; the gate of MP5 is connected to its drain.

[0045] The working principle of the utility model for realizing the suppression of overshoot and shortening the output voltage stabilization time is that the transistor MP6 and the transistor MN7 play a role in overshoot suppression, the current flowing through MN7 is adjusted, and thus the overshoot of the output voltage VOUT2 is suppressed. When the output voltage VOUT2 changes, the potential change is transmitted to the gate of MN7 through the MP6 tube, the change trend of the gate voltage of MN7 increases or decreases, and is consistent with the change of the output voltage VOUT2, and thus the current flowing through the transistor MN7 can be controlled to suppress the overshoot of the output voltage VOUT2. In addition, the transistors MP4, MP6 and MN5 constitute a feedback loop, and when the load current at the output end is switched, the feedback loop plays a role in adjusting the potential of the output voltage VOUT2. The change of the load current will cause the change of the output voltage VOUT2, and the change of VOUT2 will be transmitted to the drain of the transistor MP6 through the source of the transistor MP6, the drain of the transistor MP6 is connected to the source of the transistor MN5, and a common source common gate amplifier is formed, and the change of the output voltage VOUT2 is amplified. In this way, the change of the transistor MP6 is transmitted to the gate of MP4 through MN5, and the current flowing through MP4 is adjusted to stabilize the output voltage VOUT2. In addition, the loop formed by the capacitor C1 and the transistor MP4 can improve the transient response speed, and when the output voltage VOUT2 changes, the change is coupled to the gate of the transistor MP4 through the capacitor C1, the voltage at this position is adjusted, the overshoot of the output voltage is suppressed, the output voltage can be quickly stabilized, and the time for stabilizing the output voltage is shortened.

[0046] In the voltage stabilizing unit 103, the transistor MN3 and the transistor MN4 are connected in a diode connection mode, which has two functions: one is to provide a fixed gate voltage VGN5 for the transistor MN5, so that the transistor MN5 works in a saturation region; the other is to adjust the potential of the VGN7 node by adjusting the Vgs voltage of the transistor MN5, so that the Vgs voltage of the MN7 is adjusted, and the power consumption of the circuit in a no-load state is reduced.

[0047] It should be noted that the transistor MN refers to an NMOS transistor, and the transistor MP refers to a PMOS transistor.

[0048] Figure 2 The action timing sequence of the improved LDO circuit is shown in the figure, when the circuit is in a normal working state, that is, the change of the load end current is small, and the change of the output voltage VOUT2 is also small, at this time, the feedback loop composed of the transistors MP4, MP6 and MN5 is used for adjusting the VOUT2. When the load is switched from light load to heavy load, the output voltage VOUT2 decreases with the increase of the load current, a large instantaneous voltage drop is generated, the VOUT2 will produce undershoot, at this time, the capacitor C1 couples the undershoot voltage to the gate of the transistor MP4, reduces the gate voltage, increases the current I_MP4 flowing through the transistor MP4, so that the output voltage quickly rises, and the voltage value tends to be stable. When the load is switched from heavy load to light load or current backflow occurs, the output voltage VOUT2 rises to produce overshoot, at this time, the potential of VGN7 rises with the rise of the output voltage VOUT2, the Vgs of the transistor MN7 increases, which leads to the increase of the current I_MN7, at this time, the output voltage VOUT2 decreases, which achieves the effect of suppressing the output. In addition, when the output voltage VOUT2 overshoots, the capacitor C1 couples the voltage to the gate of the transistor MP4, increases the gate voltage, and reduces the current I_MP4 flowing through the transistor MP4, so that the output voltage quickly decreases and returns to the stable voltage state.

[0049] Figure 4 The improved effect of the LDO circuit is shown in the figure, when the load current is switched from heavy load 20mA to light load 200uA, the overshoot voltage of VOUT2 is 257mA, and the time for the output voltage to recover to the stable state is 259ns; when the load current is switched from light load 200uA to heavy load 20mA, the undershoot voltage of VOUT2 is 310mV, and the time for the output voltage to recover to the stable state is 100ns.

[0050] In comparison, Figure 5 , Figure 6The test results of the output voltage variation of the LDO circuit when the load current is switched are shown respectively when the prior art introduces resistance and off-chip capacitance.

[0051] When the off-chip capacitance is introduced, under the condition of the same load current switching, the overshoot voltage of VOUT2 is 13mV, and the time for the voltage output to recover to be stable is 226us; the undershoot voltage of VOUT2 is 11mV, and the time for the voltage output to recover to be stable is 126us.

[0052] Therefore, the improved LDO circuit has smaller overshoot voltage and undershoot voltage of the output voltage, and the time for the voltage to recover to be stable is short, so that the output voltage responds faster.

[0053] The above-described specific embodiments explain the purpose, technical solutions and advantages of the utility model in further detail, and it should be understood that the above-described specific embodiments are merely specific embodiments of the utility model and are not used to limit the protection scope of the utility model, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. An LDO circuit that suppresses overshoot and shortens output settling time, characterized in that, The circuit comprises: an LDO unit (101) for outputting a voltage VOUT1; a current mirror unit (102) for providing a bias current for a branch; a voltage stabilizing unit (103) for fixing a gate voltage and reducing power consumption of the circuit in a no-load state; a protection unit (104) for inhibiting overshoot of an output voltage VOUT2; and a transistor MP5.

2. The LDO circuit of claim 1, wherein, The protection unit (104) comprises a transistor MP4, a transistor MP6, a transistor MN5, a transistor MN7, and a capacitor C1, wherein the source of the transistor MP4 is connected to a power supply, the drain of the transistor MP4 is connected to the source of the transistor MP6, and the gate of the transistor MP4 is connected to a common terminal of the drain of the transistor MP3 and the drain of the transistor MN5; the drain of the transistor MP6 is connected to the drain of the transistor MN7, the gate of the transistor MP6 is connected to the gate of the transistor MP5, the drain of the transistor MN7 is connected to a common terminal of the drain of the transistor MP4 and the source of the transistor MP6, the source of the transistor MN7 is connected to the ground, and the gate of the transistor MN7 is connected to a common terminal of the source of the transistor MN5, the drain of the transistor MN6, and the drain of the transistor MP6; and the upper plate of the capacitor C1 is connected to the gate of the transistor MP4, and the lower plate of the capacitor C1 is connected to a common terminal of the drain of the transistor MP4 and the source of the transistor MP6.

3. The LDO circuit of claim 1, wherein, In the voltage stabilizing unit (103), the drain of the transistor MN4 is connected to a power supply, the source of the transistor MN4 is connected to the drain of the transistor MN3, and the gate of the transistor MN4 is connected to the drain of the transistor MN4; the gate of the transistor MN3 is connected to the drain of the transistor MN3, and the source of the transistor MN3 is connected to the ground.

4. The LDO circuit of claim 1, wherein, The current mirror unit (102) comprises a transistor MP1, a transistor MP2, a transistor MP3, a transistor MN1, a transistor MN2, a transistor MN6, and a transistor MN7, wherein the sources of the transistors MP1, MP2, and MP3 are all connected to the ground, the drain of the transistor MP1 is connected to the drain of the transistor MN1, the source of the transistor MN1 is connected to the ground, the gate of the transistor MN1 is connected to the gate of the transistor MN2, and the drain of the transistor MN1 is connected to a common terminal of the gate of the transistor MN1 and the gate of the transistor MN2; the source of the transistor MN6 is connected to the ground, and the gate of the transistor MN6 is connected to the drain of the transistor MN1; the source of the transistor MN7 is connected to the ground, and the gate of the transistor MN7 is connected to the drain of the transistor MN1.

5. The LDO circuit of claim 1, wherein, The LDO unit (101) comprises an operational amplifier AMP, a resistor R1, and a resistor R2, wherein one end of the resistor R1 is connected to the output of the operational amplifier AMP, the resistor R1 and the resistor R2 are connected in series, the other end of the resistor R2 is connected to the ground, a common terminal of the resistor R1 and the resistor R2 is connected to the negative input of the operational amplifier, the positive input of the operational amplifier AMP is connected to a reference voltage VREF, the A terminal of the operational amplifier is connected to a power supply, and the B terminal of the operational amplifier is connected to the ground; the source of the transistor MP5 is connected to the output of the operational amplifier AMP, the drain of the transistor MP5 is connected to the drain of the transistor MN2, the gate of the transistor MP5 is connected to the gate of the transistor MP6, and the gate of the transistor MP5 is connected to the drain of the transistor MP5.

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