Data acquisition and storage system
The FPGA main control module, composed of DDR memory, eMMC storage module and host computer communication module, combined with AD acquisition module, USB reading module and Ethernet reading module, solves the problem of high-speed data acquisition, processing, storage and export in existing data acquisition, storage and export systems, and realizes the functions of high-speed data acquisition, low power consumption and data backup.
Patent Information
- Application Number
- CN202423021510.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-12-09
AI Technical Summary
Existing pipeline inspection systems suffer from slow data acquisition, storage, and retrieval speeds, high power consumption, long export times, and insecure data storage without backup. Furthermore, the equipment is bulky and cannot meet the demands for high frequency, high precision, and high bandwidth.
The system employs an FPGA main control module composed of a DDR memory module, an eMMC storage module, and a host computer communication module. Combined with an AD acquisition module, a USB reading module, and an Ethernet reading module, it utilizes various technologies to achieve high-speed data acquisition, processing, storage, and export. An FTDI chip is used as the bridge portion of the USB 3.0 interface to implement the USB 3.0 communication protocol. High-speed signals acquired from the channels are converted from single-ended signals to differential signals via a transformer through SPI and UART serial protocols, and then converted from analog to digital signals before being transmitted to the DDR memory module for buffering. Data is also transmitted to the DDR memory module for buffering via SPI and UART serial protocols.
It achieves high-speed data acquisition, low power consumption, short export time, small size, data backup function, adaptability to complex working environments, and provides a system that integrates data acquisition, processing, storage and export, realizing high-frequency, high-precision and high-bandwidth data processing.
Smart Images
Figure CN223637982U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to data acquisition storage technical field especially is related to a data acquisition storage system. BACKGROUND
[0002] Current detection technology is developing at a high speed, and the throughput and real-time demand of data processing continue to rise. Under this condition, the acquisition, storage and reading speed of data and the size of storage capacity become increasingly important in signal processing. In the field of pipeline detection technology, the data acquisition and storage system plays an important role. The pipeline detection industry has developed from the original single acquisition, processing and analysis to a system integrating acquisition, processing, storage, analysis and other multiple requirements. At the same time, the demand for high frequency of collected signals, high precision of acquisition system, high bandwidth and large capacity of storage system is increasingly prominent.
[0003] At present, there are many companies in the pipeline detection industry that can provide high data volume and multiple types of sensors, but there is no acquisition and storage system that can provide such acquisition, processing, conversion, storage and data export. The existing similar system has slow acquisition speed, high power consumption and long export time, and the data is not safe without backup storage. Moreover, the existing equipment is large in size. SUMMARY
[0004] The utility model provides a kind of data acquisition storage system to solve one or more problems in the above.
[0005] The present specification discloses a kind of data acquisition storage systems, comprising:
[0006] FPGA master module consisting of DDR memory module, EMMC storage module and host computer communication module;
[0007] AD acquisition module is connected with the DDR memory module;
[0008] USB reading module is connected with the DDR memory module;
[0009] Ethernet reading module is connected with the DDR memory module;
[0010] Host computer is connected with the USB reading module, Ethernet reading module and host computer communication module;
[0011] Wherein, the DDR memory module is connected with EMMC storage module and host computer communication module respectively.
[0012] In the specification, the host computer comprises a PC copy host computer module and a PC detection host computer module, the PC copy host computer module is connected with the USB reading module and the Ethernet reading module to perform data transmission and data copying, and the PC detection host computer module is connected with the host computer communication module to perform data communication.
[0013] In the specification, the AD acquisition module performs data transmission through an LVDS communication protocol, converts single-ended signals into differential signals through a transformer, and then performs analog-to-digital conversion on the differential signals to transmit digital signals to the DDR memory module for buffering.
[0014] In the specification, the AD acquisition module transmits data to the DDR memory module through SPI and UART serial port protocols for buffering.
[0015] In the specification, the DDR memory module is a DDR3 buffer memory, the data bit width of which is 16 bits, the capacity size is 256M bytes, and the burst length is 8.
[0016] In the specification, the EMMC storage module is an array storage module formed by multiple EMMC chips arranged in an array.
[0017] In the specification, the USB reading module uses an FTDI chip as a USB3.0 interface.
[0018] In the specification, the Ethernet reading module uses a gigabit network RGMII interface as an external signal interface.
[0019] The embodiment of the specification can achieve at least the following beneficial effects:
[0020] The FPGA master control module is connected to control each module, the AD acquisition module acquires data and transmits the data to the EMMC storage module through the DDR memory module, the host computer communication module is used to detect the data in real time, the USB reading module and the Ethernet reading module are connected to the DDR memory module and the EMMC storage module to communicate, the host computer is used to upload and analyze the stored data, and a data acquisition and storage system integrating data acquisition, processing, conversion, storage and data export is realized, data can be acquired at a high speed, the power consumption is low, the data export time is short, the data can be stored in time, and the volume is small. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the technical scheme of the embodiment of the utility model, the drawings needed in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without creative labor.
[0022] Figure 1 A structure diagram of a data acquisition and storage system involved in some embodiments of the utility model.
[0023] Figure 2 A schematic diagram of an EMMC storage module involved in some embodiments of the utility model. DETAILED DESCRIPTION
[0024] Hereinafter, only certain exemplary embodiments are simply described. As can be appreciated by those skilled in the art, the described embodiments can be modified in various different manners without departing from the spirit or scope of the embodiments of the utility model. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.
[0025] In the description of the embodiments of the utility model, it is understood that the terms "length", "vertical", "horizontal", "top", "bottom" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the utility model.
[0026] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the utility model, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0027] In the embodiments of the utility model, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected, or it can be communicated; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the utility model can be understood according to the specific circumstances.
[0028] In the embodiments of the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can include that the first and second features are in direct contact, or the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "on the surface of" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.
[0029] The following disclosure provides many different embodiments or examples for implementing different structures of the embodiments of the present application. In order to simplify the disclosure of the embodiments of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the embodiments of the present application. In addition, the embodiments of the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.
[0030] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0031] As Figure 1 indicated, the present embodiment provides a data acquisition and storage system, comprising:
[0032] The FPGA master module is composed of a DDR memory module, an EMMC storage module and a host computer communication module;
[0033] The AD acquisition module is connected with the DDR memory module;
[0034] The USB reading module is connected with the DDR memory module;
[0035] The Ethernet reading module is connected with the DDR memory module;
[0036] The host computer is connected with the USB reading module, the Ethernet reading module and the host computer communication module;
[0037] The DDR memory module is connected with the EMMC storage module and the host computer communication module, respectively.
[0038] In some embodiments, the host computer includes a PC copy host computer module and a PC detection host computer module, the PC copy host computer module is connected with the USB reading module and the Ethernet reading module to perform data transmission and data copying; the PC detection host computer module is connected with the host computer communication module to perform data communication.
[0039] In some embodiments, the AD acquisition module transmits data through the LVDS communication protocol, converts single-ended signals into differential signals through a transformer, and then converts the differential signals into digital signals through an analog-digital conversion for transmission to the DDR memory module for buffering.
[0040] In some embodiments, the AD acquisition module transmits data to the DDR memory module through the SPI and UART serial port protocols for buffering.
[0041] In this specification, the DDR memory module is a DDR3 cache memory with a data bit width of 16 bits, a capacity of 256 Mbytes, and a burst length of 8.
[0042] In some embodiments, the EMMC storage module is an array storage module formed by multiple EMMC chips arranged in an array.
[0043] In some embodiments, the USB reading module uses an FTD I chip as a USB3.0 interface.
[0044] In some embodiments, the Ethernet reading module uses a Gigabit RGMII interface as an external signal interface.
[0045] The technical idea of the data acquisition and storage system is as follows:
[0046] The FPGA master module is connected to control each module, the AD acquisition module is connected to a high-speed ADC probe to collect data, which is transmitted to the EMMC storage module through the DDR memory module, and the data is detected in real time through the upper computer communication module. The USB reading module and the Ethernet reading module are connected to the DDR memory module and the EMMC storage array module for communication, and the storage data is uploaded and analyzed through the upper computer.
[0047] The AD acquisition module: first, data transmission through the LVDS communication protocol, converting the single-ended signals collected by the channel into differential signals through a transformer, and then converting the differential signals into digital signals through a high-precision ADC acquisition chip for transmission to the FPGA internal cache. Second, data is written into the internal cache of the FPGA through the SPI and UART serial port protocols. Finally, the data is transmitted to the DDR memory module for buffering.
[0048] DDR memory module: this module is used as the cache of data read and write, the application uses DDR3, the data bit width is 16 bits, and the capacity size is 256M bytes. Because DDR is double-edge triggered, the burst length is set to 8, so the data length transmitted each time is 16*8=128 bits. Using DDR3 as the cache memory, the specified start address and burst length of the DDR are controlled, and the addressing and writing of the cached data and the reading of the data are automatically operated, the continuous burst transmission is realized, and the effect of high-speed caching data is achieved.
[0049] EMMC storage module: this module uses multiple EMMC to build an array system to store data, such as Figure 2 , the EMMC device is composed of NAND flash and a main controller. This time, EMMC5.0 communication protocol is used for data transmission. The FPGA transmits the collected data or the data in the DDR memory module to the controller of the EMMC storage module, and the controller writes the data into multiple normal EMMCs at the same time for simultaneous storage. When the EMMC storage module receives a large amount of data, it writes more data into the EMMC. When the whole column storage receives a data export command, it reads out the data of multiple EMMCs at the same time, which is used to break the speed limit of a single EMMC.
[0050] USB reading module: this module uses FTDI chip as the bridge part of USB3.0 interface and FPGA to realize USB3.0 communication protocol. FPGA transmits the FIFO data in the FT60x chip through the bus. Through the host computer, the data copy command is transmitted to the EMMC storage module to start the data reading function, and the data is transmitted to the host computer at the same time. The copy data speed can reach 280M / s.
[0051] Ethernet reading module: this application uses gigabit network RGMII interface and physical layer PHY, and the FPGA master module is responsible for the conversion of double-edge and single-edge data of RGMII interface. Then, through ARP protocol, the host computer completes the transmission and reception of ARP data packet and CRC check. First, the Ethernet module sends a broadcast command, and the host computer parses the system MAC address and then packs its own MAC address into the ARP data segment to send to the system to parse and obtain the MAC addresses of both parties. Then, ICMP protocol is used to detect network communication and ping command, and the DDR memory module is waiting for data caching. The Ethernet module sends the cached data to the host computer through UDP protocol. The host computer receives the UDP data after ensuring the accuracy of the handshake by comparing the IP header checksum, UDP checksum and frame check sequence FCS, and realizes the data copy function of Ethernet.
[0052] Host computer communication module: the host computer will batch read data first stored in the memory buffer, then batch stored in the disk, and then realize the high-speed export and save of data.
[0053] In summary, the whole system is composed of multiple EMMC, the read-write speed of single EMMC is 280M / S, multiple EMMC can work simultaneously to reach several times the speed, which can meet the high sampling frequency of up to hundreds of megabytes per second, and the data copying system with USB3.0 and Ethernet can also provide high speed, strong anti-interference ability, low power consumption, and multiple selection copying mode storage system. The high integration system integrating signal acquisition, processing, storage, copying and analysis functions can adapt to complex working environment. The storage system of the device switches multiple EMMC to work, which has more advantages in high-speed acquisition and storage capacity, and can switch to other EMMC to continue working when a single EMMC is full or damaged, realizing data backup. The device has a USB3.0 interface and a gigabit network port, providing high transmission rate, high anti-interference ability, low power consumption data export function, and convenient user selection. Compared with X86, ARM and other controls, the EMMC controlled by FPGA, Ethernet and USB chips have higher speed and lower power consumption. Compared with UFS and hard disk, EMMC also has lower power consumption, and is more suitable for existing pipeline battery power supply environment.
[0054] The above examples describe a plurality of specific embodiments of the present application, but those skilled in the art should understand that various changes or modifications can be made to these embodiments without departing from the principles and essence of the present application, and these changes and modifications all fall within the protection scope of the present application.
Claims
1. A data acquisition storage system, characterized by, The application relates to a data acquisition system, which comprises the following parts: an FPGA master module composed of a DDR memory module, an EMMC storage module and a host computer communication module; an AD acquisition module connected with the DDR memory module; a USB reading module connected with the DDR memory module; an Ethernet reading module connected with the DDR memory module; a host computer connected with the USB reading module, the Ethernet reading module and the host computer communication module; wherein the DDR memory module is connected with the EMMC storage module and the host computer communication module.
2. The data acquisition storage system of claim 1, wherein, The host computer comprises a PC copy host computer module and a PC detection host computer module, the PC copy host computer module is connected with the USB reading module and the Ethernet reading module to realize data transmission and data copy, and the PC detection host computer module is connected with the host computer communication module to realize data communication.
3. The data acquisition storage system of claim 1, wherein, The AD acquisition module realizes data transmission through an LVDS communication protocol, converts single-end signals into differential signals through a transformer, and then converts the differential signals into digital signals through analog-digital conversion and transmits the digital signals to the DDR memory module for buffering.
4. The data acquisition storage system of claim 1, wherein, The AD acquisition module transmits data to the DDR memory module through SPI and UART serial port protocols for buffering.
5. The data acquisition storage system of claim 1, wherein, The DDR memory module is a DDR3 buffer storage, the data bit width of which is 16 bit, the capacity of which is 256M bytes, and the burst length of which is 8.
6. The data acquisition storage system of claim 1, wherein, The EMMC storage module is an array storage module formed by multiple EMMC arrays.
7. The data acquisition storage system of claim 1, wherein, The USB reading module uses an FTDI chip as a USB3.0 interface.
8. The data acquisition storage system of claim 1, wherein, The Ethernet reading module uses a gigabit network RGMII interface as an external signal interface.