Conductive bump structure
By forming a stepped groove structure on the semiconductor substrate, the delamination problem of solder bump structure under high-density circuit redistribution layer is solved, and a more stable electrical connection is achieved.
Patent Information
- Application Number
- CN202423080439.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-20
- Filing Date
- 2024-12-13
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-12-13
AI Technical Summary
Existing solder bump structures are prone to delamination between copper traces and insulation layers under high-density circuit redistribution, leading to unstable connections.
A stepped groove structure is formed on a semiconductor substrate by pre-opening the first insulating layer under the metal bump position and the first opening on the solder pad, and forming a third opening larger than the second opening in the second insulating layer to form a stepped groove to disperse stress and avoid stress concentration at the interface of different materials.
It effectively disperses the stress at the junction of the first insulating layer, the second insulating layer, the metal layer and the conductive metal layer, avoids delamination problems and improves the stability and reliability of the connection.
Smart Images
Figure CN223638364U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a conductive bump, in particular to a conductive bump structure formed on a semiconductor substrate. BACKGROUND
[0002] With the advancement of semiconductor manufacturing technology and the increasing functionality of chip circuits, accompanied by the rapid growth of demand for various portable products such as communication, network and computer, the semiconductor packaging technologies such as ball grid array (BGA), flip chip and chip size package (CSP) with high density and multi-pin characteristics have become the mainstream.
[0003] Compared with the wire bonding technology, the flip chip package is characterized in that the electrical connection between the semiconductor chip and the packaging substrate is through solder bumps instead of general gold wires. Using solder bumps as electrical connection elements has the advantages of shortening the electrical conduction path, improving performance, providing a heat dissipation path and reducing the volume of the package, thus becoming the trend of packaging.
[0004] Referring to Figures 1A-1D , the existing solder bump manufacturing method provides a wafer 10, which is covered with a protective layer 11, and the protective layer 11 exposes a solder pad 100. A first insulating layer 12 is formed on the wafer 10, and the first insulating layer 12 has a first opening 120 to expose the solder pad 100. Then, a redistribution layer (RDL) 13 is formed on the first insulating layer 12. A second insulating layer 14 is formed on the redistribution layer 13, and the second insulating layer 14 has a second opening 140 to expose part of the redistribution layer 13. An under bump metallization (UBM) 15 is formed on the exposed part of the redistribution layer 13, and a solder material is formed on the UBM 15 to form a solder bump 16.
[0005] However, considering the increase in the number of semiconductor chip input / output (I / O) and the density of the redistribution layer, the contact between the homogeneous insulating layers will decrease, and the contact between the insulating layer and the heterogeneous copper line (redistribution layer) will increase, causing delamination between the copper line and the insulating layer.
[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become an urgent issue to be solved. Invention content
[0007] In view of the above-mentioned deficiencies of the prior art, the present application provides a conductive bump structure formed on a semiconductor substrate having a pad and a passivation layer, which comprises: a first insulating layer formed on the passivation layer and having a first opening corresponding to the position of the pad so that the pad is exposed outside the first opening, and a second opening corresponding to the position of the passivation layer so that part of the passivation layer is exposed outside the second opening; a metal layer formed on the first insulating layer and electrically connected to the pad; a second insulating layer formed on the first insulating layer and the metal layer, and having a third opening corresponding to the position of the second opening so that the second opening and the third opening jointly form a groove structure; a conductive metal layer formed in the groove structure and electrically connected to the metal layer; and a metal bump formed on the conductive metal layer.
[0008] The present application also provides a method for forming a conductive bump structure on a semiconductor substrate having a pad and a passivation layer, which comprises: forming a first insulating layer on the semiconductor substrate, and forming a first opening corresponding to the position of the pad so that the pad is exposed outside the first opening, and a second opening corresponding to the position of the passivation layer so that part of the passivation layer is exposed outside the second opening; forming a metal layer on the first insulating layer and electrically connected to the pad; forming a second insulating layer on the first insulating layer and the metal layer, and the second insulating layer has a third opening corresponding to the position of the second opening so that the second opening and the third opening jointly form a groove structure; forming a conductive metal layer in the groove structure and electrically connected to the metal layer; and forming a metal bump on the conductive metal layer.
[0009] In the aforementioned conductive bump structure and method, the metal layer is a redistribution layer.
[0010] In the aforementioned conductive bump structure and method, the metal layer is formed on the first insulating layer, the pad exposed outside the first opening, and the passivation layer exposed outside the second opening.
[0011] In the aforementioned conductive bump structure and method, the metal layer is formed on the first insulating layer and the pad exposed outside the first opening, and does not extend to the passivation layer exposed outside the second opening.
[0012] In the aforementioned conductive bump structure and method, the conductive metal layer is an under-bump metal layer.
[0013] In the aforementioned conductive bump structure and method, the third opening has a size greater than that of the second opening, so that the second opening and the third opening jointly form a stepped groove structure.
[0014] From the above, the conductive bump structure of the present application mainly opens the second opening of the first insulating layer under the metal bump together with the first opening of the first insulating layer on the pad, and makes the third opening of the second insulating layer correspond to the position of the second opening to form a stepped groove structure, thereby dispersing the stress at the junction of the first insulating layer, the second insulating layer, the metal layer (RDL), and the conductive metal layer (UBM), avoiding stress concentration on the junction interface of different materials to cause delamination problems. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figures 1A-1D Process cross-sectional view of the existing solder bump.
[0016] Figures 2A-2E Process cross-sectional view of the first embodiment of the conductive bump structure of the present application.
[0017] Figures 3A-3E Process cross-sectional view of the second embodiment of the conductive bump structure of the present application.
[0018] REFERENCE NUMERALS
[0019] 10 wafer
[0020] 100 pad
[0021] 11 protective layer
[0022] 12 first insulating layer
[0023] 120 first opening
[0024] 13 RDL
[0025] 14 second insulating layer
[0026] 140 second opening
[0027] 15 bump under metal layer
[0028] 16 solder bump
[0029] 2, 3 conductive bump structure
[0030] 20, 30 semiconductor substrate
[0031] 200, 300 pad
[0032] 21, 31 protective layer
[0033] 210, 310 opening
[0034] 22, 32 first insulating layer
[0035] 221, 321 first opening
[0036] 222,322 Second opening
[0037] 23,33 Metal layers
[0038] 24,34 Second insulation layer
[0039] 243,343 Third opening
[0040] 25,35 Conductive metal layers
[0041] 26,36 metal bumps
[0042] w groove structure. Detailed Implementation
[0043] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0044] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0045] Please see Figures 2A-2E This is a cross-sectional schematic diagram of a first embodiment of the conductive bump structure of this application. The conductive bump structure is formed on a semiconductor substrate such as a wafer or a chip.
[0046] like Figure 2A As shown, a semiconductor substrate 20 having multiple pads 200 is provided. Since the processes performed on each pad are similar, only a single pad is shown in the figures.
[0047] In this embodiment, the semiconductor substrate 20 is a wafer; in other embodiments, the semiconductor substrate may also be a silicon substrate or a glass substrate. The semiconductor substrate 20 is covered with a protective layer 21, and the protective layer 21 has a plurality of openings 210, allowing the plurality of solder pads 200 to be exposed through the openings 210. Furthermore, the solder pads 200 may be made of aluminum, and the protective layer 21 may be made of silicon nitride (SiN) or silicon oxide (SiOX) as a passivation layer.
[0048] Next, a first insulating layer 22 is formed on the protective layer 21, and a plurality of first openings 221 and a plurality of second openings 222 are formed on the first insulating layer 22. The first openings 221 correspond to the positions of the solder pads 200, so that the solder pads 200 are exposed outside the first insulating layer 22. The second openings 222 do not correspond to the positions of the solder pads 200, so that a portion of the protective layer 21 is exposed outside the first insulating layer 22. In this embodiment, the material of the first insulating layer 22 may be polyimide (PI), benezocy-clobutene (BCB), or polybenzoxazole (PBO).
[0049] like Figure 2B As shown, a metal layer 23 is formed on the first insulating layer 22, the solder pad 200 exposed in the first opening 221, and the protective layer 21 exposed in the second opening 222. In this embodiment, the metal layer 23 is a copper layer, which serves as a circuit redistribution layer and electrically connects the metal layer 23 to the solder pad 200.
[0050] like Figure 2C As shown, a second insulating layer 24 is formed on the first insulating layer 22 and the metal layer 23, and a plurality of third openings 243 are formed on the second insulating layer 24, wherein the third openings 243 correspond to the positions of the second openings 222, so that the metal layer 23 formed in the second openings 222 is exposed by the third openings 243. In this embodiment, the size of the third openings 243 is larger than the size of the second openings 222, so that the second openings 222 and the third openings 243 together form a stepped groove structure w.
[0051] like Figure 2DAs shown, a conductive metal layer 25 is formed in the stepped groove structure w to serve as an under bump metallization (UBM) layer, and the conductive metal layer 25 is electrically connected to the metal layer 23 (circuit redistribution layer). In this embodiment, the material of the conductive metal layer 25 can be titanium / copper (Ti / Cu) or titanium / tungsten / copper (Ti / W / Cu), and the conductive metal layer 25 is stacked on the metal layer 23 that exposes the second opening 222.
[0052] like Figure 2E As shown, metal bumps 26 are formed on the conductive metal layer 25 to obtain the conductive bump structure 2 of this application. In this embodiment, the metal bumps 26 are, for example, solder bumps.
[0053] As can be seen from the aforementioned manufacturing method, this application pre-opens the second opening of the first insulating layer under the metal bump position together with the first opening of the first insulating layer on the solder pad, and makes the third opening of the second insulating layer correspond to the position of the second opening to form a stepped groove structure, thereby dispersing the stress at the junction of the first insulating layer, the second insulating layer, the metal layer (RDL), and the conductive metal layer (UBM) in a stepped manner, avoiding stress concentration at the interface of different materials and thus preventing delamination problems.
[0054] Please see Figures 3A-3E This is a cross-sectional schematic diagram of a second embodiment of the conductive bump structure fabrication method of this application. The main difference between this embodiment and the first embodiment lies in the change of the metal layer (RDL) layout range; other related processes are largely the same and will not be described in detail here.
[0055] like Figure 3A As shown, a semiconductor substrate 30 with a plurality of solder pads 300 is provided. The semiconductor substrate 30 is covered with a protective layer 31, and the protective layer 31 has a plurality of openings 310, so that the plurality of solder pads 300 are exposed through the plurality of openings 310. Next, a first insulating layer 32 is formed on the protective layer 31, and a plurality of first openings 321 and a plurality of second openings 322 are formed on the first insulating layer 32. The first openings 321 correspond to the positions of the solder pads 300, so that the solder pads 300 are exposed through the first insulating layer 32. The second openings 322 do not correspond to the positions of the solder pads 300, so that a portion of the protective layer 31 is exposed through the first insulating layer 32.
[0056] like Figure 3B As shown, a metal layer 33 (RDL) is formed on the first insulating layer 32 and the solder pad 300 exposed in the first opening 321, and the metal layer 33 is electrically connected to the solder pad 300. Unlike the first embodiment described above, in this embodiment, the metal layer 33 does not extend to the protective layer 31 exposed in the second opening 322.
[0057] As shown in FIG. 1, a first insulating layer 32 is formed on the substrate 30, and a metal layer 33 is formed on the first insulating layer 32. Figure 3C As shown in FIG. 2, a second insulating layer 34 is formed on the first insulating layer 32 and the metal layer 33, and a plurality of third openings 343 are formed on the second insulating layer 34, wherein the third openings 343 correspond to the positions of the second openings 322 to expose the protective layer 31 and the metal layer 33 formed on the first insulating layer 32 exposed from the second openings 322, wherein the size of the third openings 343 is greater than the size of the second openings 322, so that the second openings 322 and the third openings 343 together form a stepped recess structure w to expose part of the protective layer 31 and part of the metal layer 33 formed on the first insulating layer 31.
[0058] As shown in FIG. 3, a conductive metal layer 35 is formed in the stepped recess structure w as an under bump metallization (UBM), and the conductive metal layer 35 is electrically connected to the metal layer 33 formed on the first insulating layer 32. Figure 3D As shown in FIG. 4, a metal bump 36 is formed on the conductive metal layer 35 to obtain the conductive bump structure 3 of the present application.
[0059] Figure 3E As shown in FIG. 4, a metal bump 36 is formed on the conductive metal layer 35 to obtain the conductive bump structure 3 of the present application.
[0060] Through the above manufacturing method, the second openings of the first insulating layer under the position of the metal bump are opened together with the first openings of the first insulating layer on the solder pad, and the third openings of the second insulating layer correspond to the positions of the second openings to form a stepped recess structure, thereby dispersing the stress at the junctions of the first insulating layer, the second insulating layer, the metal layer (RDL), and the conductive metal layer (UBM) in a stepped manner, while the metal layer does not extend to the second openings, reducing the density of the metal layer, increasing the contact area between the homogeneous insulating layers to reduce the stress, and avoiding the stress concentration on the junction interface of different materials to cause delamination problems.
[0061] The application also provides a conductive bump structure 2, 3 formed on a semiconductor substrate 20, 30 having a pad 200, 300 and a protection layer 21, 31, wherein the protection layer 21, 31 is formed with an opening 210, 310 to expose the pad 200, 300, the conductive bump structure 2, 3 comprises: a first insulating layer 22, 32 formed on the protection layer 21, 31 and having a first opening 221, 321 corresponding to the position of the pad 200, 300 to expose the pad 200, 300, and a second opening 222, 322 corresponding to the position of the protection layer 21, 31 to expose part of the protection layer 21, 31; a metal layer 23, 33 formed on the first insulating layer 22, 32 and electrically connected to the pad 200, 300; a second insulating layer 24, 34 formed on the first insulating layer 22, 32 and the metal layer 23, 33, and the second insulating layer 24, 34 is formed with a third opening 243, 343 corresponding to the position of the second opening 222, 322 to form a groove structure w together with the second opening 222, 322 and the third opening 243, 343; a conductive metal layer 25, 35 formed in the groove structure w and electrically connected to the metal layer 23, 33; and a metal bump 26, 36 formed on the conductive metal layer 25, 35.
[0062] The metal layer 23, 33 is a redistribution layer, in one embodiment, the metal layer 23 is formed on the first insulating layer 22, the pad 200 exposed in the first opening 221, and the protection layer 21 exposed in the second opening 222. In another embodiment, the metal layer 33 is formed on the first insulating layer 32 and the pad 300 exposed in the first opening 321, but does not extend to the protection layer 31 exposed in the second opening 322.
[0063] The conductive metal layer 25, 35 is a bump under metal layer.
[0064] The size of the third opening 243, 343 is greater than the size of the second opening 222, 322, so that the second opening 222, 322 and the third opening 243, 343 form a stepped groove structure w.
[0065] In summary, the conductive bump structure of the present application mainly opens the second opening of the first insulating layer under the metal bump position together with the first opening of the first insulating layer on the pad, and makes the third opening of the second insulating layer correspond to the second opening position to form a stepped groove structure, thereby dispersing the stress at the junction of the first insulating layer, the second insulating layer, the metal layer (RDL), and the conductive metal layer (UBM), and avoiding stress concentration on the junction interface of different materials to cause delamination problems.
[0066] The above embodiments are only used to illustrate the principles and effects of the present application, and are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.
Claims
1. An electrically conductive bump structure formed on a semiconductor substrate having a pad and a protective layer, the structure comprising: Comprising: a first insulating layer formed on the protective layer and having a first opening corresponding to the position of the soldering pad so as to expose the soldering pad outside the first opening, and a second opening corresponding to the position of the protective layer so as to expose part of the protective layer outside the second opening; a metal layer formed on the first insulating layer and electrically connected to the soldering pad; a second insulating layer formed on the first insulating layer and the metal layer, and having a third opening corresponding to the position of the second opening so as to form a groove structure together with the second opening and the third opening; a conductive metal layer formed in the groove structure and electrically connected to the metal layer; and a metal bump formed on the conductive metal layer.
2. The conductive bump structure of claim 1, wherein, The metal layer is a redistribution layer.
3. The conductive bump structure of claim 1, wherein, The metal layer is formed on the first insulating layer, the soldering pad exposed outside the first opening, and the protective layer exposed outside the second opening.
4. The conductive bump structure of claim 1, wherein, The metal layer is formed on the first insulating layer and the soldering pad exposed outside the first opening, and does not extend to the protective layer exposed outside the second opening.
5. The conductive bump structure of claim 1, wherein, The conductive metal layer is an under-bump metal layer.
6. The conductive bump structure of claim 1, wherein, The third opening has a size greater than that of the second opening, so as to form a stepped groove structure together with the second opening and the third opening.