Low parasitic inductance package substrate and power module

Abstract

The utility model provides a low parasitic inductance packaging substrate and a power module. The low parasitic inductance packaging substrate comprises a first ceramic substrate, a first copper-clad layer, a second copper-clad layer, an electrical isolation structure and an electrical connection structure. The first copper-clad layer is arranged on the upper surface of the first ceramic substrate; the second copper-clad layer is arranged above the first copper-clad layer, and an electrical isolation structure is arranged between the second copper-clad layer and the first copper-clad layer; the plane where the first copper-clad layer is located is parallel to the plane where the second copper-clad layer is located. The projection of the first copper-clad layer in the vertical direction and the projection of the second copper-clad layer in the vertical direction are at least partially overlapped; the first end of the electric connection structure is electrically connected with the first copper-clad layer, and the second end is electrically connected with the second copper-clad layer. According to the utility model, the current flow path is spatially reversed through the stacked multiple copper-clad layers, so that the parasitic inductance is reduced, and the problem that the system is unstable and the like due to peak voltage generated by the power device during current conversion caused by overlarge parasitic inductance is solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a power device module, in particular to a low parasitic inductance package substrate. BACKGROUND

[0002] In the design of conventional multi-level power modules, single-layer DCB (Direct Copper Bonding) is usually used to mount power semiconductor devices. However, this packaging method has problems such as long commutation loop or electrical connection line, resulting in large parasitic inductance. During commutation, the parasitic inductance can cause overvoltage (Ldi / dt) on the turn-off devices inside the multi-level power module due to inductance, which can cause large turn-off peak and high voltage stress when the devices in the multi-level power module are turned off, damaging the devices or increasing device loss. It also affects the stability and reliability of the module. In addition, due to the increase of voltage stress caused by parasitic inductance, the switching frequency and efficiency of the module are also limited.

[0003] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art just because they are described in the background section of the present application. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a low parasitic inductance package substrate and a power module to solve the problem of large parasitic inductance in the prior art of single-layer DCB mounting power semiconductor.

[0005] To achieve the above-mentioned purposes and other related purposes, the utility model provides a low parasitic inductance package substrate, comprising:

[0006] a first ceramic substrate, a first copper clad layer, a second copper clad layer, an electrical isolation structure and an electrical connection structure;

[0007] The first copper clad layer is arranged on the upper surface of the first ceramic substrate;

[0008] The second copper clad layer is arranged above the first copper clad layer and an electrical isolation structure is arranged between the first copper clad layer and the second copper clad layer;

[0009] The plane on which the first copper clad layer is arranged and the plane on which the second copper clad layer is arranged are parallel to each other; the projection of the first copper clad layer in the vertical direction and the projection of the second copper clad layer in the vertical direction at least partially overlap; wherein the current flow directions in the first copper clad layer and the second copper clad layer are opposite;

[0010] The first end of the electric connection structure is electrically connected to the first copper clad layer, and the second end is electrically connected to the second copper clad layer.

[0011] Optionally, the first copper clad layer and the second copper clad layer both extend along a first direction.

[0012] Optionally, a projection of the first copper clad layer in a vertical direction completely covers a projection of the second copper clad layer in the vertical direction, or a projection of the second copper clad layer in the vertical direction completely covers a projection of the first copper clad layer in the vertical direction.

[0013] Optionally, the electric isolation structure is a second ceramic substrate.

[0014] Optionally, the electric connection structure is at least one chip, a back surface of the chip is connected to the first copper clad layer, and a front surface of the chip is connected to the second copper clad layer.

[0015] Optionally, a solder layer is further arranged between the back surface of the chip and the first copper clad layer.

[0016] Optionally, the electric connection structure is at least one lead wire, a first end of the lead wire is connected to the first copper clad layer, and a second end of the lead wire is connected to the second copper clad layer.

[0017] To achieve the above object and other related objects, the utility model provides a kind of power module, including first transistor, second transistor and the low parasitic inductance package substrate of described;

[0018] The first end of the first transistor is connected to the positive electrode of power supply through the first connection path, the second end receives the first control signal, and the third end is connected to the first end of the second transistor through the second connection path.

[0019] The first end of the second transistor serves as an output node, the second end receives the second control signal, and the third end is connected to the negative electrode of power supply through the third connection path.

[0020] The first connection path, the second connection path and the third connection path are all arranged on the low parasitic inductance package substrate.

[0021] To achieve the above object and other related objects, the utility model provides a kind of power module, including third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, capacitor and the low parasitic inductance package substrate of described;

[0022] The first end of the third transistor is connected to the first plate of capacitor through the fourth connection path, the second end receives the third control signal, and the third end is connected to the first end of the fourth transistor.

[0023] The second end of the fourth transistor receives a fourth control signal, and the third end serves as an output node of the power module;

[0024] The first end of the fifth transistor is connected to the third end of the fourth transistor, the second end receives a fifth control signal, and the third end is connected to the first end of the sixth transistor;

[0025] The second end of the sixth transistor receives a sixth control signal, and the third end is connected to the negative electrode of the power supply through a fifth connection path;

[0026] The first end of the seventh transistor is connected to the third end of the third transistor through a sixth connection path, the second end receives a seventh control signal, and the third end is connected to the second plate of the capacitor through a seventh connection path;

[0027] The second plate of the capacitor is connected to the positive electrode of the power supply;

[0028] The first end of the eighth transistor is connected to the third end of the seventh transistor, the second end receives an eighth control signal, and the third end is connected to the positive electrode of the power supply through an eighth connection path.

[0029] To achieve the above object and other related objects, the utility model provides a kind of power module, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, first diode, second diode, capacitor and the low parasitic inductance package substrate described in;

[0030] The first end of the ninth transistor is connected to the first plate of the capacitor through a ninth connection path, the second end receives a ninth control signal, and the third end is connected to the first end of the tenth transistor;

[0031] The second end of the tenth transistor receives a tenth control signal, and the third end serves as an output node of the power module;

[0032] The first end of the eleventh transistor is connected to the third end of the tenth transistor, the second end receives an eleventh control signal, and the third end is connected to the first end of the twelfth transistor;

[0033] The second end of the twelfth transistor receives a twelfth control signal, and the third end is connected to the negative electrode of the power supply through a tenth connection path;

[0034] The first end of the first diode is connected to the third end of the ninth transistor through an eleventh connection path, and the second end is connected to the second plate of the capacitor through a twelfth connection path;

[0035] The second plate of the capacitor is connected to the positive electrode of the power supply;

[0036] The first end of the second diode is connected to the second end of the first diode, and the second end is connected to a positive pole of a power supply through a thirteenth connecting path.

[0037] As described above, the low parasitic inductance packaging substrate and the power module have the following beneficial effects:

[0038] 1、The current flow path is reversed in space by the stacked multilayer copper clad layer, the parasitic inductance is reduced, and the problems such as the peak voltage generated during commutation of the power device due to excessive parasitic inductance, and finally leading to system instability are avoided.

[0039] 2、The current flow path is reversed in space by the stacked multilayer copper clad layer, the magnetic field between the stacked copper clad layers is offset, the current balance and the current density are better realized, so as to reduce thermal stress, optimize the heat conduction path, enable the module to effectively dissipate heat during the working process, reduce the maximum junction temperature of the chip, prolong the service life of the device, and improve the reliability and performance of the module.

[0040] 3、The utility model is favorable for reducing energy loss, avoiding high voltage stress, and can also significantly enhance electromagnetic compatibility.

[0041] 4、The utility model is suitable for optimizing the gate drive signal transmission path, optimizing the signal transmission path, reducing parasitic oscillation and delay, and improving switching stability. DETAILED DESCRIPTION

[0042] Figure 1 The structure diagram of the low parasitic inductance packaging substrate of the utility model is shown.

[0043] Figure 2 The principle diagram of the low parasitic inductance packaging substrate of the utility model is shown.

[0044] Figure 3 The overall schematic diagram of the power module of the utility model is shown.

[0045] Figure 4 The exploded schematic diagram of the power module of the utility model is shown.

[0046] Figure 5 The circuit schematic diagram of the first power module of the utility model is shown.

[0047] Figure 6 The circuit schematic diagram of the second power module of the utility model is shown.

[0048] Figure 7 The circuit schematic diagram of the third power module of the utility model is shown.

[0049] Figure 8The waveform diagram before and after the turn-off of the power device in the power module using the low parasitic inductance packaging substrate is shown.

[0050] Figure 9 The waveform diagram before and after the turn-off of the power device in the power module using the low parasitic inductance packaging substrate is shown.

[0051] Element number explanation

[0052] 1 power module

[0053] 11 low parasitic inductance packaging substrate

[0054] 111 first ceramic substrate

[0055] 112 first copper clad layer

[0056] 113 second copper clad layer

[0057] 114 second ceramic substrate

[0058] 115 chip

[0059] 116 solder layer

[0060] 117 control terminal

[0061] 12 cover plate

[0062] 13 carrier plate DETAILED DESCRIPTION

[0063] The embodiments of the present application will be described in detail with specific examples. The skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0064] Please refer to Figures 1-9 . It should be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and the drawings only show the components related to the present application, not the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be randomly changed, and the component layout pattern can be more complex.

[0065] As Figure 1 shown, the present embodiment provides a low parasitic inductance packaging substrate 11, which comprises a first ceramic substrate 111, a first copper clad layer 112, a second copper clad layer 113, an electrical isolation structure and an electrical connection structure.

[0066] As shown in Figure 1 , the first copper clad layer 112 is disposed on the upper surface of the first ceramic substrate 111. In this embodiment, the copper foil is directly sintered on the ceramic surface by using the manufacturing process of the direct bond copper (DBC) ceramic substrate, so that the composite substrate has the characteristics of high thermal conductivity, high electrical insulation, high mechanical strength, low expansion and the like of the ceramic, and also has the high electrical conductivity and excellent soldering performance of oxygen-free copper, and can be etched into various patterns like a PCB circuit board.

[0067] As shown in Figure 1 , the second copper clad layer 113 is disposed above the first copper clad layer 112 and an electrical isolation structure is disposed between the first copper clad layer 112 and the second copper clad layer 113.

[0068] Specifically, the electrical isolation structure is provided as a second ceramic substrate 114. The second copper clad layer 113 can also be covered on the second ceramic substrate 114 based on the direct bond copper ceramic substrate process and isolated from the first copper clad layer 112 based on the second ceramic substrate 114.

[0069] In this embodiment, the electrical isolation structure is provided as a second ceramic substrate 114, so that the same soldering process as the conventional power module can be directly used, so that the mounting of the multilayer DCB stack and the IGBT chip can be completed in the same process, reducing the manufacturing steps and complexity, thereby reducing the production cost. Similarly, the integration of the soldering process also ensures the mechanical strength and electrical conductivity between the stacks, so that the module performs better reliability and stability in high power and high current applications. Specifically, the soldering of the multilayer stack is completed by reflow soldering or silver sintering and the like. Reflow soldering is suitable for mass production and can quickly and efficiently realize the mounting of the multilayer structure, while silver sintering is suitable for high temperature environment applications and can provide higher thermal and electrical conductivity.

[0070] It should be noted that the electrical isolation structure can also be provided as other isolation structures, as long as it can be electrically isolated between the two copper clad layers, which is within the protection scope of this embodiment.

[0071] As shown in Figure 1 , the plane where the first copper clad layer 112 is located and the plane where the second copper clad layer 113 is located are parallel to each other; the projection of the first copper clad layer 112 in the vertical direction and the projection of the second copper clad layer 113 in the vertical direction at least partially overlap. Among them, the current flow directions in the first copper clad layer 112 and the second copper clad layer 113 are at least partially opposite to each other to perform electromagnetic cancellation.

[0072] Specifically, as shown in Figure 2As shown, by overlapping the single-layer conductive loops in space, on the one hand, the through-flow area directly affects the parasitic inductance of the loop, which can significantly reduce the parasitic inductance, limit and reduce the voltage stress of the inner tube power device, and at the same time, the larger copper area can also significantly reduce the on-state voltage drop of the loop and reduce the on-state loss; on the other hand, the current directions of the upper and lower layers are partially or completely reversed to ensure that the magnetic field is offset, better achieve current balance and reduce current density, thereby reducing thermal stress, optimizing the heat conduction path, enabling the module to effectively dissipate heat during operation, reducing the maximum junction temperature of the chip, prolonging the service life of the device, and improving the reliability and performance of the module.

[0073] In the embodiment, as shown in Figure 2 the total equivalent inductance of the embodiment satisfies Ltotal=Lp+Ln-2M. Lp and Ln are the equivalent inductances of the two copper layers with opposite current directions, and M (Mutual Inductance) is the mutual inductance coefficient between the two copper layers. Therefore, in the embodiment, the current flow directions between the two copper layers are partially opposite (such as when one is straight and one is "L" shaped, the "L" part is opposite to the straight current flow direction), which can ensure that the electromagnetic field is partially offset.

[0074] Specifically, in the embodiment, as shown in Figure 1 the first copper layer 112 and the second copper layer 113 both extend along the first direction (X direction).

[0075] As a first example, the projection of the first copper layer 112 in the vertical direction completely covers the projection of the second copper layer 113 in the vertical direction. That is, the projection area of the first copper layer 112 is greater than or equal to the projection area of the second copper layer 113, and the projection area of the second copper layer 113 is completely contained in the projection area of the first copper layer 112, at which time the magnetic field offset of the second copper layer 113 is the largest.

[0076] As a second example, the projection of the second copper layer 113 in the vertical direction completely covers the projection of the first copper layer 112 in the vertical direction. That is, the projection area of the first copper layer 112 is less than or equal to the projection area of the second copper layer 113, and the projection area of the first copper layer 112 is completely contained in the projection area of the second copper layer 113, at which time the magnetic field offset of the first copper layer 112 is the largest.

[0077] It should be noted that when the two areas of the first copper layer 112 and the second copper layer 113 are completely equal, the magnetic field offset effect is the best, but as long as the first copper layer 112 and the second copper layer 113 can offset to a certain extent in actual application, it belongs to the protection scope of the embodiment.

[0078] As shown in Figure 1As shown, the first end of the electric connection structure is electrically connected to the first copper layer 112, and the second end is electrically connected to the second copper layer 113.

[0079] Specifically, in the first example, the electric connection structure is provided as at least one chip 115; the back surface of the chip 115 is connected to the first copper layer 112, and the front surface of the chip 115 is connected to the second copper layer 113.

[0080] In the embodiment, as shown in Figure 1 The back surface of the chip 115 and the first copper layer 112 are further provided with a solder layer 116. At this time, the current flows in the first copper layer 112 along the x direction, and is connected to the second copper layer 113 through the chip 115, and the current flow direction in the second copper layer 113 is in the opposite direction along the x direction.

[0081] Specifically, in the second example (not shown in the figure), the electric connection structure is provided as at least one lead; the first end of the lead is connected to the first copper layer 112, and the second end is connected to the second copper layer 113.

[0082] It should be noted that the electric connection structure is not limited to the embodiment, and any structure that can ensure that the current direction between the first copper layer 112 and the second copper layer 113 is different, thereby ensuring that the magnetic field is partially or completely offset, is within the protection scope of the embodiment.

[0083] As shown in Figure 3 and Figure 4 The power module 1 is taken as an example, wherein the power module 1 at least includes a cover plate 12 and a carrier plate 13; the carrier plate is provided with a plurality of chips 115 and a low parasitic inductance packaging substrate 11, and each chip 115 is electrically connected through the low parasitic inductance packaging substrate 11. At this time, the first copper layer 112 and the second copper layer 113 in the low parasitic inductance packaging substrate 11 are both in the shape of “L”, and are electrically isolated through the second ceramic substrate 114. A control terminal 117 is further provided thereon for lead-out. It can be clearly seen from Figure 5 that the circuit length of the first copper layer 112 and the second copper layer 113 is reduced in the lateral area and stacked in the longitudinal space compared with the single-layer copper setting.

[0084] It should be noted that the stack of the embodiment is not limited to two layers, and any design of the low parasitic inductance packaging substrate 11 based on the stacking of at least two copper-clad layers is within the protection scope of the embodiment. In order to further optimize the power module 1, when the plurality of elements in the power module 1 are interconnected through the low parasitic inductance packaging substrate 11, the shortest path and the maximum current-carrying area need to be considered to reduce the inductive coupling between the power devices. In actual implementation, a multi-layer parallel structure is first set to stack the DCB to further reduce the parasitic inductance, and the connection between the stacked DCBs is also welded to minimize the overall parasitic inductance, thereby maintaining a small voltage spike and energy loss during high-frequency switching.

[0085] As shown in Figure 5 , the embodiment further provides a first power module, which includes a first transistor T1, a second transistor T2, and the low parasitic inductance packaging substrate 11 described above.

[0086] Specifically, the first end of the first transistor T1 is connected to the positive electrode of the power supply through the first connection path L1, the second end receives a first control signal, and the third end is connected to the first end of the second transistor T2 through the second connection path L2; the first end of the second transistor T2 serves as an output node o, the second end receives a second control signal, and the third end is connected to the negative electrode of the power supply through the third connection path L3.

[0087] Among them, the first connection path L1, the second connection path L2 and the third connection path L3 are all arranged on the low parasitic inductance packaging substrate 11. That is, in the embodiment, the first connection path L1, the second connection path L2 and the third connection path L3 are all connected in a stacked connection manner, which can further improve the integration of the first power module and reduce the parasitic inductance of the first connection path L1, the second connection path L2 and the third connection path L3 respectively.

[0088] In the embodiment, when the power device (transistor) in the power module switches, the current path is switched between path a and path b, and the low parasitic inductance packaging substrate 11 of the embodiment reduces the parasitic inductance in the path switching process.

[0089] As shown in Figure 6 , the embodiment further provides a second power module, which includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitor C, and the low parasitic inductance packaging substrate 11 described above.

[0090] Specifically, the first end of the third transistor T3 is connected to the first plate of the capacitor C via the fourth connection path L4, the second end receives the third control signal, and the third end is connected to the first end of the fourth transistor T4. The second end of the fourth transistor T4 receives the fourth control signal, and the third end is the output node O of the power module; the first end of the fifth transistor T5 is connected to the third end of the fourth transistor, the second end receives the fifth control signal, and the third end is connected to the first end of the sixth transistor T6; the second end of the sixth transistor T6 receives the sixth control signal, and the third end is connected to the negative electrode of the power supply via the fifth connection path L5; the first end of the seventh transistor T7 is connected to the third end of the third transistor T3 via the sixth connection path L6, the second end receives the seventh control signal, and the third end is connected to the second plate of the capacitor C via the seventh connection path L7; the second plate of the capacitor C is connected to the positive electrode of the power supply; the first end of the eighth transistor T8 is connected to the third end of the seventh transistor T7, the second end receives the eighth control signal, and the third end is connected to the positive electrode of the power supply via the eighth connection path L8.

[0091] Among them, the fourth connection path L4, the fifth connection path L5, the sixth connection path L6, the seventh connection path L7, and the eighth connection path L8 are all arranged on the low parasitic inductance packaging substrate 11. That is, in the embodiment, the fourth connection path L4, the fifth connection path L5, the sixth connection path L6, the seventh connection path L7, and the eighth connection path L8 are all connected in a laminated connection manner, which can further improve the integration of the second power module and reduce the parasitic inductance of each connection path

[0092] It should be noted that when the fourth transistor T4 or the sixth transistor T6 is turned off, the commutation loop path (that is, the area surrounded by part A between path c and path b in the figure) will change greatly, affecting the stability and reliability of the module when the second power module is not used with the low parasitic inductance packaging substrate 11 of the embodiment. However, after using the low parasitic inductance packaging substrate 11 provided in the embodiment, the length of each path in the commutation loop path will be significantly shortened, especially the length of the fourth connection path L3 will be greatly reduced, so that the parasitic inductance and voltage stress at this position are reduced, thereby ensuring the stability of the power module.

[0093] As Figure 7As shown, the third power module also provided in the embodiment includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a first diode D1, a second diode D2, a capacitor C, and the low parasitic inductance packaging substrate as described above. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are respectively the same as the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 of the second power module, and the ninth connection path L9, the tenth connection path L10, the eleventh connection path L11, the twelfth connection path L12, and the thirteenth connection path L13 are respectively the same as the fourth connection path L4, the fifth connection path L5, the sixth connection path L6, the seventh connection path L7, and the eighth connection path L8. Details are not described herein.

[0094] In addition, the third power module only replaces the seventh transistor T7 and the eighth transistor T8 with the first diode D1 and the second diode D2.

[0095] The first end of the first diode D1 is connected to the third end of the ninth transistor T9 through the eleventh connection path L11, and the second end is connected to the second plate of the capacitor C through the twelfth connection path L12. The first end of the second diode D2 is connected to the second end of the first diode D1, and the second end is connected to the positive electrode of the power supply through the thirteenth connection path L13.

[0096] The ninth connection path L9, the tenth connection path L10, the eleventh connection path L11, the twelfth connection path L12, and the thirteenth connection path L13 can further improve the integration of the third power module and reduce the parasitic inductance of each connection path, which is basically the same as the second power module. At the same time, the commutation loop path (that is, the area B surrounded by part B between path e and path f in the figure) will change greatly, which can effectively reduce the parasitic capacitance, which is basically the same as the second power module.

[0097] It should be noted that in the power module of the embodiment, each transistor is provided as an IGBT tube, and can also be provided as other types of transistors according to actual needs, and is not limited to the embodiment. Similarly, the low parasitic inductance packaging substrate 11 of the embodiment can be applied to any configuration of the power module, and is not limited to the embodiment. The low parasitic inductance packaging substrate 11 provided by the embodiment can effectively solve the problem of long commutation loop parasitic inductance caused by single-layer DCB packaging in multi-level topology power modules (such as ANPC, NPC, and TNPC), so as to reduce the path area of the multi-level working large loop, thereby effectively reducing the parasitic inductance and reducing the peak voltage in the commutation process. The specific principle has been described in the foregoing, and details are not described herein.

[0098] It needs to be further explained that the specific connection direction is not limited to the power module provided in the embodiment, as long as the connection between the components in the power module is ensured through the low parasitic inductance packaging substrate 11 of the embodiment. In addition, the connection path (gate wiring) of each control signal can also be connected based on the low parasitic inductance packaging substrate 11 of the embodiment, and is not limited to Figures 5-7 The gate wiring is optimized, avoiding interference with the power loop, thereby retaining a larger current-carrying area. Among them, the gate wiring optimization and the optimization of each connection path are separated from each other to minimize the interference with the power loop. The laminated design of the gate part makes the gate wiring more compact, effectively shortening the transmission path of the gate signal, reducing parasitic inductance and parasitic capacitance, thereby avoiding signal delay and oscillation phenomena caused by wire length. In the gate drive part, by using high-speed drive chips and laminated busbar structures, the switching speed and accuracy are further improved, ensuring that the power module can quickly respond to control signals and achieve efficient and stable switching operations.

[0099] The effects of the low parasitic inductance packaging substrate 11 of the embodiment are described in combination with Figure 8 and Figure 9 . Figure 8 For single-layer DBC process, the voltage change of the process end voltage spike before and after the fourth transistor T4 in the second power module is turned off under the condition of 200A current; Figure 9 For the low parasitic inductance packaging substrate 11 provided in the embodiment, the voltage change of the process end voltage spike before and after the fourth transistor T4 in the second power module is turned off under the condition of 200A current, Figure 8 . Without using a laminated chip, the turn-off voltage peak is 920V (power supply voltage 750V), Figure 9 is the turn-off voltage peak of 830V using the laminated scheme, the peak voltage is reduced by 90V, and the voltage safety margin of the 90V chip is improved by 90V.

[0100] Therefore, through the low parasitic inductance packaging substrate 11 stack design and the magnetic field cancellation mechanism of the upper and lower layer currents of the embodiment, the parasitic inductance is effectively reduced, and the peak voltage generated during commutation is reduced. Test results show that compared with the power module with traditional single-layer DCB design, the peak voltage of the power module of the embodiment is reduced by about 30% during commutation, and the parasitic inductance is reduced by about 40%.

[0101] At the same time, due to the reduction of parasitic inductance, the energy loss generated by the power module in the high-frequency switching process is reduced, and the system efficiency is significantly improved. Based on the experimental data, the efficiency of the power module designed in this embodiment is improved by about 5%, because the larger copper area also reduces the on-state voltage drop and reduces the conduction loss, thereby further improving the overall efficiency of the system.

[0102] In addition, the system reliability of the power module of the embodiment is significantly enhanced, because the parasitic inductance and voltage spike are reduced, the voltage stress of the power device in the power module is reduced, the device damage caused by high voltage stress is avoided, and the reliability of the module is improved. At the same time, the technology of the embodiment can be used for gate drive optimization in the power module, which can further optimize the signal transmission path, reduce parasitic oscillation and delay, and improve switching stability.

[0103] Similarly, the electromagnetic compatibility of the power module of the embodiment is significantly enhanced, because the reverse magnetic field of the upper and lower layer currents cancels out, the electromagnetic interference (EMI) of the power module is significantly reduced, thereby improving the electromagnetic compatibility of the entire system and reducing the interference to other electronic devices.

[0104] In summary, the low parasitic inductance packaging substrate and the power module provided by the utility model have the advantages that the low parasitic inductance packaging substrate includes a first ceramic substrate, a first copper clad layer, a second copper clad layer, an electrical isolation structure and an electrical connection structure, the first copper clad layer is arranged on the upper surface of the first ceramic substrate, the second copper clad layer is arranged above the first copper clad layer and the electrical isolation structure is arranged between the first copper clad layer and the second copper clad layer, the plane where the first copper clad layer is located and the plane where the second copper clad layer is located are parallel to each other, the projection of the first copper clad layer in the vertical direction and the projection of the second copper clad layer in the vertical direction at least partially overlap, the first end of the electrical connection structure is electrically connected with the first copper clad layer, and the second end of the electrical connection structure is electrically connected with the second copper clad layer, the current flow path is reversed in space by the stacked multiple copper clad layers, the parasitic inductance is reduced, the peak voltage generated when the power device switches due to excessive parasitic inductance is avoided, and problems such as instability of the system are ultimately avoided. Therefore, the utility model effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0105] The above embodiments only exemplarily illustrate the principles and effects of the utility model, and are not used to limit the utility model. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the utility model. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the utility model should be covered by the claims of the utility model.

Claims

1. A low parasitic inductance package substrate, characterized by, The low parasitic inductance packaging substrate comprises a first ceramic substrate, a first copper clad layer, a second copper clad layer, an electrical isolation structure and an electrical connection structure; The first copper clad layer is arranged on the upper surface of the first ceramic substrate; The second copper clad layer is arranged above the first copper clad layer and an electrical isolation structure is arranged between the first copper clad layer and the second copper clad layer; The plane on which the first copper clad layer is arranged and the plane on which the second copper clad layer is arranged are parallel to each other; the projection of the first copper clad layer in the vertical direction and the projection of the second copper clad layer in the vertical direction at least partially overlap; the current flow directions in the first copper clad layer and the second copper clad layer are opposite to each other; The first end of the electrical connection structure is electrically connected to the first copper clad layer, and the second end of the electrical connection structure is electrically connected to the second copper clad layer.

2. The low parasitic inductance package substrate of claim 1, wherein: The first copper clad layer and the second copper clad layer both extend along a first direction.

3. The low parasitic inductance package substrate of claim 2, wherein: The projection of the first copper clad layer in the vertical direction completely covers the projection of the second copper clad layer in the vertical direction; or the projection of the second copper clad layer in the vertical direction completely covers the projection of the first copper clad layer in the vertical direction.

4. The low parasitic inductance package substrate of claim 1, wherein: The electrical isolation structure is arranged as a second ceramic substrate.

5. The low parasitic inductance package substrate of claim 1, wherein: The electrical connection structure is arranged as at least one chip; the back surface of the chip is connected to the first copper clad layer, and the front surface of the chip is connected to the second copper clad layer.

6. The low parasitic inductance package substrate of claim 5, wherein: A solder layer is further arranged between the back surface of the chip and the first copper clad layer.

7. The low parasitic inductance package substrate of claim 1, wherein: The electrical connection structure is arranged as at least one lead; the first end of the lead is connected to the first copper clad layer, and the second end of the lead is connected to the second copper clad layer.

8. A power module, characterized by: The power module comprises a first transistor, a second transistor and the low parasitic inductance packaging substrate according to any one of claims 1 to 7; The first end of the first transistor is connected to the positive electrode of a power supply through a first connection path, the second end of the first transistor receives a first control signal, and the third end of the first transistor is connected to the first end of the second transistor through a second connection path; The first end of the second transistor serves as an output node, the second end of the second transistor receives a second control signal, and the third end of the second transistor is connected to the negative electrode of the power supply through a third connection path; The first connection path, the second connection path and the third connection path are all arranged on the low parasitic inductance packaging substrate.

9. A power module, characterized by: The power module comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a capacitor, and the low parasitic inductance packaging substrate according to any one of claims 1 to 7; The first end of the third transistor is connected to the first plate of the capacitor through a fourth connection path, the second end of the third transistor receives a third control signal, and the third end of the third transistor is connected to the first end of the fourth transistor; The second end of the fourth transistor receives a fourth control signal, and the third end of the fourth transistor serves as an output node of the power module; The first end of the fifth transistor is connected to the third end of the fourth transistor, the second end of the fifth transistor receives a fifth control signal, and the third end of the fifth transistor is connected to the first end of the sixth transistor; The second end of the sixth transistor receives a sixth control signal, and the third end of the sixth transistor is connected to the negative electrode of the power supply through a fifth connection path; The first end of the seventh transistor is connected to the third end of the third transistor through a sixth connecting path, the second end receives a seventh control signal, and the third end is connected to the second plate of the capacitor through a seventh connecting path; The second plate of the capacitor is connected to a positive electrode of a power supply; The first end of the eighth transistor is connected to the third end of the seventh transistor, the second end receives an eighth control signal, and the third end is connected to the positive electrode of the power supply through an eighth connecting path.

10. A power module, characterized by: The power module comprises a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first diode, a second diode, a capacitor, and the low parasitic inductance package substrate according to any one of claims 1-7; The first end of the ninth transistor is connected to the first plate of the capacitor through a ninth connecting path, the second end receives a ninth control signal, and the third end is connected to the first end of the tenth transistor; The second end of the tenth transistor receives a tenth control signal, and the third end is an output node of the power module; The first end of the eleventh transistor is connected to the third end of the tenth transistor, the second end receives an eleventh control signal, and the third end is connected to the first end of the twelfth transistor; The second end of the twelfth transistor receives a twelfth control signal, and the third end is connected to a negative electrode of a power supply through a tenth connecting path; The first end of the first diode is connected to the third end of the ninth transistor through an eleventh connecting path, and the second end is connected to the second plate of the capacitor through a twelfth connecting path; The second plate of the capacitor is connected to a positive electrode of a power supply; The first end of the second diode is connected to the second end of the first diode, and the second end is connected to the positive electrode of the power supply through a thirteenth connecting path.

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