Soft start hardware circuit and capacitive load device

Abstract

The utility model relates to the technical field of soft start, and discloses a soft start hardware circuit and capacitive load equipment, the soft start hardware circuit comprises a power supply module, a pre-discharge driving module and a discharge MOS delay driving module, the power supply module comprises an output port negative electrode end, a battery negative electrode end and a discharge MOS control end; one end of the pre-discharge driving module is connected with the negative electrode end of the output port, the other end of the pre-discharge driving module is connected with the discharge MOS control end, and the discharge MOS control end is used for controlling the on or off of the pre-discharge driving module; and the discharge MOS time-delay driving module is connected between the output port negative electrode end and the battery negative electrode end, is in control connection with the discharge MOS control end, and is used for controlling the on or off of the discharge MOS time-delay driving module at the output port negative electrode end and the battery negative electrode end. According to the invention, the pre-discharge low-current pre-charge large capacitor is firstly started before starting or starting, and then the discharge MOS infinite-current discharge loop is started, so that the impact of large current is prevented, the service life of the battery is prolonged, the overall design is simple, the cost is low, and the operation stability is high.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of soft starting, and particularly relates to a soft starting hardware circuit and a capacitive load device. BACKGROUND

[0002] Generally, high-power electrical equipment has the demand for soft starting. For a capacitive load device powered by a battery, soft starting generally refers to gradually increasing the load in the circuit by controlling the change of current when the device starts, so as to avoid the impact of instantaneous large current on the battery and prolong the service life of the battery. At the same time, it can also avoid unstable operation or failure of the device caused by instantaneous large current. In the application of a software protection board, a small current can be used to pre-charge the capacitive load through a program before a large current circuit is turned on, so as to realize the soft starting function at the battery end.

[0003] For a low-cost high-power hardware protection board project, there is also the demand for soft starting function. However, the current soft starting function design is complex and high in cost. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the problems of the prior art, the application provides a soft starting hardware circuit, which realizes the pre-charge of a large capacitor by a small pre-discharge current before starting, and then turns on a discharge MOS currentless discharge circuit, so as to prevent the device failure and shorten the service life of the battery caused by large current impact, and provides protection for the device. The overall design is simple, and the function of soft starting of a large capacitive load is realized at a very low cost.

[0005] The technical effects achieved by the application are achieved through the following aspects:

[0006] In a first aspect, the application provides a soft starting hardware circuit, which comprises

[0007] a power module, a pre-discharge driving module, and a discharge MOS delay driving module.

[0008] The power module comprises an output negative terminal, a battery negative terminal, and a discharge MOS control terminal.

[0009] The pre-discharge driving module is connected to the output negative terminal, and the other end of the pre-discharge driving module is connected to the discharge MOS control terminal. The discharge MOS control terminal is used to control the conduction or cutoff of the pre-discharge driving module.

[0010] In some implementations, the pre-discharge driving module comprises:

[0011] a first control unit having an input end connected to the discharge MOS control end; and

[0012] a first switch unit having a control end connected to an output end of the first control unit, and having an input end connected to the output end negative terminal.

[0013] In some implementations, the first control unit includes:

[0014] a resistor R6 having one end connected to the discharge MOS control end;

[0015] a NAND gate U1A having an input end connected to the resistor R6; and

[0016] a NAND gate U1B having an input end connected to an output end of the NAND gate U1A, and having an output end connected to the first switch unit.

[0017] In some implementations, the first switch unit includes:

[0018] a resistor R34 having one end connected to the output end of the first control unit;

[0019] a transistor Q4 having a control end connected to the resistor R34, and having an output end connected between the output end negative terminal and the battery negative terminal; and

[0020] a resistor R36 connected in series with the transistor Q4.

[0021] In some implementations, the discharge MOS delay drive module includes:

[0022] a delay unit having one end connected to the discharge MOS control end;

[0023] a second control unit having an input end connected to another end of the delay unit; and

[0024] a second switch unit having a control end connected to an output end of the second control unit, and having an input end connected to the output end negative terminal, and having an output end connected to the battery negative terminal.

[0025] In some implementations, the delay unit includes:

[0026] a capacitor C5 having one end connected to the input end of the second control unit, and having another end connected to ground;

[0027] a capacitor C6 connected in parallel with the capacitor C5; and

[0028] A resistor R40 is connected in series with the capacitor C5, and the resistor R40 is connected with the discharge MOS control end and the input end of the second control unit.

[0029] In some implementations, the second control unit includes a NAND gate U1C and a NAND gate U1D connected in series, the input end of the NAND gate U1C is connected with the delay unit, the output end of the NAND gate U1C is connected with the input end of the NAND gate U1D, and the output end of the NAND gate U1D is connected with the second switch unit.

[0030] In some implementations, the second switch unit includes transistors M5 and M6 connected in parallel, and the control ends of the transistors M5 and M6 are connected with the output end of the NAND gate U1D.

[0031] In some implementations, the power module includes a step-down unit including a transistor Q6 and a transistor Q7, the collector of the transistor Q6 and the base of the transistor Q6 are connected with the output negative end, the emitter of the transistor Q6 is connected with the base of the transistor Q7, the collector of the transistor Q7 is connected with the output negative end, and the emitter of the transistor Q7 is connected with a voltage source V11.

[0032] In a second aspect, the application provides a capacitive load device including a control module provided with a soft start hardware circuit, wherein the soft start hardware circuit adopts the above soft start hardware circuit.

[0033] In summary, the application has at least the following advantages:

[0034] The soft start hardware circuit provided by the application is controlled by the discharge MOS control end through the switch of the pre-discharge driving module. When the discharge MOS control end outputs a high level, the pre-discharge driving module is turned on, so that the battery pack and the load form a current-limiting loop in series with the corresponding resistor. Secondly, the switch of the discharge MOS delay driving module is also controlled by the discharge MOS control end. When the discharge MOS control end outputs a high level, the discharge MOS delay driving module is turned on, which realizes that the pre-discharge 1S small current pre-charge large capacitor is started first before starting, and then the discharge MOS currentless discharge loop is started. Thus, the problems such as device failure caused by large current impact, shortening of battery life, etc. are prevented, and the device is protected. The overall design is simple, and the function of soft starting of large capacitive load is realized at a very low cost. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a structural schematic diagram of a soft start hardware circuit in Embodiment 1 of the application.

[0036] Figure 2Another structural schematic diagram of the soft start hardware circuit in Embodiment 1 of the present application.

[0037] Figure 3 A structural schematic diagram of the soft start hardware circuit in Embodiment 2 of the present application.

[0038] Figure 4 Another structural schematic diagram of the soft start hardware circuit in Embodiment 2 of the present application.

[0039] Figure 5 A structural schematic diagram of the capacitive load device in Embodiment 3 of the present application.

[0040] Markings in the figure:

[0041] 100, soft start hardware circuit, DS-, output negative terminal, B-, battery negative terminal, DSG, discharge MOS control terminal, 11, voltage reduction unit;

[0042] 2, pre-discharge driving module, 21, first control unit, 22, first switch unit;

[0043] 3, discharge MOS delay driving module, 31, delay unit, 32, second control unit, 33, second switch unit;

[0044] 200, control module;

[0045] 300, capacitive load device. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application.

[0047] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present application.

[0048] Embodiment 1:

[0049] Please refer to the drawings Figure 1 - the drawings Figure 2 A soft start hardware circuit of the present application includes a power module, a pre-discharge driving module 2 and a discharge MOS delay driving module 3.

[0050] The power module comprises an output negative terminal DS-, a battery negative terminal B- and a discharge MOS control terminal DSG.

[0051] One end of the pre-discharge driving module 2 is connected to the output negative terminal DS-, and the other end of the pre-discharge driving module 2 is connected to the discharge MOS control terminal DSG, which is used to control the conduction or cutoff of the pre-discharge driving module 2. Through the pre-discharge driving module 2, current diversion is achieved.

[0052] Specifically, the pre-discharge driving module 2 comprises a first control unit 21 and a first switch unit 22. The input end of the first control unit 21 is connected to the discharge MOS control terminal DSG. The control end of the first switch unit 22 is connected to the output end of the first control unit 21, and the input end of the first switch unit 22 is connected to the output negative terminal DS-.

[0053] The first control unit 21 comprises a resistor R6, an NAND gate U1A and an NAND gate U1B. One end of the resistor R6 is connected to the discharge MOS control terminal DSG. The input end of the NAND gate U1A is connected to the resistor R6. The input end of the NAND gate U1B is connected to the output end of the NAND gate U1A, and the output end of the NAND gate U1B is connected to the first switch unit 22.

[0054] The first switch unit 22 comprises a resistor R34, a transistor Q4 and a resistor R36. One end of the resistor R34 is connected to the output end of the first control unit 21. The control end of the transistor Q4 is connected to the resistor R34, and the output end of the transistor Q4 is connected between the output negative terminal DS- and the battery negative terminal B-. The resistor R36 is connected in series with the transistor Q4.

[0055] The pre-discharge driving module 2 in the embodiment adopts the NAND gate U1A and the NAND gate U1B in series to jointly control the conduction or cutoff of the transistor Q4. When the discharge MOS control terminal DSG outputs a high level, the NAND gate U1A and the NAND gate U1B in the pre-discharge driving module 2 will first act to turn on the transistor Q4, so that the battery pack and the load form a current limiting loop in series with the resistor R36.

[0056] The discharge MOS delay driving module 3 is connected between the output negative terminal DS- and the battery negative terminal B-, and is connected to the discharge MOS control terminal DSG for control, which is used to control the conduction or cutoff of the discharge MOS delay driving module 3 between the output negative terminal DS- and the battery negative terminal B-.

[0057] Specifically, the discharge MOS delay driving module 3 comprises a delay unit 31, a second control unit 32 and a second switch unit 33. One end of the delay unit 31 is connected with the discharge MOS control end DSG; the input end of the second control unit 32 is connected with the other end of the delay unit 31; the control end of the second switch unit 33 is connected with the output end of the second control unit 32, the input end of the second switch unit 33 is connected with the negative end DS- of the output port, and the output end of the second switch unit 33 is connected with the negative end B- of the battery.

[0058] The delay unit 31 comprises a capacitor C5, a capacitor C6 and a resistor R40. One end of the capacitor C5 is connected with the input end of the second control unit 32, and the other end of the capacitor C5 is grounded; the capacitor C6 is connected in parallel with the capacitor C5; the resistor R40 is connected in series with the capacitor C5, and the resistor R40 is connected with the discharge MOS control end DSG and the input end of the second control unit 32. The delay unit 31 is composed of the capacitor C5, the capacitor C6 and the resistor R40, the delay time is 1 second, and the specific setting time can be flexibly set.

[0059] The second control unit 32 comprises a NAND gate U1C and a NAND gate U1D connected in series, the input end of the NAND gate U1C is connected with the delay unit 31, the output end of the NAND gate U1C is connected with the input end of the NAND gate U1D, and the output end of the NAND gate U1D is connected with the second switch unit 33.

[0060] The second switch unit 33 comprises transistors M5 and M6 connected in parallel, and the control ends of the transistors M5 and M6 are connected with the output end of the NAND gate U1D. In this way, the NAND gate U1C and the NAND gate U1D jointly control the conduction or cut-off of the transistors M5 and M6.

[0061] In the discharge MOS delay driving module 3 in the embodiment, the NAND gate U1C and the NAND gate U1D act to open the transistors M5 and M6 to discharge only after the discharge MOS control end DSG outputs a high level for about 1S, and the transistors M5 and M6 are closed when the discharge MOS control end DSG outputs a low level, and the logic is the same as above when outputting high again. The transistors M5 and M6 are opened to form an infinite current discharge circuit after the large-capacitance capacitor is pre-charged with a small current for 1S before starting, so as to prevent the problems of equipment failure caused by large current impact, shortening of battery life and the like, provide protection for the equipment, and the overall design is simple, and the function of soft starting of large-capacitance load is realized with extremely low cost.

[0062] In the structure, the pre-discharge driving module 2 and the discharge MOS delay driving module 3 are combined, and the two modules are controlled through the discharge MOS control end DSG; when the discharge MOS control end DSG outputs a high level, the NAND gate U1A and the NAND gate U1B in the pre-discharge driving module 2 act to turn on the transistor Q4 first, so that the battery pack and the load form a current-limiting loop in series with the resistor R36, current diversion is realized, and the current is indirectly reduced; then, through the discharge MOS delay driving module 3, the NAND gate U1C and the NAND gate U1D act to turn on the transistor M5 and the transistor M6, and because the capacitor C5, the capacitor C6 and the resistor R40 cooperate to delay for 1 second, the pre-discharge 1S small-current precharge of the large capacitor is started first before starting, and then the current-limiting discharge loop of the transistor M5 and the transistor M6 is started, the device failure caused by the large-current impact is avoided, the anti-interference ability is high, the protection of the device is effectively improved, the service life of the battery is prolonged, the overall design is simple, the operation performance is stable, the reliability is high, and the cost is low.

[0063] Embodiment 2

[0064] The difference between this embodiment and embodiment 1 is that, as shown in Figures 3-4 The power module of this embodiment includes a voltage reduction unit 11, the voltage reduction unit 11 includes a triode Q6 and a tetrode Q7, the collector of the triode Q6 and the base of the triode Q6 are connected with the output negative end DS-, the emitter of the triode Q6 is connected with the base of the tetrode Q7, the collector of the tetrode Q7 is connected with the output negative end DS-, and the emitter of the tetrode Q7 is connected with a voltage source V11.

[0065] The power module in this embodiment forms a voltage amplification voltage reduction circuit through the triode Q6 and the tetrode Q7, can stably output a 11V-11.3V small-power constant voltage source, and further improves the driving ability of the circuit.

[0066] Embodiment 3

[0067] This embodiment is based on the above-mentioned embodiments, and as shown in Figure 5 A capacitive load device 300 is provided, which includes a control module 200 provided with a soft start hardware circuit 100; wherein the soft start hardware circuit 100 adopts the above-mentioned soft start hardware circuit 100.

[0068] The capacitive load device 300 in this embodiment adopts the above-mentioned soft start hardware circuit 100, and the overall circuit design is simple, so that the soft start function of the battery end hardware protection board is realized under the condition of almost no increase in cost, the capacitive load device 300 has strong working stability and good running reliability.

[0069] In the present application, unless specifically defined otherwise, the terms "mounting", "connected", "connecting", "fixed", and "fixedly" should be understood broadly, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0070] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the product of the application is used, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0071] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0072] In the present application, unless specifically defined otherwise, the first feature above or below the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature above, above and above the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The first feature below, below and below the second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0073] Although the description of the present application is made in combination with the above specific embodiments, it is obvious that those skilled in the art can make many substitutions, modifications and changes according to the above content. Therefore, all such alternatives, improvements and changes are included in the spirit and scope of the appended claims.

Claims

1. A soft start hardware circuit, characterized by, The application relates to a power module, which comprises an output negative terminal, a battery negative terminal and a discharge MOS control terminal. The power module further comprises a pre-discharge driving module, one end of which is connected with the output negative terminal, and the other end of which is connected with the discharge MOS control terminal, the discharge MOS control terminal being used for controlling the on or off of the pre-discharge driving module; and a discharge MOS delay driving module, which is connected between the output negative terminal and the battery negative terminal and is controlled by the discharge MOS control terminal, and is used for controlling the on or off of the discharge MOS delay driving module between the output negative terminal and the battery negative terminal. The pre-discharge driving module comprises a first control unit, the input end of which is connected with the discharge MOS control terminal, and a first switch unit, the control end of which is connected with the output end of the first control unit, and the input end of which is connected with the output negative terminal. The first control unit comprises a resistor R6, the one end of which is connected with the discharge MOS control terminal, a NAND gate U1A, the input end of which is connected with the resistor R6, and a NAND gate U1B, the input end of which is connected with the output end of the NAND gate U1A, and the output end of which is connected with the first switch unit.

2. The soft start hardware circuit of claim 1, wherein, The first switch unit comprises a resistor R34, the one end of which is connected with the output end of the first control unit, a transistor Q4, the control end of which is connected with the resistor R34, and the output end of which is connected between the output negative terminal and the battery negative terminal, and a resistor R36, which is connected in series with the transistor Q4. The discharge MOS delay driving module comprises a delay unit, one end of which is connected with the discharge MOS control terminal, a second control unit, the input end of which is connected with the other end of the delay unit, and a second switch unit, the control end of which is connected with the output end of the second control unit, the input end of which is connected with the output negative terminal, and the output end of which is connected with the battery negative terminal. The delay unit comprises a capacitor C5, one end of which is connected with the input end of the second control unit, and the other end of which is connected with the ground, a capacitor C6, which is connected in parallel with the capacitor C5, and a resistor R40, which is connected in series with the capacitor C5, and is connected with the discharge MOS control terminal and the input end of the second control unit.

3. The soft start hardware circuit of claim 2, wherein, The second control unit comprises a NAND gate U1C and a NAND gate U1D connected in series, the input end of the NAND gate U1C being connected with the delay unit, the output end of the NAND gate U1C being connected with the input end of the NAND gate U1D, and the output end of the NAND gate U1D being connected with the second switch unit. The second switch unit comprises a transistor M5 and a transistor M6 connected in parallel, the control ends of the transistor M5 and the transistor M6 being connected with the output end of the NAND gate U1D. The power module comprises a voltage reduction unit, which comprises a transistor Q6 and a triode Q7. ​ 4. The soft start hardware circuit of claim 2, wherein, ​ ​ ​ ​ 5. The soft start hardware circuit of claim 1, wherein, ​ ​ ​ ​ 6. The soft start hardware circuit of claim 5, wherein, ​ ​ ​ ​ 7. The soft start hardware circuit of claim 5, wherein, ​ 8. The soft start hardware circuit of claim 7, wherein, ​ 9. The soft start hardware circuit of claim 1, wherein, ​ The collector of the triode Q6, the base of the triode Q6 are connected with the output negative terminal, the emitter of the triode Q6 is connected with the base of the triode Q7, the collector of the triode Q7 is connected with the output negative terminal, and the emitter of the triode Q7 is connected with the voltage source V11.

10. A capacitive load device, characterized by The control module is provided with a soft start hardware circuit; wherein the soft start hardware circuit adopts the soft start hardware circuit in any one of claims 1-9.

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