SiC MOSFET device capable of reducing gate-drain capacitance

Abstract

The utility model discloses a SiC MOSFET device capable of reducing gate-drain capacitance, and relates to the technical field of semiconductors. Comprising an N + substrate layer, an N-epitaxial layer, a P-body region, an ohmic contact alloy layer and a front electrode metal layer which are sequentially arranged from bottom to top, the top surface of the P-body region is provided with a gate trench region which extends downwards and is of an inverted trapezoidal structure; a gate oxide layer of which the thickness is gradually increased from top to bottom is arranged in the gate trench region; a Poly layer with an inverted trapezoidal structure is arranged in the gate oxide layer; according to the utility model, the gate trench with the inverted trapezoidal structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the purpose of reducing the gate-drain capacitance is achieved, the Miller plateau time is reduced, and the switching loss of the device is improved. In addition, the thicker gate oxide layer is designed at the bottom of the gate trench, the thickness value of the thicker gate oxide layer is 60-70nm, the purpose of further reducing the gate-drain capacitance is achieved, and meanwhile, the deposited thick gate oxide layer 7 can relieve the risk that the gate oxide is broken down by a voltage peak.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a kind of SiC MOSFET devices of reducing gate leakage capacitance. BACKGROUND

[0002] SiC is an advanced semiconductor material, with many traditional silicon material incomparable advantages. First, the band gap of SiC is larger than silicon, which means it has higher efficiency and lower loss in conductivity. Secondly, the thermal conductivity of SiC is higher than Si, which makes it can work stably at higher temperature. In addition, the electron mobility of SiC is also superior to Si, which makes it perform well in high-frequency applications. In addition, SiC also has good chemical stability and wear resistance.

[0003] In the field of power devices, the total loss is the core indicator to evaluate performance, which includes conduction loss and switching loss. Conduction loss is mainly related to the characteristics of the device itself and working conditions, while switching loss is affected by more factors. The main factors affecting the total switching loss of the device are the turn-on energy Eon, the turn-off energy Eoff and the reverse recovery energy Erec. The proportion of these factors usually depends on the characteristics of the device, operating conditions and external circuit. In addition, other losses may occur during switching, such as losses caused by parasitic conduction. Therefore, how to improve the switching loss of SiC MOSFET device is a technical problem that technicians in the field need to solve. SUMMARY

[0004] To solve the above problems, a SiC MOSFET device for reducing gate leakage capacitance and reducing Miller platform time is provided.

[0005] The technical solution of the utility model is:

[0006] A SiC MOSFET device for reducing gate leakage capacitance, comprising N+ substrate layer, N- epitaxial layer, P-body region, ohmic contact alloy layer and front electrode metal layer arranged from bottom to top.

[0007] The top surface of the P-body region is provided with a gate trench area of inverted trapezoidal structure extending downward; the gate trench area is provided with a gate oxide layer with increasing thickness from top to bottom; the gate oxide layer is provided with a Poly layer of inverted trapezoidal structure.

[0008] The top surface of the P-body region is provided with an N+ region extending downward and connected with the gate oxide layer; the width of the N+ region increases from top to bottom, and the bottom surface of the P-body region is provided with a spacing.

[0009] The top surface of the P-body region is provided with a P+ region formed by downward extending implantation; the side surface where the P+ region connects with the N+ region is a bevel surface;

[0010] The top surface of the N+ region, the gate oxide layer and the Poly layer is provided with an isolation medium layer, and the isolation medium layer is connected with the ohmic contact alloy layer.

[0011] Specifically, the bottom surface of the front electrode metal layer is connected with the isolation medium layer and the ohmic contact alloy layer respectively.

[0012] Specifically, the bottom surface of the front electrode metal layer is connected with the isolation medium layer and the ohmic contact alloy layer respectively.

[0013] Specifically, the depth of the P-body region is 0.8-1.5 um.

[0014] Specifically, the depth of the N+ region is 0.4-0.8 um.

[0015] Specifically, the depth of the P+ region is 0.4-0.8 um.

[0016] The gate trench with the inverted trapezoidal structure reduces the overlapping area of the gate and the drain, thereby reducing the gate-drain capacitance, reducing the Miller platform time and improving the switching loss of the device. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a structural schematic diagram of preparing an N-epitaxial layer;

[0018] Figure 2 is a structural schematic diagram of preparing a P-body region;

[0019] Figure 3 is a structural schematic diagram of preparing a gate trench region;

[0020] Figure 4 is a structural schematic diagram of preparing an N+ region;

[0021] Figure 5 is a structural schematic diagram of preparing a P+ region;

[0022] Figure 6 is a structural schematic diagram of preparing a gate oxide layer;

[0023] Figure 7 is a structural schematic diagram of preparing a Poly layer;

[0024] Figure 8is a structural schematic diagram of preparing the isolation medium layer;

[0025] Figure 9 is a structural schematic diagram of preparing the ohmic contact alloy layer;

[0026] Figure 10 is a structural schematic diagram of preparing the front electrode metal layer;

[0027] In the figure, 1 is an N+ substrate layer, 2 is an N- epitaxial layer, 3 is a P-body region, 4 is a gate trench region, 5 is an N+ region, 6 is a P+ region, 7 is a gate oxide layer, 8 is a Poly layer, 9 is an isolation medium layer, 10 is an ohmic contact alloy layer, and 11 is a front electrode metal layer. DETAILED DESCRIPTION

[0028] The utility model will be explained in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the illustrative embodiments of the utility model and the description thereof are only used for explaining the utility model and do not limit the utility model.

[0029] A SiC MOSFET device for reducing gate leakage capacitance comprises the following steps:

[0030] S100, as shown in the figure, growing an N- epitaxial layer 2 above the N+ substrate layer 1, and ion implanting Al ions on the top of the N- epitaxial layer to form a P-body region 3, the concentration of the P-body region 3 ranges from 1E 17 cm -2 -1E 18 cm -2 , and the implantation depth is 0.8-1.5um, as shown in the figure; Figure 2

[0031] S200, as shown in the figure, etching a gate trench region 4 in the form of an inverted trapezoid from the top surface of the P-body region 3 downwards, and the etching depth is 1.8-2um (the etching depth refers to the distance from the top surface of the P-body region 3 to the bottom of the gate trench region 4), and the inclination angle of the inverted trapezoid is adjusted according to the actual process;

[0032] S300, as shown in the figure, implanting N ions in the P-body region 3 of the gate trench region 4 multiple times with photoresist and SiO2 as masks, forming an N+ region 5, and the concentration ranges from 1E 18 cm -2 -1E 19 cm -2 , and the implantation depth is 0.4-0.8um;

[0033] S400, as shown in the figure, implanting P ions in the N+ region 5 multiple times with photoresist and SiO2 as masks, forming a P+ region 6, and the concentration ranges from 1E 18 cm -2 -1E 19 cm -2 , and the implantation depth is 0.4-0.8um;As shown, using photoresist and SiO2 as masks, Al ions are implanted multiple times on the top surface of P-body region 3 to form P+ region 6 connected to N+ region 5.

[0034] The concentration range of P+ region 6 is 1E. 18 cm -2 -1E 19 cm -2 The implantation depth is 0.4-0.8 μm. After implantation, the mask is removed. Then, a thin graphite layer is deposited on the device surface as a protection and annealed at a high temperature of 1650℃-1690℃ for 15 min to activate the implanted ions.

[0035] S500, such as Figure 6 As shown, a gate oxide layer 7 is grown on the sidewalls and bottom of the gate trench region 4 using a dry oxygen thermal oxidation method with photoresist as a mask. The layer is then annealed in a NO atmosphere at a temperature of 1250°C for 1 hour to improve the density of the gate oxide layer and reduce defects.

[0036] In step S500, the thickness of the gate oxide layer 7 increases with the increase of the gate trench depth. This reduces the gate-drain capacitance without affecting the formation of the channel. The gate oxide layer at the bottom of the gate trench 4 is the thickest, with a thickness of 60-70 nm, while the gate oxide layer at the top of the N-epitaxial layer 2 is the thinnest, with a thickness of 25-40 nm.

[0037] In step S500, the photoresist is formed by the diffraction effect of light passing through a photoresist plate with a slit, causing the light passing through the slit area to diffract outward. After the photolithography and development process, the edge of the photoresist forms a gently sloping region.

[0038] S600, such as Figure 7 As shown, polysilicon is deposited in the gate trench region 4 using LPCVD to form a poly layer 8, which is then used as the gate electrode.

[0039] S700, such as Figure 8 As shown, an isolation dielectric layer 9 is formed by depositing oxide on top of the N-epitaxial layer;

[0040] In step S700, the two ends of the isolation medium layer 9 are respectively placed on the upper end of the N+ region 5, and the overlap distance is not limited. The bottom is in contact with the top of the N- epitaxial layer 2.

[0041] S800, such as Figure 9 As shown, an ohmic metal layer is formed on the N-epitaxial layer 2 by Ni metal sputtering deposition, and then annealed at a high temperature of 1000°C for 5 min to form an ohmic contact alloy layer 10, which forms an ohmic contact with the N+ region 5 and the P+ region 6 above.

[0042] The ohmic contact alloy layer 14 in step S800 is arranged on both sides of the isolation medium layer 9 and in contact with the side wall of the isolation medium layer 9 respectively.

[0043] S900, as shown in the isolation medium layer 9 and the ohmic contact alloy layer 10 above the way of sputtering metal Al deposition front electrode metal layer 11, as the source electrode lead-out. Figure 10

[0044] A kind of SiC MOSFET device for reducing gate leakage capacitance, including N+ substrate layer 1, N- epitaxial layer 2, P-body region 3, ohmic contact alloy layer 10 and front electrode metal layer 11 are sequentially arranged from bottom to top;

[0045] The top surface of the P-body region 3 is provided with a gate trench region 4 of inverted trapezoidal structure extending downward;The gate trench region 4 is provided with a gate oxide layer 7 with increasing thickness from top to bottom;The gate oxide layer 7 is provided with a Poly layer 8 of inverted trapezoidal structure;

[0046] The top surface of the P-body region 3 is provided with an N+ region 5 extending downward and connected with the gate oxide layer 7;The width of the N+ region 5 increases from top to bottom, and the bottom surface of the P-body region 3 is provided with a spacing;

[0047] The top surface of the P-body region 3 is provided with a P+ region 6 extending downward and connected with the gate oxide layer 7;The side surface of the P+ region 6 connected with the N+ region 5 is a slope;

[0048] The top surface of the N+ region 5, the gate oxide layer 7 and the Poly layer 8 is provided with an isolation medium layer 9, and the isolation medium layer 9 is connected with the ohmic contact alloy layer 10.

[0049] The bottom surface of the front electrode metal layer 11 is connected with the isolation medium layer 9 and the ohmic contact alloy layer 10 respectively.

[0050] The utility model discloses a gate trench 4 of inverted trapezoidal structure, reduces the overlapping area of gate and drain, thereby reaches the purpose of reducing gate leakage capacitance, reduces miller platform time, improves the switching loss of device.In addition, the utility model discloses a relatively thick gate oxide layer 7 designed at the gate trench bottom, and the thickness value is 60-70nm, which further reduces the purpose of reducing gate leakage capacitance, and the deposited thick gate oxide layer 7 can alleviate the risk of gate oxide breakdown by voltage spike.

[0051] For the content disclosed in the case, the following points need to be explained:

[0052] (1), the embodiment disclosed in the case only involves the structure involved in the embodiment disclosed in the case, and other structures can be referred to as usual;

[0053] ​(2) In the case of no conflict, the embodiments disclosed in the present case and the features in the embodiments can be combined with each other to obtain new embodiments;

[0054] The above is only a specific embodiment disclosed in the present case, but the protection scope of the present disclosure is not limited thereto, and the protection scope disclosed in the present case is subject to the protection scope of the claims.

Claims

1. A SiC MOSFET device with reduced gate-drain capacitance, characterized by, It comprises N+ substrate layer (1), N- epitaxial layer (2), P-body region (3), ohmic contact alloy layer (10) and front electrode metal layer (11) arranged in turn from bottom to top; The top surface of the P-body region (3) is provided with gate trench region (4) of inverted trapezoidal structure extending downward; the gate trench region (4) is provided with gate oxide layer (7) with thickness increasing from top to bottom; the gate oxide layer (7) is provided with Poly layer (8) of inverted trapezoidal structure; The top surface of the P-body region (3) is provided with N+ region (5) extending downward and connected with the gate oxide layer (7); The top surface of the P-body region (3) is provided with P+ region (6) extending downward; The top surface of the N+ region (5), gate oxide layer (7) and Poly layer (8) is provided with isolation dielectric layer (9) connected with the ohmic contact alloy layer (10).

2. The SiC MOSFET device of claim 1, wherein, The bottom surface of the front electrode metal layer (11) is connected with the isolation dielectric layer (9) and the ohmic contact alloy layer (10) respectively.

3. The SiC MOSFET device of claim 1, wherein, The depth of the P-body region (3) is 0.8-1.5 um.

4. The SiC MOSFET device of claim 1, wherein, The depth of the N+ region (5) is 0.4-0.8 um.

5. The SiC MOSFET device of claim 1, wherein, The depth of the P+ region (6) is 0.4-0.8 um.

Images