Lead frame and power device structure

Abstract

The utility model discloses a lead frame and a power device structure, the lead frame comprises a plurality of sub-frames in array connection, each sub-frame comprises a first power pin connection area, a second power pin connection area and a power chip installation area, the first power pin connecting area and the second power pin connecting area are both arranged at the first end of the power chip mounting area, and the first power pin connecting area, the second power pin connecting area and the power chip mounting area are all connected to the frame of the sub-frame through connecting ribs; the power chip installation area is used for installing a power chip. According to the utility model, each sub-frame of the lead frame is provided with the power chip installation area used for installing the power chip, and the first power pin connection area, the second power pin connection area and the power chip installation area are arranged at certain intervals, so that the transient creepage distance of the power device structure manufactured by using the lead frame can be enhanced; and the safety and the service life of the power device structure are improved.

Description

Technical Field

[0001] This utility model relates to the field of power device technology, and in particular to a lead frame and power device structure. Background Technology

[0002] In high-voltage, high-frequency pulse applications (such as photovoltaic panels and new energy motor drives), energy conversion (power inversion) is mainly achieved by combining modular high-power device packaging structures (such as HPD, HPI, 62mm, etc.) or discrete low-power packaged devices (such as TO single transistors, PDFN, QFN, etc.) for functional applications. To ensure the stability of end applications, traditional power devices are typically optimized in various ways for end applications with high voltage platforms above 3.3kV. For example, the power chip packaged in the power device is replaced with a more voltage-resistant SiC chip or GaN chip, or multiple low-voltage silicon-based power devices are modularly packaged according to a certain electrical structure, or packaged TO single transistors, PDFN, QFN, etc., are combined according to a certain electrical structure. However, all of the above methods require high costs, and the use of device combinations also results in larger PCB board size for end applications, increased difficulty in controlling stray inductance, and stronger electromagnetic EMC, leading to a significant reduction in the performance and lifespan of the devices in end applications and poor reliability.

[0003] Furthermore, due to the characteristics of IGBT power chips, devices packaged in IGBT TO single-transistor, PDFN, and QFN packages often require a one-to-one matching freewheeling protection diode to ensure the IGBT power chip is not damaged during switching and to guarantee its safety. Therefore, in actual design, the safety of the IGBT power chip needs to be considered. That is, the performance of the IGBT during operation is affected by the design width of the frame supporting the IGBT power chip, the distance between the two power chips (IGBT and FRD), and the packaging material. For example, too wide a distance will result in an excessively large product, which is not conducive to terminal layout and application; too small a distance will lead to a large inductance between the IGBT power chip and the FRD freewheeling diode, reducing device reliability; in modular packaging applications of high-power, high-voltage, and high-pulse platforms, electrical stress and mechanical stress generated by the epoxy resin packaging material can easily cause the internal electrical connection wires (bonding wires) of the power module device to detach or break, reducing the device's performance life and reliability.

[0004] In the process of developing this utility model, the applicant discovered at least the following problems in the prior art:

[0005] Existing power devices have low performance and lifespan, low reliability, and high cost when used in high voltage and high frequency applications. Utility Model Content

[0006] The purpose of this invention is to provide a lead frame and power device structure to solve the technical problems of low performance and service life of existing power devices in high-voltage and high-frequency applications. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] This utility model provides a lead frame comprising multiple array-connected sub-frames. Each sub-frame includes a first power pin connection area, a second power pin connection area, and a power chip mounting area. The first power pin connection area and the second power pin connection area are both disposed at a first end of the power chip mounting area. The first power pin connection area, the second power pin connection area, and the power chip mounting area are all connected to the edge of the sub-frame via connecting ribs. The power chip mounting area is used to mount power chips.

[0009] Optionally, the first power pin connection area, the second power pin connection area and the power chip mounting area have a first spacing, the first spacing being in the range of 4mm to 6mm.

[0010] Optionally, there is a second spacing between the first power pin connection area and the second power pin connection area, the second spacing being in the range of 5mm to 8mm.

[0011] Optionally, the four opposite corners of the power chip mounting area are provided with rounded chamfers, and the radius of the rounded chamfers ranges from 0.1mm to 1mm.

[0012] A power device structure includes a lead frame as described above, and further includes a power chip, an electrical connector, and an encapsulating colloid. A first electrode of the power chip is disposed on a power chip mounting area of ​​a subframe of the lead frame. A second electrode of the power chip is electrically connected to a first power pin connection area via the electrical connector. A third electrode of the power chip is electrically connected to a second power pin connection area via the electrical connector. The encapsulating colloid is used to encapsulate the first power pin connection area, the second power pin connection area, and the power chip mounting area of ​​the subframe, as well as the power chip and the electrical connector mounted on the subframe.

[0013] Optionally, it also includes an auxiliary slot, which is disposed on the back side of the power device structure and located between the power chip mounting area and the first power pin connection area and the second power pin connection area.

[0014] Optionally, the width of the auxiliary groove is in the range of 1mm to 3mm; the depth of the auxiliary groove is in the range of 1mm to 4mm, and the depth of the auxiliary groove is lower than the curvature of the electrical connector perpendicular to the location of the auxiliary groove; the length of the auxiliary groove is in the range of 3 / 4 to 1 / 4 of the width of the power device structure.

[0015] Optionally, the power chip is any one of IGBT, MOSFET, SiC power chip, and GaN power chip.

[0016] Optionally, the encapsulating colloid is made of insulating colloid, and the electrical connector is a bonding wire or a bonding metal strip.

[0017] Optionally, the first electrode of the power chip is disposed on the power chip mounting area of ​​the subframe of the lead frame by solder.

[0018] Implementing one of the above-described technical solutions of this utility model has the following advantages or beneficial effects:

[0019] This invention provides a power chip mounting area on each sub-frame of the lead frame for mounting power chips, and there is a certain distance between the first power pin connection area, the second power pin connection area and the power chip mounting area, which can enhance the transient creepage distance of the power device structure made by the lead frame, and improve the safety and service life of the power device structure.

[0020] Meanwhile, auxiliary slots are set on the fabricated power device structure to further enhance the transient creepage distance, and insulating materials such as silicone are used for encapsulation, resulting in low cost and small device size. Compared with traditional discrete TO single tube, PDFN, QFN and other packaged devices, it saves a lot of costs. Moreover, the power structure provided by this solution has the advantages of simple structure, low field strength, low stray emissions, low EMI, high safety, high reliability and strong compatibility. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0022] Figure 1 This is a first structural schematic diagram of an embodiment of the lead frame of this utility model;

[0023] Figure 2 This is a second structural schematic diagram of an embodiment of the lead frame of this utility model;

[0024] Figure 3 This is a schematic diagram of the subframe structure of an embodiment of the lead frame of this utility model;

[0025] Figure 4 This is a first schematic diagram of the power chip setup and wire bonding in an embodiment of the power device structure of this utility model;

[0026] Figure 5 This is a second schematic diagram of the power chip setup and wire bonding in an embodiment of the power device structure of this utility model;

[0027] Figure 6 This is a schematic diagram of the packaging ribs of an embodiment of the power device structure of this utility model;

[0028] Figure 7 This is a perspective view of an embodiment of the power device structure of this utility model;

[0029] Figure 8 This is a cross-sectional view of an embodiment of the power device structure of this utility model.

[0030] In the diagram: 1. Subframe; 11. First power pin connection area; 12. Second power pin connection area; 13. Power chip mounting area; 14. Rounded chamfer; 15. Connecting rib; 16. Frame; 2. Power chip; 3. Electrical connector; 4. Encapsulating colloid; 5. Auxiliary groove. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this utility model clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be adopted to implement this utility model. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this utility model disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this utility model.

[0032] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0033] To illustrate the technical solution described in this utility model, specific embodiments are described below, showing only the parts related to the embodiments of this utility model.

[0034] Example 1:

[0035] like Figure 1 and Figure 2 As shown, this utility model provides a lead frame including multiple arrayed sub-frames 1. Each sub-frame 1 includes a first power pin connection area 11, a second power pin connection area 12, and a power chip mounting area 13. The first power pin connection area 11 and the second power pin connection area 12 are both located at the first end of the power chip mounting area 13. The first power pin connection area 11, the second power pin connection area 12, and the power chip mounting area 13 are all connected to the frame 16 of the sub-frame 1 via connecting ribs 15. The power chip mounting area 13 is used to mount power chips 2.

[0036] Specifically, the lead frame consists of multiple sub-frames 1 arranged in an array, the number of which is adaptively set according to the production volume requirements. Each sub-frame 1 includes a power chip mounting area 13 for mounting and fixing the power chip 2, and also includes a first power pin connection area 11 and a second power pin connection area 12 for completing the electrical connection of the power chip 2. The power chip mounting area 13 is matched with the power chip 2. The first power pin connection area 11 and the second power pin connection area 12 are both located at the first end of the power chip mounting area 13, so that the second terminal of the power chip 2 fixed on the power chip mounting area 13 can be connected to the first power pin connection area 11, and the third terminal can be connected to the second power pin connection area 12.

[0037] More specifically, the lead frame material in this embodiment is, but is not limited to, copper, aluminum, aluminum alloy, copper-aluminum alloy, and other materials with good electrical properties and excellent ductility. The lead frame material in this embodiment is preferably a copper or aluminum frame with lower cost.

[0038] This invention provides a power chip mounting area 13 on each sub-frame 1 of the lead frame for mounting a power chip 2, and there is a certain distance between the first power pin connection area 11, the second power pin connection area 12 and the power chip mounting area 13, which can enhance the transient creepage distance of the power device structure made by the lead frame, and improve the safety and service life of the power device structure.

[0039] As an optional implementation, a first spacing exists between the first power pin connection area 11, the second power pin connection area 12, and the power chip mounting area 13, with the first spacing ranging from 4mm to 6mm. Specifically, according to silicon-based safety standards, in high-frequency applications at 3.3kV, the enhanced transient creepage distance corresponds to a value of at least 3.8mm. Therefore, the first spacing of the power device structure is preferably designed to be greater than 3.8mm. In this embodiment, to ensure the safety and reliability of the power device structure, the first spacing of the power device structure of this utility model is further preferably designed to be greater than 4mm. The range of the first spacing is 4mm to 6mm, and the first spacing is preferably 5mm. Figure 3 As shown, the first spacing between the first power pin connection area 11, the second power pin connection area 12 and the power chip mounting area 13 is denoted as D1.

[0040] As an optional implementation, a second spacing is provided between the first power pin connection area 11 and the second power pin connection area 12, the second spacing ranging from 5mm to 8mm. Specifically, according to silicon-based safety standards, under high-frequency applications at 3.3kV, the enhanced transient creepage distance corresponds to a value of at least 3.8mm. Therefore, the second spacing of the power device structure is preferably designed to be greater than 3.8mm, and this invention further preferably sets it to 4mm to further ensure device safety while reducing internal stray interference. The range of the second spacing is 5mm to 8mm, and the second spacing is preferably 6mm. Figure 3 As shown, the first spacing between the first power pin connection area 11, the second power pin connection area 12 and the power chip mounting area 13 is denoted as D2.

[0041] As an optional implementation method, such as Figure 3As shown, the four opposite corners of the power chip mounting area 13 are provided with rounded chamfers 14, and the radius of the rounded chamfers 14 ranges from 0.1mm to 1mm. Specifically, the four opposite corners of the power chip mounting area 13 can be set as rounded chamfers 14. When the power device structure operates on a high-voltage, high-frequency platform above 3.3KV, the rounded chamfers 14 can reduce the charge accumulation at the rounded chamfers 14 of the internal frame of the power device structure and the intensity of the two directions "superimposed" on the four corners of the power chip 2. This avoids the instantaneous excessive charge accumulation that could lead to arc discharge and insulation damage, thereby reducing inductance and internal field strength, and improving the lifespan of the power device structure, the reliability of electrical connections, and the stability of operation. In addition, setting rounded chamfers 14 at the corners of the power chip 2 carrying the electrical connection layer, i.e., the four opposite corners of the power chip mounting area 13, can also reduce the resistance of the circuit and reduce power loss. In the product design process of this embodiment, the size of the rounded chamfers 14 is determined by the actual operating requirements of the power device structure. For applications above 3.3KV, the radius of the rounded chamfers 14 is preferably 0.5mm. For cost considerations, other sizes of chamfers can also be set, and there are no fixed restrictions.

[0042] Example 2:

[0043] like Figure 4 As shown, a power device structure includes a lead frame, a power chip 2, an electrical connector 3, and an encapsulating colloid 4, as described in Embodiment 1. The first electrode of the power chip 2 is disposed on the power chip mounting area 13 of the sub-frame 1 of the lead frame. The second electrode of the power chip 2 is electrically connected to the first power pin connection area 11 via the electrical connector 3. The third electrode of the power chip 2 is electrically connected to the second power pin connection area 12 via the electrical connector 3. The encapsulating colloid 4 is used to encapsulate the first power pin connection area 11, the second power pin connection area 12, and the power chip mounting area 13 of the sub-frame 1, as well as the power chip 2 and the electrical connector 3 mounted on the sub-frame 1.

[0044] Specifically, the first terminals of multiple power chips 2 are respectively disposed in the power chip mounting area 13 of each sub-frame 1. The second terminal of each power chip 2 is connected to the first power pin connection area 11 in the sub-frame 1 by bonding wires 3, and the third terminal of each power chip 2 is connected to the second power pin connection area 12 in the sub-frame 1 by electrical connectors 3, thus completing the electrical connection of the power chips 2. The first power pin connection area 11, the second power pin connection area 12, and the power chip mounting area 13 of each sub-frame 1, as well as the power chips 2 and electrical connectors 3 mounted on each sub-frame 1, are encapsulated by encapsulating colloid 4, resulting in a schematic diagram of the power module encapsulation connection. Figure 6 By cutting away the frame 16 and connecting ribs 15, the multiple power device structures of this embodiment are obtained.

[0045] The length, width, and height of the power device structure can be selected as 30mm*26mm*5mm. The actual specifications are set according to the specific voltage platform. The power device structure provided in this embodiment has a small and thin volume, which saves costs.

[0046] The power device of this invention has a small size, low cost, and advantages such as simple structure, low field strength, low stray emissions, low EMI, high safety, high reliability, and strong compatibility.

[0047] As an optional implementation method, such as Figure 7 and Figure 8 As shown, it also includes an auxiliary groove 5, which is disposed on the back of the power device structure and located between the power chip mounting area 13 and the first power pin connection area 11 and the second power pin connection area 12. Specifically, during the power device structure packaging process, i.e., during the potting process, an auxiliary groove 5 is set on the back of the power device structure by means of the protrusion of the potting fixture, located between the power chip mounting area 13 and the first power pin connection area 11 and the second power pin connection area 12. From the perspective of end application, the power device structure with the auxiliary groove 5 facilitates assembly to the corresponding position on the PCB circuit board, provides strong mechanical connection stability for subsequent power device structure applications, and improves production process efficiency. On the other hand, according to silicon-based safety standards, under high-frequency applications of 3.3KV, the corresponding value after the transient creepage distance enhancement is at least 3.8mm. In order to further improve the safety and reliability of the power device structure, this utility model preferably designs the first and second spacings of the power device structure to be greater than 4mm. However, this only meets the basic electrical performance requirements. The power device structure may break down due to external factors such as heat generation during long-term operation, and the safety performance needs to be further improved. Therefore, by providing an auxiliary slot 5 between the power chip mounting area 13 and the first power pin connection area 11 and the second power pin connection area 12 in the power device structure, the transient creepage distance can be increased, further improving the safety of the power device structure and making it more resistant to breakdown. Furthermore, by providing the auxiliary slot 5 between the power chip mounting area 13 and the first power pin connection area 11 and the second power pin connection area 12 in the power device structure, it is not necessary to widen the spacing between the power chip mounting area 13 and the first power pin connection area 11 and the second power pin connection area 12 to increase the transient creepage distance, thus ensuring that the volume of the power device structure remains unchanged and reducing costs. The cross-section of the auxiliary slot 5 can be an "n" shape, a "v" shape, or a U-shaped structure or a boss structure; the specific slot shape can be set according to the electrical creepage requirements of the power device structure.

[0048] As an optional implementation, the width of the auxiliary groove 5 ranges from 1mm to 3mm, the depth ranges from 1mm to 4mm, and the depth of the auxiliary groove 5 is lower than the curvature of the electrical connector 3 vertically corresponding to the location of the auxiliary groove 5. The length of the auxiliary groove 5 ranges from 3 / 4 to 1mm of the width of the power device structure. Specifically, the length, width, and depth of the auxiliary groove 5 are set according to the actual power scenario. In this utility model, the width of the auxiliary groove 5 is preferably 1mm, the depth is preferably 1mm, and the length is preferably 3 / 4 of the width of the power device structure. Therefore, the creepage distance can be increased from 4mm to 6mm. The depth of the auxiliary groove 5 is lower than the curvature of the electrical connector 3 vertically corresponding to the location of the auxiliary groove 5, which ensures that the electrical connector 3 vertically corresponding to the location of the auxiliary groove 5 will not be damaged when the auxiliary groove 5 is opened, and ensures the normal operation of the power device structure.

[0049] As an optional implementation, the power chip 2 can be any one of IGBT, MOSFET, SiC power chip, and GaN power chip. Specifically, the power device structure can be selected from different power chips 2 according to requirements. The power chip 2 is preferably a silicon-based high-power IGBT power chip. The first electrode of the power chip 2 corresponds to the IGBT collector, the second electrode of the power chip 2 corresponds to the IGBT gate, and the third electrode of the power chip 2 corresponds to the IGBT emitter.

[0050] As an optional implementation method, such as Figure 4 and Figure 5 As shown, the encapsulating colloid 4 is made of insulating colloid. The electrical connector 3 is a bonding wire or a bonding metal strip. Specifically, the insulating colloid used to encapsulate the power device structure is preferably a hardened silicone gel. The hardened silicone gel, with a dielectric strength greater than 25 KV / mm, has a hardness of 47 Shore A after curing, effectively protecting the power chip 2 inside the power device structure. Under the condition of a hardness of 47 Shore A, the encapsulating colloid 4 possesses corresponding flexibility and, under the condition that the material can withstand mechanical stress, has corresponding buffering capacity, preventing breakage or detachment failure of the power chip 2 and connecting circuits inside the power device structure, and has strong resistance to mechanical stress. Alternatively, the insulating colloid can also be made of traditional epoxy resin, which is suitable for low-power platforms and offers stable performance. The electrical connector 3 can be a bonding wire or a bonding metal strip. When the electrical connector 3 is a bonding wire, the bonding wire is a metal wire with good electrical properties, such as copper or aluminum wire; when the electrical connector 3 is a bonding metal strip, the bonding metal strip is a metal strip with good ductility, such as copper or aluminum strip. The power chip 2 is connected to the first power pin connection area 11 and the second power pin connection area 12 via a bonding metal strip, which enables the power module to dissipate heat not only through the power chip mounting area 13, but also through the bonding metal strip, further enhancing the heat dissipation capability of the power device structure and the reliability of operation on a high-voltage platform.

[0051] As an optional implementation method, such as Figure 4 and Figure 5 As shown, the first electrode of the power chip 2 is set on the power chip mounting area 13 of the subframe 1 of the lead frame by solder. Specifically, the first electrode of the power chip 2 is vacuum welded into the power chip mounting area 13 of each subframe 1 by solder or solder pads, solder paste, solder wire, and other welding materials to achieve stable fixation of the power chip 2.

[0052] The above description is merely a preferred embodiment of the present utility model. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present utility model. Furthermore, under the teachings of the present utility model, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present utility model. Therefore, the present utility model is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present utility model.

Claims

1. A lead frame, characterized in that, The subframe (1) includes multiple array-connected subframes. Each subframe (1) includes a first power pin connection area (11), a second power pin connection area (12), and a power chip mounting area (13). The first power pin connection area (11) and the second power pin connection area (12) are both located at the first end of the power chip mounting area (13). The first power pin connection area (11), the second power pin connection area (12), and the power chip mounting area (13) are all connected to the frame (16) of the subframe (1) by connecting ribs (15). The power chip mounting area (13) is used to mount power chips (2).

2. The lead frame according to claim 1, characterized in that, The first power pin connection area (11), the second power pin connection area (12) and the power chip mounting area (13) have a first spacing, which is 4mm to 6mm.

3. The lead frame according to claim 1, characterized in that, There is a second gap between the first power pin connection area (11) and the second power pin connection area (12), and the second gap ranges from 5mm to 8mm.

4. The lead frame according to any one of claims 1-3, characterized in that, The power chip mounting area (13) has rounded chamfers (14) at its four opposite corners, and the radius of the rounded chamfers (14) ranges from 0.1 mm to 1 mm.

5. A power device structure comprising the lead frame as described in any one of claims 1-4, characterized in that, It also includes a power chip (2), an electrical connector (3), and an encapsulating colloid (4). The first electrode of the power chip (2) is disposed on the power chip mounting area (13) of the subframe (1) of the lead frame. The second electrode of the power chip (2) is electrically connected to the first power pin connection area (11) through the electrical connector (3). The third electrode of the power chip (2) is electrically connected to the second power pin connection area (12) through the electrical connector (3). The encapsulating colloid (4) is used to encapsulate the first power pin connection area (11), the second power pin connection area (12), and the power chip mounting area (13) of the subframe (1), as well as the power chip (2) and the electrical connector (3) mounted on the subframe (1).

6. The power device structure according to claim 5, characterized in that, It also includes an auxiliary slot (5), which is disposed on the back side of the power device structure and located between the power chip mounting area (13) and the first power pin connection area (11) and the second power pin connection area (12).

7. The power device structure according to claim 6, characterized in that, The width of the auxiliary groove (5) is 1mm to 3mm; the depth of the auxiliary groove (5) is 1mm to 4mm, and the depth of the auxiliary groove (5) is lower than the arc of the electrical connector (3) perpendicular to the position of the auxiliary groove (5); the length of the auxiliary groove (5) is 3 / 4 to 1 / 4 of the width of the power device structure.

8. The power device structure according to claim 5, characterized in that, The power chip (2) is any one of IGBT, MOSFET, SiC power chip and GaN power chip.

9. The power device structure according to claim 5, characterized in that, The encapsulating colloid (4) is made of insulating colloid, and the electrical connector (3) is a bonding wire or a bonding metal strip.

10. The power device structure according to claim 5, characterized in that, The first electrode of the power chip (2) is disposed on the power chip mounting area (13) of the subframe (1) of the lead frame by solder.

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