Broadband high-gain radio frequency amplification circuit

Abstract

The broadband high-gain radio frequency amplification circuit comprises a first-stage amplification module, a second-stage amplification module, a third-stage amplification module and a fourth-stage amplification module, the first-stage amplification module comprises a chip U3, an inductor L1, an inductor L2 and a resistor R5, and the second-stage amplification module comprises a chip U1, an inductor L3, a capacitor C5, a capacitor C6 and a capacitor C27. The third-stage amplification module comprises a chip U2, a capacitor C8, a capacitor C9 and an inductor L4, and the fourth-stage amplification module comprises a chip U4, a capacitor C11, a capacitor C12 and an inductor L5. According to the utility model, the frequency coverage is obviously improved, and the test discontinuity caused by frequency band switching in the traditional radio frequency test is avoided.

Description

Technical Field

[0001] This utility model relates to the field of signal processing technology, and in particular to a wideband high-gain radio frequency amplifier circuit. Background Technology

[0002] Radio frequency (RF) preamplifiers are key functional modules in modern communication systems and electronic testing, widely used in signal reception, processing, and testing. In the RF signal chain, the primary function of a preamplifier is to amplify weak RF signals while maintaining a low noise level, thereby improving the system's signal-to-noise ratio (SNR).

[0003] Currently, most RF amplifiers on the market are designed for specific frequency bands or applications. Many high-gain amplifiers can cover the 1GHz-6GHz band, suitable for current mainstream communication bands such as LTE, Wi-Fi 6, and Sub-6 GHz 5G. However, high-gain RF amplifiers with a wider bandwidth (30MHz to 6GHz) are relatively scarce, posing a technical bottleneck for some specialized applications. For example:

[0004] EMI applications in electromagnetic compatibility (EMC) testing:

[0005] EMC testing requires detecting the electromagnetic radiation performance of equipment over a wide frequency band. Traditional testing methods often require multiple frequency amplifiers and RF switches to cover the entire test frequency band. This multi-segment testing approach introduces the following problems:

[0006] Test data discontinuity: Segmented measurements may cause breakpoints between measurement data, affecting the accuracy and consistency of the overall test.

[0007] Increased system complexity: additional RF switches and connectors are required, which may introduce additional signal attenuation and noise.

[0008] Inefficient: The testing process is cumbersome, and data needs to be manually integrated, which increases workload and the possibility of errors.

[0009] The requirements of broadband communication:

[0010] The 30MHz to 6GHz frequency band covers multiple mainstream frequency bands, including wireless communication (such as Wi-Fi 6, Sub-6 GHz 5G), aerospace, radar, and certain industrial communications. In practical applications, wideband amplifiers can reduce design complexity, improve system stability, and reduce uncertainties caused by signal switching. Therefore, there is a broad market demand for a high-gain RF amplifier capable of covering the 30MHz to 6GHz range, but existing technologies face the following challenges in wideband designs:

[0011] Wideband gain flatness: Ensuring stable gain in the range of 30MHz to 6GHz is a technical challenge, especially since gain fluctuations are prone to occur in high-gain amplifiers.

[0012] Low noise characteristics: Wideband design may lead to an increased noise figure, especially in noise-sensitive applications (such as receiver front-end and EMC testing).

[0013] Impedance matching: In broadband designs, achieving efficient impedance matching to optimize power transmission and reduce the reflection coefficient is another key issue. Utility Model Content

[0014] In order to overcome the shortcomings of the prior art, this application proposes a wideband high-gain radio frequency amplifier circuit to solve the problems existing in the prior art.

[0015] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0016] A wideband, high-gain radio frequency amplifier circuit includes a first-stage amplification module, a second-stage amplification module, a third-stage amplification module, and a fourth-stage amplification module. The first-stage amplification module includes a chip U3, inductors L1 and L2, and a resistor R5. The second-stage amplification module includes a chip U1, inductor L3, capacitors C5, C6, and C27. The third-stage amplification module includes a chip U2, capacitors C8 and C9, and an inductor L4. The fourth-stage amplification module includes a chip U4, capacitors C11 and C12, and an inductor L5. Pin 2 of chip U3 is connected to capacitor C3 and inductor L1. The other end of inductor L1 is connected to capacitor C18 and resistor R5. The other end of resistor R5 is connected to capacitors C25, C30, and C35, and a resistor R5. R20, capacitors C46 and C48, and resistor R19. The other end of capacitor C46 is connected to the other end of capacitor C48, the other end of resistor R19, and ground. The other end of resistor R20 is connected to resistor R16 and capacitor C47. The other end of capacitor C47 is grounded. The other end of resistor R16 is connected to resistor R18 and chip U7. The other end of resistor R18 is grounded. Pin 4 of chip U3 is connected to capacitors C17, C22, and C24. The other end of capacitor C17 is connected to the other ends of capacitors C22 and C24. Pin 5 of chip U3 is connected to capacitor C4 and inductor L2. The other end of inductor L2 is connected to capacitor C19 and resistor R6. The other end of resistor R6 is connected to capacitor C26 and capacitor... C31, capacitor C36, resistors R13 and R14; the other end of capacitor C19 is connected to the other ends of capacitors C26, C31, and C36, and ground; the other end of capacitor C4 is connected to capacitor C5; the other end of capacitor C5 is connected to pin 1 of chip U1; pin 2 of chip U1 is grounded; pin 3 of chip U1 is connected to capacitor C6 and inductor L3; the other end of inductor L3 is connected to capacitors C20, C27, and C32, resistors R7 and R8; the other end of capacitor C20 is grounded; the other end of capacitor C27 is connected to the other end of capacitor C32 and ground; the other end of capacitor C6 is connected to capacitors C7 and C16, and resistor R2; the other end of resistor R2 is connected to capacitor C16... The other ends of capacitors C1, C8, and C7 are connected. The other end of capacitor C1 is grounded. The other end of capacitor C16 is grounded. Pin 2 of chip U2 is grounded. Pin 3 of chip U2 is connected to capacitor C9 and inductor L4. The other end of inductor L4 is connected to capacitors C21, C28, and C33, resistors R9 and R10. The other end of capacitor C21 is grounded. The other end of capacitor C28 is connected to the other end of capacitor C33 and ground. The other end of capacitor C9 is connected to capacitor C10, resistor R4, and resistor R3. The other end of resistor R3 is connected to resistor R1, capacitor C11, and the other end of capacitor C10. The other end of resistor R1 is grounded. The other end of resistor R4 is grounded. The other end of capacitor C11 is connected to pin 2 of chip U4.Pin 1 of chip U4 is connected to pin 3 of chip U4 and ground. Pin 4 of chip U4 is connected to pin 6 of chip U4 and ground. Pin 5 of chip U4 is connected to capacitor C12 and inductor L5. The other end of capacitor C12 is connected to capacitors C15 and C13. The other end of capacitor C13 is connected to capacitors C2 and C14. The other end of inductor L5 is connected to capacitors C23, C29, C34, resistor R11, and resistor R12. The other end of capacitor C23 is grounded. The other end of capacitor C29 is connected to the other end of capacitor C34 and ground. The other end of resistor R13 is connected to the other ends of resistors R14, R7, R8, R9, R10, R11, R12, capacitors C38 and C39, and chip U6.

[0017] As a further technical solution of this utility model: the model number of the chip U1 is TQP369180.

[0018] As a further technical solution of this utility model: the model number of the chip U2 is TQP369180.

[0019] As a further technical solution of this utility model: the chip U3 is model HMC8410LP2FETR.

[0020] As a further technical solution of this utility model: the model of the chip U4 is HMC788ALP2ETR.

[0021] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0022] Wideband coverage and flat gain: Through a rationally designed multi-stage amplifier structure and LC matching network, a flat gain response is achieved over a wide frequency range (30MHz-6 GHz). Compared with existing solutions, this design significantly improves frequency coverage and avoids the test discontinuity caused by frequency band switching in traditional RF testing.

[0023] High signal integrity: The use of a low-noise amplifier (LNA) as the first stage effectively reduces the system noise figure and ensures the signal-to-noise ratio (SNR) of the signal chain.

[0024] The subsequent gain amplification modules (second and third stages) achieve stable gain through high linearity amplifiers and suppress reflections and interference through isolation and matching networks.

[0025] The final stage uses an LNA again to optimize the output impedance and reduce output distortion, ensuring the integrity of the RF signal.

[0026] Modular Design: Each amplifier stage features a modular design for easy independent optimization. Modules are connected via precise impedance matching networks to reduce inter-stage reflections and improve power transfer efficiency. The PCB layout employs individually shielded power management and signal isolation to avoid interference and reflections.

[0027] Application Flexibility: The system's wide bandwidth and high gain characteristics make it highly adaptable to application scenarios such as EMC and EMI testing, communication testing, and radar signal amplification.

[0028] This avoids the frequency band segmentation testing requirements common in the existing market, reducing testing complexity and cost. Attached Figure Description

[0029] Figure 1 This is the overall circuit diagram of this utility model. Detailed Implementation

[0030] The technical solutions in the embodiments of this utility model will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0031] like Figure 1 As shown, a wideband high-gain radio frequency amplifier circuit consists of four stages of amplifier circuitry, wherein:

[0032] The first-stage circuit is a low-noise amplifier (LNA) based on the HMC8410LP2FETR, used for the first stage of RF front-end signal amplification, focusing on improving signal strength while maintaining a low noise figure. This circuit achieves low-noise amplification of RF signals using the high-performance HMC8410 LNA chip, suitable for wideband applications from 0.1 GHz to 6 GHz. The input / output matching network, bypass filter capacitors, and bias circuitry in the design collectively ensure the circuit's performance, including high gain, low noise, and wideband stability.

[0033] (1) Input matching network:

[0034] L1 and C18 form an input impedance matching network to match the input impedance of the HMC8410, making it match the characteristic impedance of the RF input signal source (usually 50Ω), maximizing power transmission efficiency and reducing the reflection coefficient.

[0035] C3: DC blocking capacitor, used to isolate the DC component of the input signal to ensure the normal transmission of radio frequency signals.

[0036] R5: This is a bias resistor used to provide appropriate VGG bias and stabilize circuit performance to some extent.

[0037] (2) Output matching network:

[0038] L2, C19: Used to match the impedance of the output terminal to the load (usually 50Ω) to ensure power transmission efficiency and reduce return loss.

[0039] C4: DC blocking capacitor, used to isolate DC components and ensure the radio frequency characteristics of the output signal.

[0040] (3) Bias circuit:

[0041] VGG (Gate Bias Voltage):

[0042] It provides gate bias, adjusts the chip's operating point to control the drain current (IDQ), thereby optimizing gain and linearity.

[0043] C25, C30, C35: These bypass filters the bias voltage to suppress low-frequency noise and power supply ripple interference.

[0044] VDD (drain bias voltage):

[0045] It provides drain voltage (+5V) to power the amplifier.

[0046] C26, C31, C36: Bypass filtering of the drain power supply voltage to suppress high-frequency and low-frequency interference.

[0047] (4) Bypass filtering:

[0048] Multi-stage filter capacitor design in bias circuit:

[0049] High-frequency band (C25, C26, such as 1nF): suppresses high-frequency noise.

[0050] Mid-frequency band (C30, C31, such as 100nF): Suppresses mid-frequency ripple.

[0051] Low frequency band (C35, C36, such as 1μF): suppresses low frequency fluctuations and power supply noise.

[0052] This multi-stage filtering design covers a wide range of noise suppression requirements from low to high frequencies, effectively improving the stability of the bias circuit.

[0053] (5) Thermal stability design:

[0054] Resistors R5 and R6: Introducing resistors in the bias circuit helps control the current and avoid chip bias drift caused by temperature changes, thereby improving the temperature stability of the circuit.

[0055] The second and third stage circuits are second-stage and third-stage gain modules based on the TQP369180 RF amplifier chip. The overall design focuses on achieving high-gain, high-efficiency broadband RF signal amplification, serving as the intermediate gain section of the broadband RF amplifier circuit and optimizing the signal amplification link.

[0056] (1) Input / output impedance matching network: C5, C6, C8, C9: DC isolation capacitors used to isolate the DC component in the RF signal to avoid affecting subsequent circuits. L3, L4 and C20, C21: form an LC matching network, which achieves wideband matching between the chip's input / output impedance and the system impedance (50Ω) by adjusting the component values. The matching network optimizes the power transmission efficiency of the RF signal and reduces return loss, making it particularly suitable for broadband amplification of high-frequency signals. C7, C10 and resistors R2, R3: assist in achieving load matching of the RF signal and also provide DC isolation to ensure the stability of the signal transmission in subsequent stages.

[0057] (2) Bias circuit: R7, R9 and R8, R10: provide the bias current required by the RF amplifier, stabilize the chip operating point, and adjust the bias value to optimize the chip linearity and gain performance. C27, C28 and C32, C33: form a multi-stage filter network.

[0058] (3) Gain Distribution and Optimization: Through a two-stage amplification design, the gain of each stage is determined by the chip characteristics. The typical gain of the TQP369180 is 15dB, and the two-stage design can provide approximately 30dB of gain. Reasonable bias and matching design ensures that the signal transmission efficiency between the two stages is maximized, avoiding excessive reflection or signal loss.

[0059] (4) Wideband characteristics: The selection of LC matching network and high-quality passive components (such as inductors L3 / L4 (preferably power inductors) and capacitors C20 / C21) ensures the flatness of the gain of the whole system over a wide bandwidth, avoiding frequency band selective amplification.

[0060] The fourth-stage amplifier circuit, based on the HMC788ALP2ETR as its core amplifier chip, is the final stage of the entire RF signal chain. The main design goal of this stage is to provide additional gain while further optimizing output impedance matching to ensure high-fidelity RF signal output and meet the application requirements of wide-band RF signals.

[0061] (1) Input impedance matching network: C11: DC isolation capacitor, used to block DC signal components and ensure the purity of RF signal input to amplifier.

[0062] (2) Bias circuit: R11 and R12 form the bias path, providing the stable bias current required by the HMC788ALP2ETR chip. C34 and C29 filter capacitors are used to remove noise signals in the power supply and optimize the chip's operating power environment. The bias design ensures that the chip maintains stable gain and high linearity over a wide frequency range.

[0063] (3) Output impedance matching network: L5 and C23: form an LC matching network to adjust the chip's output impedance to the standard 50Ω, optimizing the transmission efficiency of RF signals. C12: DC isolation capacitor, used to block DC signal components and ensure the purity of RF signal output. C13, C14, C2 and C15 serve as additional bypass filters to further reduce noise in the RF output.

[0064] Through multi-stage amplification and a meticulously designed inter-stage matching network, a wideband flat gain from 30MHz to 6GHz was achieved. This design effectively avoids gain fluctuations caused by frequency variations, ensuring consistent signal chain performance across the entire frequency band. Furthermore, the coordination between PCB layout and structural design is crucial to the success of this solution: independent isolation of each module, optimized power supply design, and anti-interference layout further enhance the stability and reliability of the entire system.

[0065] The working principle is as follows:

[0066] (1) Multistage amplifier structure:

[0067] Level 1:

[0068] This low-noise LNA amplifier uses the HMC8410 chip and incorporates bias and impedance matching networks to achieve low-noise amplification. An LC network (inductor L1 and capacitor C18) provides input matching and reduces noise reflections.

[0069] Second and third levels: intermediate gain module:

[0070] The TQP369180 amplifier is used, and impedance continuity is achieved through interstage matching networks (L3 and C20).

[0071] A moderate gain boost ensures the linearity and gain flatness of the system signal chain.

[0072] Level 4: LNA Optimized Output:

[0073] Using the HMC788ALP2ETR chip, combined with the output matching network (L5 and C13), low distortion and high impedance matching of the output signal are ensured.

[0074] (2) PCB layout and structural design:

[0075] Module isolation and shielding:

[0076] Each module has its own separate signal path to avoid signal interference and reflection.

[0077] The signal lines of key RF modules adopt a 50Ω impedance matching design to ensure the continuity of characteristic impedance.

[0078] Power management isolation:

[0079] Each module power supply uses independent decoupling capacitors (such as C34 and C36) and filter networks to reduce power supply noise.

[0080] In the PCB layout, an RF ground plane and multi-layer design are used to ensure isolation between power and signals.

[0081] Test Implementation and Optimization:

[0082] Input / output matching debugging: Use a vector network analyzer (VNA) to measure the S-parameters of the input and output to ensure that S11 < -10dB and S22 < -10dB, so as to achieve good matching performance.

[0083] Gain flatness verification: Independent testing of each stage of the amplifier, adjustment of the matching network to ensure the consistency of gain of each stage (typical value <3.0dB).

[0084] Frequency and gain verification: Adjust the bias voltage to optimize to the target range, and use a vector network analyzer (VNA) to measure the input and output S-parameters to ensure a total gain of 40dB in the frequency range of 30MHz to 6GHz.

[0085] Noise figure test:

[0086] Test system noise figure: Ensure noise is kept within a reasonable range (typical value <3dB).

[0087] Maximum input power: Increasing the input power to -30dBm will allow the test system to achieve a gain of 40dB without damage.

[0088] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention.

[0089] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment have been appropriately combined to form other embodiments that are easy for those skilled in the art to understand.

Claims

1. A wideband high-gain radio frequency amplifier circuit, comprising a first-stage amplification module, a second-stage amplification module, a third-stage amplification module, and a fourth-stage amplification module, characterized in that: The first-stage amplification module includes chip U3, inductors L1 and L2, and resistor R5. The second-stage amplification module includes chip U1, inductor L3, capacitors C5, C6, and C27. The third-stage amplification module includes chip U2, capacitors C8 and C9, and inductor L4. The fourth-stage amplification module includes chip U4, capacitors C11 and C12, and inductor L5. Pin 2 of chip U3 is connected to capacitor C3 and inductor L1. The other end of inductor L1 is connected to capacitor C18 and resistor R5. The other end of resistor R5 is connected to capacitors C25, C30, C35, R20, C46, ​​C48, and R19. The other end of capacitor C46 is connected to the other end of capacitor C48, the other end of resistor R19, and... The ground terminal is connected to the other end of resistor R20, which is connected to resistor R16 and capacitor C47. The other end of capacitor C47 is grounded. The other end of resistor R16 is connected to resistor R18 and chip U7. The other end of resistor R18 is grounded. Pin 4 of chip U3 is connected to capacitors C17, C22, and C24. The other end of capacitor C17 is connected to the other ends of capacitors C22 and C24. Pin 5 of chip U3 is connected to capacitor C4 and inductor L2. The other end of inductor L2 is connected to capacitor C19 and resistor R6. The other end of resistor R6 is connected to capacitors C26, C31, C36, resistor R13, and resistor R14. The other end of capacitor C19 is connected to the other ends of capacitors C26, C31, and C36. The other end of capacitor C4 is connected to the ground terminal. The other end of capacitor C4 is connected to capacitor C5. The other end of capacitor C5 is connected to pin 1 of chip U1. Pin 2 of chip U1 is grounded. Pin 3 of chip U1 is connected to capacitor C6 and inductor L3. The other end of inductor L3 is connected to capacitors C20, C27, C32, resistor R7, and resistor R8. The other end of capacitor C20 is grounded. The other end of capacitor C27 is connected to the other end of capacitor C32 and the ground terminal. The other end of capacitor C6 is connected to capacitors C7, C16, and resistor R2. The other end of resistor R2 is connected to capacitors C1, C8, and the other end of capacitor C7. The other end of capacitor C1 is grounded. The other end of capacitor C16 is grounded. Pin 2 of chip U2 is grounded. Pin 3 of chip U2 is connected to capacitor C6. C9 and inductor L4 are connected. The other end of inductor L4 is connected to capacitors C21, C28, and C33, resistors R9 and R10. The other end of capacitor C21 is grounded. The other end of capacitor C28 is connected to the other end of capacitor C33 and ground. The other end of capacitor C9 is connected to capacitor C10, resistors R4 and R3. The other end of resistor R3 is connected to resistor R1, capacitor C11, and the other end of capacitor C10. The other end of resistor R1 is grounded. The other end of resistor R4 is grounded. The other end of capacitor C11 is connected to pin 2 of chip U4. Pin 1 of chip U4 is connected to pin 3 of chip U4 and ground. Pin 4 of chip U4 is connected to pin 6 of chip U4 and ground. Pin 5 of chip U4 is connected to capacitor C12 and inductor L5.The other end of capacitor C12 is connected to capacitors C15 and C13. The other end of capacitor C13 is connected to capacitors C2 and C14. The other end of inductor L5 is connected to capacitors C23, C29, and C34, resistors R11 and R12. The other end of capacitor C23 is grounded. The other end of capacitor C29 is connected to the other end of capacitor C34 and ground. The other end of resistor R13 is connected to the other ends of resistors R14, R7, R8, R9, R10, R11, and R12, as well as capacitors C38 and C39 and chip U6.

2. The wideband high-gain radio frequency amplifier circuit according to claim 1, characterized in that, The chip U1 is model number TQP369180.

3. The wideband high-gain radio frequency amplifier circuit according to claim 1, characterized in that, The chip U2 is model number TQP369180.

4. The wideband high-gain radio frequency amplifier circuit according to claim 1, characterized in that, The chip U3 is model HMC8410LP2FETR.

5. A wideband high-gain radio frequency amplifier circuit according to claim 1, characterized in that, The model number of the chip U4 is HMC788ALP2ETR.

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