Integrated circuit structure

Abstract

In one embodiment, an integrated circuit (IC) structure is described, and a method for fabricating the integrated circuit (IC) structure is described. In some embodiments, a structure includes a fin-shaped structure disposed over a substrate, the fin-shaped structure including a first segment and a second segment and a bottom surface between the first segment and the second segment, and the bottom surface including a plurality of recesses. The structure further includes a dielectric material disposed between the first segment and the second segment of the fin structure, and the dielectric material is disposed on the bottom surface and in the plurality of recesses. The IC structure further includes a gate structure disposed over the first segment of the fin-shaped structure, and the gate structure covers a top surface and a plurality of side surfaces of the first segment of the fin-shaped structure.

Description

Technical Field

[0001] Some embodiments of this disclosure provide integrated circuit structures. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using fabrication processes) has decreased. This shrinkage typically benefits production efficiency and reduces associated costs. This shrinkage has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are required to achieve these advancements. For example, high-voltage field-effect transistors (FETs) for high-voltage applications face various challenges, including breakdown voltage, on-state channel resistance, drain saturation current, off-state current, and signal-to-noise ratio. Therefore, while conventional high-voltage FETs are generally sufficient for their intended use, they are not perfect in every aspect. Utility Model Content

[0003] Some embodiments of this disclosure provide an integrated circuit structure, including a fin structure, a dielectric material, and a gate structure. The fin structure is disposed above a substrate, wherein the fin structure includes a first segment and a second segment, and a bottom surface located between the first segment and the second segment, and the bottom surface includes a plurality of grooves. The dielectric material is disposed between the first and second segments of the fin structure, wherein the dielectric material is disposed on the bottom surface and in the grooves. The gate structure is disposed above the first segment of the fin structure, wherein the gate structure covers the top surface and a plurality of side surfaces of the first segment of the fin structure.

[0004] Some embodiments of this disclosure provide an integrated circuit structure including a first field-effect transistor (FET) and a second FET. The first FET is disposed above a substrate and includes a first source, a drain, a first gate structure, and a first shallow trench isolation feature. The first gate structure is disposed between the first source and the drain. The first shallow trench isolation feature is disposed between the first source and the drain, wherein the first shallow trench isolation feature is disposed on a first bottom surface of the substrate, and the first bottom surface includes a first plurality of bumps. The second FET is disposed above the substrate and includes a second source, a drain, a second gate structure, and a second shallow trench isolation feature. The second gate structure is disposed between the second source and the drain. The second shallow trench isolation feature is disposed between the second source and the drain.

[0005] Some embodiments of this disclosure provide an integrated circuit structure, including a fin structure, a dielectric material, and a gate structure. The fin structure is disposed above a substrate, wherein the fin structure includes a first segment and a second segment, and a bottom surface located between the first segment and the second segment. The dielectric material is disposed between the first and second segments of the fin structure, wherein the dielectric material is disposed on the bottom surface. The gate structure is disposed above the first segment of the fin structure, wherein the gate structure covers the top surface and a plurality of side surfaces of the first segment of the fin structure, wherein one of these side surfaces forms an acute or obtuse angle with the bottom surface. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A top view of an integrated circuit (IC) structure including two FETs according to some embodiments;

[0008] Figure 1B According to some embodiments Figure 1A A cross-sectional view of the IC structure;

[0009] Figure 2A This is a top view of an IC structure according to some embodiments;

[0010] Figure 2B According to some embodiments Figure 2A Cross-sectional view of the IC structure;

[0011] Figures 3A to 3C Manufacturing according to some embodiments Figure 2A A cross-sectional side view of one of the various stages of an IC structure;

[0012] Figures 4A to 4C Manufacturing according to some embodiments Figure 2A Various views of the various stages of the IC structure;

[0013] Figures 5A to 5C Manufacturing according to some embodiments Figure 4C A cross-sectional side view of one of the various stages of an IC structure;

[0014] Figures 6A to 6D A cross-sectional side view of one of the various stages of manufacturing an IC structure according to some embodiments;

[0015] Figures 7A to 7CA cross-sectional side view of one of the various stages of manufacturing an IC structure according to some embodiments;

[0016] Figure 8 According to some embodiments Figure 7A A top view of the IC structure.

[0017] [Symbol Explanation]

[0018] 100: Integrated Circuit Structure

[0019] 102:Substrate

[0020] 104: p-type doped region / deep p-well

[0021] 106: N-well region / N-well

[0022] 108: P-well region / P-well

[0023] 110: Isolation Structure / Shallow Trench Isolation Features / Shallow Trench Isolation Structure

[0024] 112, 112F: Active Zone

[0025] 112P: Planar region / Planar active region

[0026] 114: Source Region / Source

[0027] 116: Drain region / drain electrode

[0028] 118, 332: Gate structure

[0029] 120: Neutral Zone

[0030] 122: Channel

[0031] 302: Fin-shaped structure

[0032] 304, 324: Opening

[0033] 306: Bottom surface

[0034] 308: Top surface

[0035] 310: Side surface

[0036] 312: Part One

[0037] 314: Part Two

[0038] 316: Masking layer

[0039] 320: Groove

[0040] 322: Fins

[0041] 326: Protrusion

[0042] 328: Bump

[0043] 330: Shallow trench isolation features

[0044] 334: Source

[0045] 336: Drain

[0046] A:Angle

[0047] AA', BB', CC': Dashed lines

[0048] FET-I and FET-II: n-type field-effect transistors

[0049] H1: Height

[0050] W1, W2: Width

[0051] X:X direction

[0052] Y: Y direction

[0053] Z:Z direction Detailed Implementation

[0054] The following disclosure provides many different embodiments or instances for implementing different features. Reference numerals and / or letters may be repeated in the various instances described herein. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various disclosed embodiments and / or configurations. Furthermore, the specific examples of elements and configurations described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, in this disclosure, forming a feature on another feature, forming a feature connected to another feature, and / or forming a feature coupled to another feature may include embodiments where these features are formed in direct contact, and may also include embodiments where additional features are formed to be inserted between these features so that these features are not in direct contact.

[0055] Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, the formation of a feature on another feature, a feature connected to another feature, and / or a feature coupled to another feature may include embodiments where these features are formed in direct contact, and may also include embodiments where additional features are formed to be inserted between these features so that these features are not in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “up,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to simplify the relationship between one feature and another in some embodiments of this disclosure. Spatially relative terms are intended to cover different orientations of the means comprising the feature. Furthermore, when using "about," "approximately," and similar terms to describe numbers or ranges of numbers, the term is intended to cover numbers within a reasonable range that includes the number being described (such as within + / - 10% of the described number or other values ​​as understood by one skilled in the art). For example, the term "about 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0056] Some embodiments of this disclosure generally relate to integrated circuit (IC) structures and methods of manufacturing thereof, and more specifically to high-voltage field-effect transistor (FET) structures. In various embodiments, the IC structure includes a planar FET structure and multi-gate devices, such as fin-like field-effect transistors (FinFETs). An isolation region, such as shallow trench isolation (STI), located between the source and drain regions of the FinFET, can be disposed on a modified bottom surface of the fin structure. Therefore, the breakdown voltage is increased while maintaining a high current flowing through the device.

[0057] The disclosed IC structure is a high-voltage metal-oxide-semiconductor (HVMOS) device structure. The IC structure can be a hybrid structure including a planar active region, such as a planar FET device, and a three-dimensional (3D) active region, such as a multi-gate FET device. Examples of multi-gate devices include fin-like field-effect transistors (FinFETs) with fin structures and multi-bridge-channel (MBC) configurations. MBC transistors have gate structures that extend partially or completely around the channel region to provide pathways to the channel region on two or more sides. Because the gate structure of an MBC transistor surrounds the channel region, an MBC transistor can also be referred to as a surrounding-gate transistor (SGT) or a gate-all-around (GAA) transistor with multiple vertically stacked channel components. The IC structure can include other suitable device structures, such as forked FETs and complementary FET (CFET) structures. Various embodiments of the IC structure and its fabrication methods are described in detail according to the various embodiments disclosed herein.

[0058] According to some embodiments, Figure 1A This is a top view of an IC structure 100 having one or more FETs. Figure 1B Along IC structure 100 Figure 1A The cross-sectional view is shown by the dashed line AA'. In the embodiments disclosed herein, the FET of IC structure 100 is designed for high-voltage applications and is therefore also referred to as a high-voltage FET (HVFET). In the disclosed embodiments of IC structure 100, one or more n-type FETs (nFETs) are provided as illustrative examples. However, this is not intended to be limiting, and alternatively, IC structure 100 may include one or more p-type FETs (pFETs). Figure 1A and Figure 1B In the IC structure 100, there are two FETs configured side by side, and the two FETs share a common drain.

[0059] IC structure 100 includes a substrate 102. The substrate 102 is a semiconductor substrate. In some embodiments, the semiconductor substrate 102 comprises silicon. In some embodiments, the substrate 102 comprises germanium, silicon germanium, or other suitable semiconductor materials. Alternatively, the substrate 102 may be made of a suitable elemental semiconductor such as diamond or germanium, a suitable compound semiconductor such as silicon carbide, indium arsenide, or indium phosphide, or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenide, or gallium indium phosphide.

[0060] According to various embodiments, substrate 102 may include buried layers, such as an n-type buried layer (NBL), a p-type buried layer (PBL), and a buried dielectric layer comprising a buried oxide (BOX) layer. In the disclosed embodiments, substrate 102 includes a p-type doped region 104 located at a deep level of substrate 102. The p-type dopant includes boron, gallium, indium, other suitable p-type dopant, or combinations thereof. Therefore, p-type doped region 104 is also referred to as deep P-well 104. In some embodiments, substrate 102 may include a BOX layer located below the deep P-well 104. The deep P-well 104 can be formed by ion implantation, and the BOX layer can be formed by a method known as separation by implanted oxygen (SIMOX).

[0061] The substrate 102 also includes an N-well region (or simply N-well) 106 (also referred to as a high-voltage N-well or HVNW) and a P-well region (or simply P-well) 108 formed above the deep P-well 104. Figure 1A As illustrated, in the top view, the P-well 108 surrounds and encloses the N-well 106. The N-well 106 and P-well 108 are formed using suitable methods such as ion implantation with appropriate dopant, implantation energy, and dopant dosage to achieve the desired doping type, doping degree, doping thickness, and doping concentration. Figure 1A In the top view illustrated, according to the disclosed embodiment, the P-well 108 surrounds and encloses the N-well 106. The P-well 108 is doped with a p-type dopant such as boron, while the N-well 106 is doped with an n-type dopant such as phosphorus. In another embodiment, the N-well 106 and P-well 108 can be formed respectively by any suitable process having multiple processing steps, such as forming a patterned mask by photolithography and patterning, applying an ion implantation process to the substrate 102 through an opening in the patterned mask, and subsequently removing the patterned mask. In the disclosed embodiment, the N-well 106 serves as a drift region for the nFET to be formed, while the P-well 108 provides a channel 122 for the nFET.

[0062] In addition, such as Figure 1A As explained, the neutral region 120 is inserted between the N-well 106 and the P-well 108, such that in a top view, the neutral region 120 surrounds and encloses the N-well 106, while the P-well 108 surrounds and encloses the neutral region 120. The neutral region 120 is designed to improve the performance of the IC structure 100, especially the performance of the high-voltage FET, including increased breakdown voltage, reduced resistance of the HVFET in the on-state, and reduced current of the HVFET in the off-state.

[0063] Neutral region 120 is a region in semiconductor substrate 102 that is free of dopants. This can be achieved by suitable methods, such as redesigning the photomask used to form N-well 106 and P-well 108 so that neutral region 120 is un-deployed. Neutral region 120 includes an inner edge that continuously contacts N-well 106 and an outer edge that continuously contacts P-well 108. IC structure 100 also includes an isolation structure 110 formed on substrate 102, thereby defining active region 112, which is a semiconductor surface region for active devices (such as FETs) to be formed thereon. Figure 1B In the IC structure 100 described herein, the active region 112 is planar, finned, or a combination thereof (also referred to as a hybrid active region). A finned active region is a three-dimensional (3D) active region used to increase the coupling between the channel and the gate. However, this is not intended as a limitation. The active region may have any suitable contour, such as other suitable 3D contours.

[0064] The isolation structure 110 includes one or more dielectric materials and provides separation and isolation between various devices formed on the active region 112. The isolation structure 110 can be formed by any suitable method and can have any suitable geometry. In the disclosed embodiments, the isolation structure 110 includes a shallow trench isolation (STI) feature (also indicated by the numeral 110) formed on the substrate 102. In some embodiments, the STI feature 110 is formed by a suitable process including patterning to form trenches, filling the trenches with a dielectric material, and polishing to remove excess dielectric material and planarize the top surface. The patterning process includes photolithography, etching, and may further include forming a patterned hard mask. One or more etching processes are performed on the substrate 102 through openings in the patterned hard mask, these openings being formed by photolithography patterning and etching. The formation of the STI feature 110 is further described below according to some embodiments.

[0065] In some embodiments, a hard mask is deposited on substrate 102 and patterned by a photolithography process. The hard mask comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials, such as metal oxides. In one embodiment, the hard mask comprises a silicon oxide film and a silicon nitride film. The hard mask can be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), other suitable deposition processes, or combinations thereof.

[0066] A photoresist layer (or resist) defining the isolation structure 110 can be formed on a hard mask. The photoresist layer contains a photosensitive material that causes the photoresist layer to undergo a property change upon exposure to light such as ultraviolet (UV), deep UV (DUV), or extreme UV (EUV). This property change can be used to selectively remove exposed or unexposed portions of the resist layer via the aforementioned development process. This procedure for forming the patterned resist layer is also known as lithography.

[0067] In one embodiment, the resist layer is patterned to retain a portion of the photoresist material disposed above the substrate 102 by a photolithography process. After the resist is patterned, the substrate 102 is etched to open the hard mask, thereby transferring the pattern from the resist layer to the hard mask. After the hard mask is patterned, the remaining resist layer can be removed. The photolithography process includes spin-coating the resist layer, soft baking of the resist layer, mask alignment, exposure, post-exposure baking, developing the resist layer, rinsing, and drying (e.g., hard baking). Alternatively, the photolithography process can be implemented, supplemented, or replaced by other suitable methods such as maskless photolithography, electron beam writing, and ion beam writing. The etching process used to pattern the hard mask can include wet etching, dry etching, or a combination thereof. The etching process can include multiple etching steps. For example, the silicon oxide film in the hard mask can be etched with a diluted hydrofluoric acid solution, and the silicon nitride film in the hard mask can be etched with a phosphoric acid solution.

[0068] Next, an etching process can be performed to etch the portions of substrate 102 not covered by the patterned hard mask. The patterned hard mask is used as an etching mask during the etching process to pattern the substrate 102. The etching process can include any suitable etching technique, such as dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps with different etching chemicals, these etching steps being designed to etch substrate 102 to form trenches with specific trench profiles to obtain improved device performance and pattern density. In some instances, the semiconductor material of substrate 102 can be etched using a dry etching process using a fluorine-based etchant. Specifically, the etching process applied to substrate 102 is controlled such that substrate 102 is partially etched. This can be achieved by controlling the etching time or by controlling other etching parameters. After the etching process, active region 112 is defined on substrate 102.

[0069] One or more dielectric materials are filled in the trench to form STI feature 110. Suitable dielectric materials include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorinated silica glass (FSG), low-k dielectric materials, and / or combinations thereof. In various embodiments, the dielectric material is deposited using HDP-CVD, sub-atmospheric CVD (SACVD), high-aspect-ratio process (HARP), flowable CVD (FCVD), and / or spin-coating processes.

[0070] Following the deposition of the dielectric material, a chemical mechanical polishing / planarization (CMP) process can be performed to remove excess dielectric material and planarize the top surface of the structure. The CMP process may use a patterned hard mask as a polishing termination layer to prevent polishing of the semiconductor substrate 102. In some embodiments, the CMP process completely removes the patterned hard mask. Alternatively, the patterned hard mask can be removed by an etching process. However, in other embodiments, a portion of the patterned hard mask is retained after the CMP process.

[0071] In some embodiments, this method further includes forming the finned active region 112 by a suitable method, such as removing a portion of the substrate 102 to form a trench-separated finned structure. Alternatively, the finned active region 112 is formed by epitaxial growth of a finned structure extending from the substrate 102, with the finned structure being trench-separated. In some embodiments, the bottom of the trench is modified before forming the STI structure 110 in the trench between adjacent finned structures to increase the breakdown voltage while maintaining a high current flowing through the device. The modification of the bottom of the trench in the finned active region 112 is described in the following embodiments. Figures 5A to 5C It is described in detail in the text.

[0072] The active regions 112 are spaced apart from each other. The active regions 112 may have an elongated shape oriented longitudinally along a first direction (X direction). A second direction (Y direction) is orthogonal to the X direction. The X and Y axes define the top surface of the substrate 102. In some embodiments, the STI feature 110 includes two extensions to define three active regions: a first active region, a second active region, and a third active region, as described in... Figure 1A And more clearly explained in Figure 2A middle.

[0073] In some embodiments, a first active region 112 is formed directly on and disposed within the N-well 106. The first active region 112 spans along the X direction between two extensions of the STI feature 110. A second active region 112 is disposed on one side (such as the left side) of the first active region 112 and includes a portion of the N-well 106, a neutral region 120, and a portion of the P-well 108 along the X direction. A third active region 112 is disposed on the other side (such as the right side) of the first active region 112 and includes a portion of the N-well 106, a neutral region 120, and a portion of the P-well 108 along the X direction. As mentioned above, the active region 112 may be a hybrid active region comprising planar active regions and fin-shaped active regions.

[0074] One or more FETs are formed in the active region 112. Each FET includes a source region (or simply source) 114, a drain region (or simply drain) 116, and a gate structure 118 disposed between the source 114 and the drain 116. The source 114 and drain 116 are formed in the substrate 102, and the gate structure 118 is formed on the substrate 102. Figure 1A and Figure 1B In the disclosed embodiment described herein, IC structure 100 includes two nFETs (FET-I and FET-II) sharing a common drain 116.

[0075] Gate structure 118 includes a gate stack, which may further include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes one or more dielectric materials, such as silicon oxide, high-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer includes one or more high-k dielectric materials and may further include an interface layer (such as silicon oxide) disposed between the channel and the high-k dielectric material. The high-k dielectric material may include metal oxides, metal nitrides, such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), or other suitable high-k dielectric materials. The interface layer may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials. The interface layer can be formed by suitable methods such as atomic layer deposition (ALD), CVD, ozone oxidation, etc. A high-k dielectric layer, if present, can be deposited on the interface layer using suitable techniques such as ALD, CVD, metal-organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and / or other suitable techniques.

[0076] The gate electrode comprises one or more conductive materials, such as doped polycrystalline silicon, metals, or metal alloys. The metal in the gate electrode includes aluminum, copper, tungsten, ruthenium, cobalt, nickel, metal silicides, other suitable metal-containing conductive materials, or combinations thereof. In some embodiments, the gate electrode may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, any suitable material, or combinations thereof.

[0077] The gate structure 118 may further include gate sidewall features (or gate spacers) formed on the sidewalls of the gate electrode and the gate dielectric layer. The gate spacers provide isolation between the gate electrode and the source / drain regions. The gate spacers may comprise any suitable dielectric material, such as semiconductor oxides, semiconductor nitrides, semiconductor carbides, semiconductor oxynitrides, other suitable dielectric materials, and / or combinations thereof. The gate spacers may have a multilayer structure, such as a two-layer structure (silicon oxide and silicon nitride) or a three-layer structure (silicon oxide; silicon nitride; and silicon oxide). The formation of the gate spacers includes deposition and anisotropic etching, such as dry etching.

[0078] The formation of the gate structure 118 includes depositing various gate materials and using a process including photolithography and etching to pattern the deposited gate material. In some embodiments, the gate structure 118 can be formed by a gate replacement process, in which a dummy gate structure is formed and replaced at a later stage, such as after the formation of the source 114 and drain 116, to avoid undesirable effects of thermal processes on the gate structure 118.

[0079] In some embodiments, the gate structure 118 is divided into multiple segments to achieve various manufacturing benefits, such as tuned pattern density and improved processing (such as CMP) uniformity. In the disclosed embodiment, the gate structure 118 of the first nFET (FET-1) includes a first segment disposed between the drain 116 and the STI feature 110; and a second segment disposed between the source 114 and the STI feature 110. To facilitate the embodiment, the first segment of the gate structure 118 is formed and floating for manufacturing benefits, meaning that the first segment is not to be biased and does not serve as the gate of the first nFET. The second segment of the gate structure 118 is used to connect to a power signal line such that it is biased as the functional gate of the first nFET. Due to the different functions of the first and second segments of the gate structure 118, the first and second segments can be designed to have different dimensions. For example, the second segment may have a larger dimension along the X direction than the first segment. In some embodiments, the second segment of the gate structure 118 lands on the P-well 108, the neutral region 120, and the N-well 106. The second segment of the gate structure 118 is capacitively coupled to the P-well 108, thereby controlling the channel 122 of the first nFET. The channel 122 is the portion of the P-well 108 located below the second segment of the gate structure 118. The second nFET (FET-II) is similar to the first nFET in layout and configuration. For example, the gate structure 118 of the second nFET also includes two segments: one segment is floating and disposed between the drain 116 and the STI feature 110; while the other segment is biased and disposed between the STI feature 110 and the source 114.

[0080] The source 114 and drain 116 are semiconductor features doped with appropriate dopants. For example, in Figure 1A and Figure 1B In the embodiments described herein, an nFET is formed, and the source 114 and drain 116 are doped with an n-type dopant, such as phosphorus. This is merely illustrative and not intended to be limiting. It should be understood that, alternatively or additionally, one or more pFETs may be formed. For a pFET, the source 114 and drain 116 are doped with a p-type dopant. Furthermore, the doped wells 106 and 108 are correspondingly interchanged as p-type wells and n-type wells.

[0081] In some embodiments, the source 114 and drain 116 are formed by diffusion or ion implantation. In some embodiments, the source 114 and drain 116 are formed by a procedure comprising the following steps: etching substrate 102 to form source / drain (S / D) trenches; and epitaxially growing one or more semiconductor materials such as silicon or silicon-germanium to achieve a strain effect with enhanced carrier mobility. In this case, dopants may be introduced into the source 114 and drain 116 during epitaxial growth. In some embodiments, a thermal annealing process may be performed to activate the source 114 and drain 116. In some embodiments of this disclosure, the source region and drain region are used interchangeably and their structures are substantially the same. Furthermore, individually or collectively, depending on the context, the source / drain region may refer to either the source or the drain.

[0082] exist Figure 1A and Figure 1B In the described embodiment, IC structure 100 includes two nFETs arranged side-by-side with a common drain 116. Figure 1B As described, the source 114, drain 116, and the portion of the gate structure 118 located to the left of the drain 116 (such as the second segment) constitute a first nFET (FET-I); while the source 114, drain 116, and the portion of the gate structure 118 located to the right of the drain 116 constitute a second nFET (FET-II). The first nFET and the second nFET share a common drain 116. In some embodiments, the common drain 116 is formed in the N-well 106, and the source 114 is formed in the P-well 108.

[0083] Figure 2A This is a top view of an IC structure 100 with two high-voltage FETs. Figure 2B Along IC structure 100 Figure 2A The cross-sectional view is taken by the dashed line AA'. For simplicity, Figure 2A and Figure 2B Only STI feature 110 and active region 112 are described.

[0084] like Figure 2A As described, the IC structure 100 includes three active regions 112: a left active region, a central active region, and a right active region. In some embodiments, the IC structure 100 includes a hybrid structure with planar active regions and 3D active regions. For example, Figure 2A The three active regions 112 shown are 3D active regions with FinFETs, and as... Figure 2B As shown, the IC structure 100 further includes a planar region 112P. For simplicity, Figure 2A Planar region 112P is not shown in the diagram. For example... Figure 2BAs shown, the active region 112F (which is Figure 2A The central active region 112 shown contains multiple fin-shaped structures as channels. For simplicity, Figure 2B The gate stack and STI feature disposed between adjacent fin structures are not shown. In some embodiments, each fin structure has a height H1 ranging from about 100 nanometers to about 120 nanometers. An active region 112F is disposed between two planar active regions 112P, and the active regions 112F and 112P are separated by an STI feature 110. In some embodiments, one or more FETs are formed across the planar active regions 112P and the 3D active region 112F.

[0085] Figures 3A to 3C Manufacturing according to some embodiments Figure 2A One of the various stages of the IC structure 100 along Figure 2A The side view of the cross-section cut off by the dashed line BB'. (See example...) Figure 3A As shown, the fin-shaped structure 302 is formed from the substrate 102. The fin-shaped structure 302 can be... Figure 2B One of the fin-shaped structures shown. When fin-shaped structure 302 is formed... Figure 2B The planar active region 112P shown can be protected by a mask. For example... Figure 3A As shown, after forming the fin structure 302, an opening 304 is formed in the fin structure 302. The opening 304 forms multiple segments of the fin structure 302. In other words, the fin structure 302 includes discrete segments in the X direction. The opening 304 can be formed by any suitable process. In some embodiments, a patterned mask layer (not shown) is formed on the fin structure 302, and the pattern of the patterned mask layer is transferred to the fin structure 302. Photolithography and etching processes can be performed to pattern the mask layer and transfer the pattern to the fin structure 302. The fin structure 302 may have a height H1 ranging from about 100 nanometers to about 120 nanometers. The height H1 can be measured from the bottom surface 306 of the opening 304 to the top surface 308 of the fin structure 302. Each opening 304 may be defined by a side surface 310 and a bottom surface 306. The side surface 310 and the bottom surface 306 form an angle A. In some embodiments, angle A is a substantially right angle ranging from about 89 degrees to about 91 degrees.

[0086] In some embodiments, such as Figure 3BAs shown, angle A is an acute or obtuse angle. Angle A can range from about 70 degrees to about 85 degrees or from about 95 degrees to about 120 degrees. Angle A can be controlled by an etching process used to form opening 304. Process conditions such as plasma power and / or bias power can be adjusted to form a predetermined angle A. For example, an opening 304 having a right angle or acute angle (angle A) can be formed by an etching process comprising first process conditions followed by second process conditions. The second process conditions may have a higher plasma power and / or a higher bias power than the first process conditions. In some embodiments, the first process conditions comprise allowing a first etchant to flow into a processing chamber, and the second process conditions comprise allowing a second etchant, different from the first etchant, to flow into the processing chamber.

[0087] In some embodiments, such as Figure 3C As shown, opening 304 includes a first portion 312 and a second portion 314 located below the first portion 312. The first portion 312 may include a substantially constant width W1, while the second portion 314 may include a different width W2. In some embodiments, the different width W2 increases in the direction toward the bottom surface 306. Opening 304 having the first portion 312 and the second portion 314 can be formed by a two-step etching process. For example, the first step includes an isotropic etching process, while the second step includes an isotropic etching process performed after the first step. In some embodiments, a dry etching process is performed first, followed by a wet etching process to form opening 304 having the first portion 312 and the second portion 314. In some embodiments, opening 304 having the first portion 312 and the second portion 314 can be formed by an etching process similar to that used to form opening 304 having a right angle or acute angle A, the etching process including a first process condition followed by a second process condition. In some embodiments, the plasma power and / or bias power of the second process condition is substantially greater than the plasma power and / or bias power of the first process condition. In some embodiments, the first process condition comprises an etchant having a first carbon-fluorine ratio, while the second process condition comprises an etchant having a second carbon-fluorine ratio substantially greater than the first carbon-fluorine ratio.

[0088] Openings 304 with different shapes can have different benefits. For example, an opening 304 having a first portion 312 and a second portion 314 can have a more stable subsequently formed STI feature 330. Figures 6A to 6D ).

[0089] Figures 4A to 4C Manufacturing according to some embodiments Figure 2A Various views of one of the various stages of the IC structure 100. Figure 4A Along IC structure 100 Figure 2AThe image shows a cross-sectional side view taken by the dashed line BB'. After forming the opening 304, a masking layer 316 is deposited in the opening 304 and on the fin structure 302. In some embodiments, a masking layer (not shown) has already been formed on a portion of the fin structure 302, such as on the top surface 308, and the masking layer 316 is deposited on the masking layer. The masking layer 316 may contain any suitable material with a different etch selectivity than the fin structure 302. In some embodiments, the masking layer 316 contains a dielectric material. In some embodiments, the masking layer 316 is a bottom anti-reflective coating (BARC) layer. Figure 4B for Figure 4A A top view of the IC structure 100, and Figure 4C Along IC structure 100 Figure 4A or Figure 4B The side view of the cross section cut by the dashed line CC'.

[0090] In some embodiments, the mask layer 316 may be planarized such that the top surface of the mask layer 316 is substantially flat. Next, a resist layer (not shown) is deposited on the mask layer 316 and patterned. The patterning of the resist layer may include a photolithography process and one or more etching processes. The pattern of the resist layer is then transferred to the mask layer 316, and subsequently to the bottom surface 306 of the fin structure 302. The transfer of the pattern to the mask layer 316 and the bottom surface 306 of the fin structure 302 can be performed by an etching process. The transfer of the pattern to the bottom surface 306 modifies the bottom surface 306, and Figures 5A to 5C The description describes various modified bottom surfaces 306 according to some embodiments.

[0091] Figures 5A to 5C Manufacturing according to some embodiments Figure 4C A cross-sectional side view of one of the various stages of the IC structure 100. For example... Figure 5A As shown, the modified bottom surface 306 of the fin structure 302 includes a plurality of grooves 320, and the grooves 320 define a plurality of fins 322. The depth of the grooves 320 can range from about 5 nanometers to about 20 nanometers, and the height of the fins 322 can range from about 5 nanometers to about 20 nanometers. Figure 5B As shown, in some embodiments, the modified bottom surface 306 includes a plurality of protrusions 326 separated by a plurality of openings 324. The protrusions 326 extend from the bottom surface 306, and each protrusion 326 may have a height ranging from about 5 nanometers to about 20 nanometers. In some embodiments, such as Figure 5C As shown, the modified bottom surface 306 includes a plurality of bumps 328. Each bump 328 may have a height ranging from about 5 nanometers to about 20 nanometers.

[0092] Figures 6A to 6D This is a cross-sectional side view of one of the various stages of manufacturing the IC structure 100 according to some embodiments. For example... Figures 6A to 6C As shown, after modifying the bottom surface 306, an STI feature 330 is formed in the opening 304 on the modified bottom surface 306 of the fin structure 302. The STI feature 330 can be... Figure 1A and Figure 1B The STI feature 110 is shown. By forming the STI feature 330 on the modified bottom surface 306, the breakdown voltage is increased while maintaining a high current flowing through the device. The STI feature 330 can be formed by first depositing dielectric material in the opening 304 and on the fin structure 302, followed by a planarization process to remove the portion of the dielectric material disposed on the fin structure 302. Next, the dielectric material is recessed to form the STI feature 330. Figure 6D STI features 330 formed between segments of fin structure 302 are shown.

[0093] Figures 7A to 7C Manufacturing according to some embodiments Figure 6D A cross-sectional side view of one of the various stages of the IC structure 100. For example... Figure 7A , Figure 7B and Figure 7C As shown, a gate structure 332 is formed above the fin structure 302. The gate structure 332 may contain the same layer as the gate structure 118. However, the gate structure 332 covers the top and side surfaces of the fin structure 302. Similar to the gate structure 118, the gate structure 332 also includes multiple segments. As described above, the multiple segments are for various manufacturing benefits, such as tuning pattern density and improving the uniformity of processes (such as CMP). Some segments may be floating, while others may be connected to power signal lines. In some embodiments, the segment of the gate structure 332 with the largest size on the X-axis is a functional gate structure.

[0094] like Figure 7A , Figure 7B and Figure 7C As shown, the IC structure 100 further includes a source 334 and a drain 336. In some embodiments, Figure 7A , Figure 7B and Figure 7CThe IC structure 100 shown includes two FETs sharing a drain 336. The source 334 and drain 336 may contain the same material as the source 114 and drain 116, and can be formed using the same process as the source 114 and drain 116. As described above, the FET may be an HVFET, and a large current can flow from the source 334 to the drain 336. The large current flows through a portion of the fin structure 302 having a modified bottom surface 306. Due to the modified bottom surface 306, the breakdown voltage of the STI feature 330 is increased while maintaining the large current flowing through it.

[0095] Figure 8 According to some embodiments Figure 7A (or Figure 7B , Figure 7C A top view of the IC structure 100. (e.g.) Figure 8 As shown, the gate structure 332 covers the top and side surfaces of the fin structure 302. STI feature 330 and modified bottom surface 306 ( Figure 5A , Figure 5B , Figure 5C It is located between the source 334 and the drain 336.

[0096] Some embodiments of this disclosure provide an IC structure having one or more HVFET devices and a method of manufacturing the same. As described above, the IC structure includes a fin structure 302 in which one or more openings 304 are formed. The bottom surface 306 of the fin structure 302 at the bottom of each opening 304 includes a groove 320, a protrusion 326, or a bump 328. Various features are implemented in the disclosed IC structure to achieve enhanced performance, including increased breakdown voltage, reduced leakage current, and increased current in the on-state of the STI feature 330. Furthermore, the HVFET devices of the IC structure can be formed in the fin active region or formed with other three-dimensional FET structures, such as nanostructures with multiple vertically stacked channels, such as gate-all-around (GAA) structures, or CFET structures with nFETs and pFETs stacked vertically to each other.

[0097] This embodiment is an IC structure. The IC structure includes a fin-shaped structure disposed above a substrate. The fin-shaped structure includes a first segment and a second segment, and a bottom surface located between the first segment and the second segment. The bottom surface includes a plurality of grooves. The IC structure further includes a dielectric material disposed between the first segment and the second segment of the fin-shaped structure, and the dielectric material is disposed on the bottom surface and in the plurality of grooves. The IC structure further includes a gate structure disposed above the first segment of the fin-shaped structure, and the gate structure covers the top surface and side surface of the first segment of the fin-shaped structure.

[0098] In some embodiments, the IC structure further includes a source electrode disposed in a first segment of the fin structure and a drain electrode disposed in a second segment of the fin structure. In some embodiments, a bottom surface and dielectric material are disposed between the source and the drain electrode. In some embodiments, the fin structure has a height ranging from about 100 nanometers to about 120 nanometers. In some embodiments, the recesses define a plurality of fins, and each fin has a height ranging from about 5 nanometers to about 20 nanometers. In some embodiments, the gate structure includes a first segment, a second segment, a third segment, and a fourth segment, with the first and second segments of the gate structure disposed above the first segment of the fin structure, and the third and fourth segments of the gate structure disposed above the second segment of the fin structure. In some embodiments, viewed from a top view, the source electrode is disposed between the first and second segments of the gate structure, and the drain electrode is disposed between the third and fourth segments of the gate structure.

[0099] Another embodiment is an IC structure. The IC structure includes a first field-effect transistor (FET) disposed above a substrate. The first FET includes a first source, a drain, a first gate structure disposed between the first source and the drain, and a first shallow trench isolation (STI) feature disposed between the first source and the drain. The first STI feature is disposed on a first bottom surface of the substrate, and the first bottom surface includes a first plurality of bumps. The IC structure further includes a second FET disposed above the substrate. The second FET includes a second source, a drain, a second gate structure disposed between the second source and the drain, and a second STI feature disposed between the second source and the drain.

[0100] In some embodiments, a first gate structure is disposed above this segment of the fin structure. In some embodiments, this segment of the fin structure has a height ranging from about 100 nanometers to about 120 nanometers. In some embodiments, each of the first plurality of bumps has a height ranging from about 5 nanometers to about 20 nanometers. In some embodiments, this segment of the fin structure has a side surface, and an angle is formed between the side surface and the first bottom surface. In some embodiments, the angle is an acute angle. In some embodiments, the angle is an obtuse angle. In some embodiments, a second shallow trench isolation feature is disposed on a second bottom surface of the substrate, and the second bottom surface includes a second plurality of bumps.

[0101] Another embodiment is a method for manufacturing an integrated circuit structure. The method includes forming a fin-shaped structure from a substrate; and forming a plurality of openings in the fin-shaped structure. Each opening has a bottom surface. The method further includes depositing a mask layer in the openings; patterning the mask layer; transferring the pattern of the mask layer to the bottom surface to modify the bottom surface in each opening; depositing a dielectric material in the openings and on the modified bottom surface in each opening; and forming a gate structure covering the top surface and a plurality of side surfaces of the fin-shaped structure.

[0102] In some embodiments, transferring the pattern of the mask layer to the bottom surface includes forming a plurality of grooves in the bottom surface. In some embodiments, transferring the pattern of the mask layer to the bottom surface includes forming a plurality of protrusions in the bottom surface. In some embodiments, transferring the pattern of the mask layer to the bottom surface includes forming a plurality of bumps in the bottom surface. In some embodiments, each opening includes a first portion having a first width and a second portion located below the first portion, the second portion having a second width substantially greater than the first width.

[0103] Another embodiment is an integrated circuit structure including a fin structure, a dielectric material, and a gate structure. The fin structure is disposed above a substrate, wherein the fin structure includes a first segment and a second segment, and a bottom surface located between the first segment and the second segment. The dielectric material is disposed between the first and second segments of the fin structure, wherein the dielectric material is disposed on the bottom surface. The gate structure is disposed above the first segment of the fin structure, wherein the gate structure covers the top surface and a plurality of side surfaces of the first segment of the fin structure, wherein one of these side surfaces forms an acute or obtuse angle with the bottom surface.

[0104] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit structure, characterized in that, include: A fin-shaped structure is disposed above a substrate, wherein the fin-shaped structure includes a first segment and a second segment and a bottom surface located between the first segment and the second segment, and the bottom surface includes a plurality of grooves; A dielectric material is disposed between the first and second segments of the fin structure, wherein the dielectric material is disposed on the bottom surface and in the plurality of grooves; and A gate structure is disposed above the first segment of the fin structure, wherein the gate structure covers a top surface and a plurality of side surfaces of the first segment of the fin structure.

2. The integrated circuit structure as claimed in claim 1, further comprising a source electrode disposed in the first segment of the fin structure and a drain electrode disposed in the second segment of the fin structure.

3. The integrated circuit structure of claim 1, wherein the fin structure has a height ranging from 100 nanometers to 120 nanometers.

4. The integrated circuit structure as claimed in claim 1, wherein the gate structure includes a first segment, a second segment, a third segment and a fourth segment, the first segment and the second segment of the gate structure are disposed above the first segment of the fin structure, and the third segment and the fourth segment of the gate structure are disposed above the second segment of the fin structure.

5. An integrated circuit structure, characterized in that, include: A first field-effect transistor is disposed above a substrate, the first field-effect transistor comprising: The first source pole; One leak pole; A first gate structure is disposed above a segment of a fin-shaped structure above the substrate, and between the first source and the drain, wherein the first gate structure covers a top surface and a plurality of side surfaces of the segment of the fin-shaped structure; and A first shallow trench isolation feature is disposed between the first source and the drain, wherein the first shallow trench isolation feature is disposed on a first bottom surface of the substrate, and the first bottom surface includes... One first multiple bumps; and A second field-effect transistor is disposed above the substrate, the second field-effect transistor comprising: A second source pole; The drain electrode; A second gate structure is disposed between the second source and the drain; and A second shallow trench isolation feature is disposed between the second source and the drain.

6. The integrated circuit structure of claim 5, wherein the second shallow trench isolation feature is disposed on a second bottom surface of the substrate, and the second bottom surface includes a second plurality of bumps.

7. The integrated circuit structure of claim 5, wherein the segment of the fin structure has a height ranging from 100 nanometers to 120 nanometers.

8. The integrated circuit structure of claim 7, wherein each of the first plurality of bumps has a height ranging from 5 nanometers to 20 nanometers.

9. The integrated circuit structure of claim 7, wherein the segment of the fin structure has a side surface and forms an angle between the side surface and the first bottom surface.

10. An integrated circuit structure, characterized in that, include: A fin-shaped structure is disposed above a substrate, wherein the fin-shaped structure includes a first segment and a second segment and a bottom surface located between the first segment and the second segment; A dielectric material is disposed between the first segment and the second segment of the fin structure, wherein the dielectric material is disposed on the bottom surface; and A gate structure is disposed above the first segment of the fin structure, wherein the gate structure covers a top surface and a plurality of side surfaces of the first segment of the fin structure, wherein one of the plurality of side surfaces forms an acute angle or an obtuse angle with the bottom surface.

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