Battery simulation circuit

Abstract

The utility model discloses a battery analog circuit which comprises a BMS (battery management system), a digital-to-analog converter DAC1, a digital-to-analog converter DAC2, a digital-to-analog converter DAC3, an operational amplifier APM1, an operational amplifier APM2, an operational amplifier APM3, an operational amplifier APM4, an operational amplifier APM5, an operational amplifier APM6, an MOS (metal oxide semiconductor) tube Q1 and an MOS tube Q2. The digital-to-analog converter DAC1 is used for controlling output voltage, the digital-to-analog converter DAC2 and the digital-to-analog converter DAC3 are used for controlling discharge current, and two ends of the BMS are output electrodes of the equipment. According to the utility model, a double-MOS tube structure is adopted, one MOS tube is used as a charging control circuit, the other MOS tube is used as a discharging control circuit, voltage and current can be controlled, the requirements of high voltage precision, current charging and discharging switching and large current magnitude in a BMS test are met, and the BMS test circuit has the advantages of high precision and high-speed response.

Description

TECHNICAL FIELD

[0001] The utility model relates to battery simulation circuit technical field, especially in a kind of battery simulation circuit that can simulate battery charging and discharging. BACKGROUND

[0002] Current battery simulation scheme is mostly using a DC power supply as the battery pack voltage supply, after connecting multiple same resistors in series to the positive and negative poles of power supply, the voltage on each cell is simulated by resistance voltage division. The current scheme has the following defects:

[0003] 1. The voltage of all cells is composed of total voltage and fixed resistance voltage division, the total voltage is adjusted, and all cells are adjusted together, which cannot realize the state of single cell adjustment change alone;

[0004] 2. The control precision is not high, limited by total power supply precision and voltage division resistance;

[0005] 3. Since it is resistance voltage division, BMS cannot get a large equalization current when doing voltage equalization, and can only simulate voltage;

[0006] 4. Current active equalization BMS scheme has appeared, as the current method cannot be charged, so the state of battery charging cannot be simulated, and active equalization BMS cannot be tested. INVENTION CONTENTS

[0007] The main purpose of the utility model is to provide a kind of battery simulation circuit that can simulate battery charging and discharging, to meet the demand of voltage high precision, current charging and discharging switching and large current in BMS test.

[0008] To achieve the above purpose, the utility model provides a kind of battery simulation circuit, including: BMS, digital-to-analog converter DAC1, digital-to-analog converter DAC2, digital-to-analog converter DAC3, operational amplifier APM1, operational amplifier APM2, operational amplifier APM3, operational amplifier APM4, operational amplifier APM5, operational amplifier APM6, MOS tube Q1 and MOS tube Q2.

[0009] The digital-to-analog converter DAC1 is used to control output voltage, the digital-to-analog converter DAC2 and digital-to-analog converter DAC3 are used to control discharge current, and the BMS two ends are the output pole of equipment.

[0010] The operational amplifier APM1, operational amplifier APM2, operational amplifier APM3 and the MOS tube Q1 constitute discharge loop, the operational amplifier APM2, operational amplifier APM3 double loop competition, simulate the discharge state of battery.

[0011] The operational amplifier APM1, the operational amplifier APM4, the operational amplifier APM5, the operational amplifier APM6 and the MOS tube Q2 constitute a charging loop, and the operational amplifier APM5 and the operational amplifier APM6 compete in a double loop to simulate the charging state of the battery.

[0012] The utility model further technical scheme is still including operational amplifier APM7, operational amplifier APM8 and sampling resistance R3.

[0013] The digital-to-analog converter DAC1 is connected to the pin 1 of the operational amplifier APM1, the pin 2 of the operational amplifier APM1 is connected to the pin 3 of the operational amplifier APM8, the pin 3 of the operational amplifier APM1 is connected to the pin 1 of the operational amplifier APM2 and the pin 1 of the operational amplifier APM6, the pin 3 of the operational amplifier APM2 is connected to the pin 3 of the operational amplifier APM3 and the G pole of the MOS tube Q1, the digital-to-analog converter DAC2 is connected to the pin 1 of the operational amplifier APM3, the pin 2 of the operational amplifier APM3 is connected to the pin 2 of the operational amplifier APM5 and the pin 3 of the operational amplifier APM7, the digital-to-analog converter DAC3 is connected to the operational amplifier APM4, the pin 3 of the operational amplifier APM4 is connected to the pin 1 of the operational amplifier APM5, the pin 3 of the operational amplifier APM5 is connected to the G pole of the MOS tube Q2 and the pin 2 of the operational amplifier APM6, the D pole of the MOS tube Q1 is connected to the positive pole of the power supply, the S pole of the MOS tube Q1 is connected to the S pole of the MOS tube Q2, one end of the BMS and the pin 1 of the operational amplifier APM8, the D pole of the MOS tube Q2 is connected to one end of the sampling resistance R3 and the pin 2 of the operational amplifier APM7, the pin 1 of the operational amplifier APM7 is connected to the other end of the sampling resistance R3, the other end of the BMS and the pin 2 of the operational amplifier APM8.

[0014] The utility model further technical scheme is still including diode D1, diode D2, diode D3, diode D4, resistance R1, resistance R2, resistance R4 and resistance R5.

[0015] The negative electrode of the diode D1 is connected to pin 3 of the operational amplifier APM2, the positive electrode of the diode D1 is connected to pin 2 of the operational amplifier APM2, the positive electrode of the diode D2, the G electrode of the MOS tube Q1 and one end of the resistor R1, the negative electrode of the diode D2 is connected to pin 3 of the operational amplifier APM3, the other end of the resistor R1 is connected to VCC, the positive electrode of the diode D3 is connected to pin 3 of the operational amplifier APM5, the negative electrode of the diode D3 is connected to one end of the resistor R2, the G electrode of the MOS tube Q2, the negative electrode of the diode D4 and pin 2 of the operational amplifier APM6, the other end of the resistor R2 is connected to VEE, the positive electrode of the diode D4 is connected to pin 3 of the operational amplifier APM6, one end of the resistor R4 is connected to the digital-to-analog converter DAC3, the other end of the resistor R4 is connected to pin 2 of the operational amplifier APM4 and one end of the resistor R5, the other end of the resistor R5 is connected to pin 3 of the operational amplifier APM4 and pin 1 of the operational amplifier APM5.

[0016] The further technical scheme of the utility model further relates to a plurality of MOS tubes connected in parallel with the MOS tube Q1 and a plurality of MOS tubes connected in parallel with the MOS tube Q2.

[0017] The utility model discloses battery simulation circuit's beneficial effect is:

[0018] The utility model discloses battery simulation circuit's beneficial effect is: BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to make the technical scheme in the embodiment of the utility model or prior art clearer, the following will briefly introduce the drawing needed to be used in the embodiment or prior art description, and obviously, the drawing in the following description is only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to the structure shown in these drawings without paying creative labor.

[0020] Figure 1 It is the circuit structure schematic diagram of the preferable embodiment of the utility model battery simulation circuit.

[0021] The realization, functional characteristics and advantages of the utility model will be further explained by combining with the embodiment and referring to the drawings. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the utility model will be clearly and completely described in connection with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the utility model.

[0023] The utility model provides a kind of battery simulation circuit in BMS test field can simulate battery charging, discharging, static and various working conditions, and can automatically switch, can simulate a piece of battery or multiple battery series even can simulate a battery pack, it can be applied to the test link of BMS, simulates the various states of battery, test whether the various working conditions of BMS are within design range, solve the test demand under the various schemes of current BMS.Each battery can be independently adjusted, and the precision is very high.Charging and discharging current can be achieved in a very wide range by means of parallel power circuit, and the utility model can be charged and discharged, so it can be applied to passive balancing BMS and active balancing BMS system test.

[0024] The technical scheme adopted by the battery simulation circuit of the utility model is mainly to adopt double MOS tube structure, one as charging control circuit, the other as discharging control circuit, which can control voltage and current, solve the demand of high precision voltage, charging and discharging switching and large current in BMS test.

[0025] Specifically, as shown in Figure 1 The battery simulation circuit preferred embodiment of the utility model includes: BMS, digital-to-analog converter DAC1, digital-to-analog converter DAC2, digital-to-analog converter DAC3, operational amplifier APM1, operational amplifier APM2, operational amplifier APM3, operational amplifier APM4, operational amplifier APM5, operational amplifier APM6, MOS tube Q1 and MOS tube Q2.

[0026] The digital-to-analog converter DAC1 is used to control output voltage, and the digital-to-analog converter DAC2 and the digital-to-analog converter DAC3 are used to control discharging current, and the BMS two ends are the output pole of equipment.

[0027] The operational amplifier APM1, the operational amplifier APM2, the operational amplifier APM3 and the MOS tube Q1 constitute a discharging loop, and the operational amplifier APM2 and the operational amplifier APM3 compete in double loop, simulate the discharging state of battery.

[0028] The operational amplifier APM1, the operational amplifier APM4, the operational amplifier APM5, the operational amplifier APM6 and the MOS tube Q2 constitute a charging circuit, the operational amplifier APM5 and the operational amplifier APM6 compete in double loop, and simulate the charging state of the battery.

[0029] Further, in the embodiment, the battery simulation circuit further comprises an operational amplifier APM7, an operational amplifier APM8 and a sampling resistor R3.

[0030] The digital-to-analog converter DAC1 is connected to pin 1 of the operational amplifier APM1, pin 2 of the operational amplifier APM1 is connected to pin 3 of the operational amplifier APM8, pin 3 of the operational amplifier APM1 is connected to pin 1 of the operational amplifier APM2 and pin 1 of the operational amplifier APM6, pin 3 of the operational amplifier APM2 is connected to pin 3 of the operational amplifier APM3 and the G pole of the MOS tube Q1; the digital-to-analog converter DAC2 is connected to pin 1 of the operational amplifier APM3, pin 2 of the operational amplifier APM3 is connected to pin 2 of the operational amplifier APM5 and pin 3 of the operational amplifier APM7; the digital-to-analog converter DAC3 is connected to the operational amplifier APM4, pin 3 of the operational amplifier APM4 is connected to pin 1 of the operational amplifier APM5, pin 3 of the operational amplifier APM5 is connected to the G pole of the MOS tube Q2 and pin 2 of the operational amplifier APM6, the D pole of the MOS tube Q1 is connected to the positive pole of the power supply, the S pole of the MOS tube Q1 is connected to the S pole of the MOS tube Q2, one end of the BMS and pin 1 of the operational amplifier APM8, the D pole of the MOS tube Q2 is connected to one end of the sampling resistor R3 and pin 2 of the operational amplifier APM7, pin 1 of the operational amplifier APM7 is connected to the other end of the sampling resistor R3, the other end of the BMS and pin 2 of the operational amplifier APM8.

[0031] Further, in the embodiment, the battery simulation circuit further comprises a diode D1, a diode D2, a diode D3, a diode D4, a resistor R1, a resistor R2, a resistor R4 and a resistor R5.

[0032] The negative electrode of the diode D1 is connected to pin 3 of the operational amplifier APM2, the positive electrode of the diode D1 is connected to pin 2 of the operational amplifier APM2, the positive electrode of the diode D2, the G electrode of the MOS tube Q1 and one end of the resistor R1, the negative electrode of the diode D2 is connected to pin 3 of the operational amplifier APM3, the other end of the resistor R1 is connected to VCC, the positive electrode of the diode D3 is connected to pin 3 of the operational amplifier APM5, the negative electrode of the diode D3 is connected to one end of the resistor R2, the G electrode of the MOS tube Q2, the negative electrode of the diode D4 and pin 2 of the operational amplifier APM6, the other end of the resistor R2 is connected to VEE, the positive electrode of the diode D4 is connected to pin 3 of the operational amplifier APM6, one end of the resistor R4 is connected to the digital-to-analog converter DAC3, the other end of the resistor R4 is connected to pin 2 of the operational amplifier APM4 and one end of the resistor R5, the other end of the resistor R5 is connected to pin 3 of the operational amplifier APM4 and pin 1 of the operational amplifier APM5.

[0033] Further, in the embodiment, the battery simulation circuit further comprises a plurality of MOS tubes connected in parallel with the MOS tube Q1, and a plurality of MOS tubes connected in parallel with the MOS tube Q2.

[0034] The working principle of the battery simulation circuit will be described in detail below. Figure 1 The working principle of the battery simulation circuit will be described in detail below.

[0035] Figure 1 The digital-to-analog converter DAC1 is used to control the output voltage, the digital-to-analog converter DAC2 is used to control the discharge current, the digital-to-analog converter DAC3 is used to control the discharge current, and the BMS is connected between the output poles of the device. The operational amplifier APM1, the operational amplifier APM2, the operational amplifier APM3 and the MOS tube Q1 form a discharge loop as a whole, and the operational amplifier APM2 and the operational amplifier APM3 compete in a double loop, so that the discharge state of the battery can be simulated. The operational amplifier APM1, the operational amplifier APM4, the operational amplifier APM5, the operational amplifier APM6 and the MOS tube Q2 form a charging loop as a whole, and the operational amplifier APM5 and the operational amplifier APM6 compete in a double loop, so that the charging state of the battery can be simulated. The upper half part is equivalent to a program-controlled power supply, and the lower half part is equivalent to a program-controlled electronic load. The program-controlled power supply is responsible for simulating the discharge state of the battery, and the program-controlled electronic load is responsible for simulating the charging state of the battery.

[0036] In the discharging state, the operational amplifier APM8 collects the output stage voltage, compares it with the digital-to-analog converter DAC1 through the operational amplifier APM1, and controls the linear region of the MOS tube Q1 through the operational amplifier APM2 to realize the control of the output voltage. The current signal is converted into a voltage signal through a sampling resistor, and is converted by the operational amplifier APM7 and compared with the digital-to-analog converter DAC2 through the operational amplifier APM3. The operational amplifier APM2 and the operational amplifier APM3 are in a competitive relationship, when the discharging current does not reach the setting current of the digital-to-analog converter DAC2, the output is controlled by the MOS tube Q1 of the operational amplifier APM2, and the whole works in the voltage control loop, and the output is completely determined by the digital-to-analog converter DAC1. When the discharging current increases to the setting current of the digital-to-analog converter DAC2, the operational amplifier APM3 works, the operational amplifier APM2 exits, and the whole works in the current loop, effectively controlling the output current.

[0037] In the charging state, the operational amplifier APM8 collects the output stage voltage, compares it with the digital-to-analog converter DAC1 through the operational amplifier APM1, and controls the linear region of the MOS tube Q2 through the operational amplifier APM6 to realize the control of the output voltage. The current signal is converted into a voltage signal through a sampling resistor, and is converted by the operational amplifier APM7 and compared with the signal inverted by the operational amplifier APM4 through the operational amplifier APM5 and the digital-to-analog converter DAC3. The operational amplifier APM5 and the operational amplifier APM6 are in a competitive relationship, when the discharging current does not reach the setting current of the digital-to-analog converter DAC3, the output is controlled by the MOS tube Q2 of the operational amplifier APM6, and the whole works in the voltage control loop, and the output is completely determined by the digital-to-analog converter DAC1. When the discharging current increases to the setting current of the digital-to-analog converter DAC3, the operational amplifier APM5 works, the operational amplifier APM6 exits, and the whole works in the current loop, effectively controlling the output current.

[0038] The MOS tube Q1 is an NMOS and the MOS tube Q2 is a PMOS, and only one of them works at the same time. The whole system automatically switches to work in the MOS tube Q1 or the MOS tube Q2 after comparing the voltage of the output electrode with the digital-to-analog converter DAC1, so that the analog battery determines whether to charge or discharge according to whether the positive and negative electrodes are filled with current or absorb current, and the whole switching is seamless.

[0039] The MOS tube Q1 can be connected in parallel to the MOS tube Q1n, and the MOS tube Q2 can be connected in parallel to the MOS tube Q2n, and a plurality of MOS tubes Q1 and MOS tubes Q2 in parallel can realize larger current and larger power output, and theoretically can be infinitely expanded.

[0040] The battery simulation circuit has the following beneficial effects:

[0041] The utility model discloses through above-mentioned technical scheme, can apply on the test equipment of BMS, simulates various working conditions of battery, adopts double MOS pipe structure, one is as charging control circuit, and the other is as discharge control circuit, can control voltage, and can control current, solves the demand of voltage high accuracy, current charge-discharge switching and current amount in BMS test, has the advantages of high accuracy, high speed response.

[0042] The above-mentioned is only the preferred embodiment of the utility model, and does not limit the patent range of the utility model, and the equivalent structure transformation of the utility model specification and the attached drawing contents is made under the concept of the utility model, or direct / indirect application in other related technical fields are included in the patent protection range of the utility model.

Claims

1. A battery simulation circuit, characterized by, Comprise: BMS, digital-to-analog converter DAC1, digital-to-analog converter DAC2, digital-to-analog converter DAC3, operational amplifier APM1, operational amplifier APM2, operational amplifier APM3, operational amplifier APM4, operational amplifier APM5, operational amplifier APM6, MOS tube Q1 and MOS tube Q2; The digital-to-analog converter DAC1 is used to control the output voltage, the digital-to-analog converter DAC2 and the digital-to-analog converter DAC3 are used to control the discharge current, and the BMS is connected between the output poles of the device; The operational amplifier APM1, the operational amplifier APM2, the operational amplifier APM3 and the MOS tube Q1 constitute a discharge loop, and the operational amplifier APM2 and the operational amplifier APM3 compete in double loops to simulate the discharge state of the battery; The operational amplifier APM1, the operational amplifier APM4, the operational amplifier APM5, the operational amplifier APM6 and the MOS tube Q2 constitute a charging loop, and the operational amplifier APM5 and the operational amplifier APM6 compete in double loops to simulate the charging state of the battery.

2. The battery emulation circuit of claim 1, wherein, Further comprising operational amplifier APM7, operational amplifier APM8 and sampling resistor R3; The digital-to-analog converter DAC1 is connected to pin 1 of the operational amplifier APM1, pin 2 of the operational amplifier APM1 is connected to pin 3 of the operational amplifier APM8, pin 3 of the operational amplifier APM1 is connected to pin 1 of the operational amplifier APM2 and pin 1 of the operational amplifier APM6, pin 3 of the operational amplifier APM2 is connected to pin 3 of the operational amplifier APM3 and the G pole of the MOS tube Q1; the digital-to-analog converter DAC2 is connected to pin 1 of the operational amplifier APM3, pin 2 of the operational amplifier APM3 is connected to pin 2 of the operational amplifier APM5 and pin 3 of the operational amplifier APM7; the digital-to-analog converter DAC3 is connected to the operational amplifier APM4, pin 3 of the operational amplifier APM4 is connected to pin 1 of the operational amplifier APM5, pin 3 of the operational amplifier APM5 is connected to the G pole of the MOS tube Q2 and pin 2 of the operational amplifier APM6, the D pole of the MOS tube Q1 is connected to the positive pole of the power supply, the S pole of the MOS tube Q1 is connected to the S pole of the MOS tube Q2, one end of the BMS and pin 1 of the operational amplifier APM8, the D pole of the MOS tube Q2 is connected to one end of the sampling resistor R3, pin 2 of the operational amplifier APM7, pin 1 of the operational amplifier APM7 is connected to the other end of the sampling resistor R3, the other end of the BMS and pin 2 of the operational amplifier APM8.

3. The battery emulation circuit of claim 2, wherein, Further comprising diode D1, diode D2, diode D3, diode D4, resistor R1, resistor R2, resistor R4 and resistor R5; The negative pole of the diode D1 is connected to pin 3 of the operational amplifier APM2, the positive pole of the diode D1 is connected to pin 2 of the operational amplifier APM2, the positive pole of the diode D2, the G pole of the MOS tube Q1, one end of the resistor R1, the negative pole of the diode D2 is connected to pin 3 of the operational amplifier APM3, the other end of the resistor R1 is connected to VCC, the positive pole of the diode D3 is connected to pin 3 of the operational amplifier APM5, the negative pole of the diode D3 is connected to one end of the resistor R2, the G pole of the MOS tube Q2, the negative pole of the diode D4, pin 2 of the operational amplifier APM6, the other end of the resistor R2 is connected to VEE, the positive pole of the diode D4 is connected to pin 3 of the operational amplifier APM6; one end of the resistor R4 is connected to the digital-to-analog converter DAC3, the other end of the resistor R4 is connected to pin 2 of the operational amplifier APM4, one end of the resistor R5, the other end of the resistor R5 is connected to pin 3 of the operational amplifier APM4, pin 1 of the operational amplifier APM5.

4. The battery emulation circuit of claim 3, wherein, Also included are a plurality of MOS tubes in parallel with the MOS tube Q1, and a plurality of MOS tubes in parallel with the MOS tube Q2. Also included are a plurality of MOS tubes in parallel with the MOS tube Q1, and a plurality of MOS tubes in parallel with the MOS tube Q2.

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