Chip insulation testing device

Abstract

The utility model provides a chip insulation test device. The chip insulation test device comprises test probes distributed in an array; wherein the metal bumps of the to-be-detected chip are arranged on the chip protection layer, and the to-be-detected chip comprises a support column located on the chip protection layer and a solder cap located at the end part of the support column; the test probe is provided with an open end, and the open end of the test probe is used for being in contact conduction with the support column to realize transmission of a test signal; the outer side of the test probe is provided with an insulation positioning layer, and the insulation positioning layer abuts against the chip protection layer and is used for insulating and positioning the contact between the test probe and the support column. According to the utility model, the related test of the chip can be completed under the condition that the solder cap is not damaged.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip detection technical field more specifically, relate to a chip insulation testing arrangement. BACKGROUND

[0002] In the field of semiconductor chip stacking technology, before the chip is formed or leaves the factory, its related performance needs to be tested, so as to realize quality detection, grading and defective product screening of the chip. At present, there are various ways of chip stacking, such as HBM, Wide-IO or HMC, etc. When testing such chips, external probes need to be in contact with the metal bumps on the chip, so as to realize the transmission of test signals and test results.

[0003] However, due to the small size and fragility of each metal bump on the chip, if the existing probe is used to directly test the metal bump, the solder end of the metal bump will be damaged, which will affect the subsequent bonding process and chip performance, and affect the product yield.

[0004] Therefore, there is an urgent need for a chip testing scheme that can realize the conduction of the chip and the test signal while preventing the solder end of the metal bump from being damaged and affecting the performance of the chip. SUMMARY

[0005] In view of the above problems, the purpose of the utility model is to provide a chip insulation testing arrangement to solve the problem that the existing chip testing scheme will damage the solder end of the chip and affect the performance of the chip.

[0006] The chip insulation testing arrangement provided by the utility model comprises: test probes arranged in an array; wherein the metal bumps of the chip to be tested are arranged on a chip protection layer, including support columns on the chip protection layer and solder caps at the end of the support columns; the test probe has an open end, the open end of the test probe is used to contact and conduct with the support column, and the transmission of test signals is realized; an insulation positioning layer is arranged on the outside of the test probe, the insulation positioning layer abuts against the chip protection layer, and is used to insulate and position the contact between the test probe and the support column.

[0007] In addition, the optional technical scheme further comprises a probe support for fixing the test probe and a driving device for driving the movement of the probe support; wherein the driving device is used to drive the test probe to contact and conduct with the metal bump at the corresponding position through the probe support.

[0008] In addition, the optional technical scheme is that the probe support is provided with a plurality of probe supports, and the probe support and the test probe are correspondingly arranged; and the insulation positioning layer is arranged on the outside of each test probe.

[0009] In addition, the probe support is provided with one, and the test probes are arranged in an array on the probe support; and the insulating positioning layer is arranged outside the edge of the probe support.

[0010] In addition, the insulating positioning layer is in a plate structure or a columnar structure.

[0011] In addition, the length of the insulating positioning layer in a direction parallel to the chip protection layer is not less than the length of the test probe.

[0012] In addition, a positioning structure is arranged on the chip protection layer, and the lower end of the insulating positioning layer is limited in the positioning structure when the insulating positioning layer abuts against the chip protection layer.

[0013] In addition, the test probe has a deformable inner cavity; and the opening end of the test probe is deformed inward to contact the support column and conduct when a preset condition is met, and the solder cap is avoided in the inner cavity of the test probe.

[0014] In addition, the test probe is a memory metal piece, and the preset condition is a preset temperature condition.

[0015] In addition, a PCB is arranged on the probe support, the test probe is connected with an external test system through the PCB, and the test system is used for testing the chip to be detected.

[0016] By using the chip insulating test device, the test probe is arranged as a deformable cavity structure with an opening end, so that the opening end of the test probe can contact the support column and conduct when a preset condition is met, and then the support column is used for realizing the conduction between the test probe and the metal bump, the insulating positioning layer is arranged outside the test probe, so as to isolate the adjacent test probes and realize the accurate positioning between the test probe and the chip to be detected, improve the detection accuracy, avoid the direct contact between the test probe and the solder cap, ensure the integrity of the solder cap, and avoid the influence of the subsequent process and performance caused by the damage of the solder cap.

[0017] To achieve the above and related objects, one or more aspects of the present application include features that will be explained in detail below. The following description and the drawings detail certain illustrative aspects of the present application. However, these aspects indicate only some of the ways in which the principles of the present application can be employed. In addition, the present application is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF DRAWINGS

[0018] Other objects and advantages of the present application can be more fully understood in view of the following detailed description together with the drawings, in which:

[0019] Figure 1 FIG. 1 is a structural schematic diagram of a chip insulation testing device according to an embodiment of the present application in a first state;

[0020] Figure 2 FIG. 2 is a structural schematic diagram of the chip insulation testing device according to the embodiment of the present application in a second state;

[0021] Figure 3 FIG. 3 is a bottom view of the chip insulation testing device according to the embodiment of the present application;

[0022] Figure 4 FIG. 4 is a structural schematic diagram of a chip insulation testing device according to another embodiment of the present application;

[0023] Figure 5 FIG. 5 is an array distribution diagram of the chip insulation testing device according to the embodiment of the present application;

[0024] Figure 6 FIG. 6 is an array distribution top view of the chip insulation testing device according to the embodiment of the present application.

[0025] The reference signs therein include: a testing probe 1, a base part 11, an inclined side arm 12, an open end 13, a metal bump 2, a solder cap 21, a support column 22, a chip protection layer 3, an insulation positioning layer 4, and a connecting part 5.

[0026] The same reference signs in all the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0027] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It can be obvious, however, that such embodiment(s) can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

[0028] In the description of the utility model, it is understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.

[0029] Those skilled in the art can understand that the singular forms "a", "an" and "the" used herein include plural forms unless specifically stated otherwise. It should be further understood that the use of the term "include" in the description of the utility model herein indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that the term "and / or" used herein includes any one of the associated listed items and all combinations of the associated listed items.

[0030] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art to which the utility model belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with those in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless otherwise defined.

[0031] To describe the chip insulation testing device in the utility model in detail, the specific embodiments of the utility model will be described in detail below in combination with the drawings.

[0032] Figures 1 to 6 The overall or partial schematic structure of the chip insulation testing device according to the embodiments of the utility model is shown from different angles respectively.

[0033] As Figures 1 to 6As shown in the drawings, the chip insulation testing device comprises test probes 1 arranged in an array, and metal bumps 2 of a chip to be tested are arranged on a chip protection layer 3; wherein the metal bumps 2 of the chip to be tested comprise support columns 22 arranged on the chip protection layer 3 and solder caps 21 located at end portions of the support columns 22, and the material of the support columns 22 is slightly harder than that of the solder caps 21 in a normal case, for example, the support columns 22 can be made of copper which is not easy to be damaged compared with the solder caps 21; in order to avoid direct contact between the conventional test probes 1 and the solder caps 21, each test probe 1 in the embodiment of the utility model is a deformable cavity structure with an open end 13, the open end of the test probe 1 is used for contacting and conducting with the support column 22 to realize transmission of a test signal; an insulation positioning layer 4 is arranged on the outside of the test probe 1, the insulation positioning layer 4 abuts against the chip protection layer 3 and is used for insulating and positioning the contact between the test probe 1 and the support column 22.

[0034] Specifically, the chip insulation testing device further comprises a probe support (not shown in the drawings) for fixing the test probe 1, a driving device (not shown in the drawings) for driving the probe support or the chip to be tested to move, and the test probe 1 is arranged on the probe support; the test probe 1 can comprise a memory metal piece or a memory metal and alloy piece, and the proportion of the alloy and the memory metal can be flexibly set according to the deformation requirement of the test probe, and it can be known that, according to the characteristics of the memory metal, the open end 13 of the test probe 1 can be in contact and conduction with the support column 22 when a preset condition is met, so that the metal bump 2 to be tested and the test probe 1 realize signal transmission through the support column 22, that is, the test signal is transmitted through the support column 22, and the integrity of the solder cap 21 at the end portion is ensured.

[0035] Specifically, the above-mentioned preset condition can be set as a preset temperature condition, so that the memory metal is in different shapes at different temperatures, and then the connection or disconnection of the test probe 1 and the metal bump 2 is completed; wherein when in a first preset temperature range, the open end 13 of the test probe 1 is opened, at this time, the test probe 1 can be driven by the driving device to move to the outside of the support column 22, so that the whole metal bump 2 is located in the internal cavity of the test probe 1; the external environment temperature is changed, so that when in a second preset temperature range, the open end 13 of the test probe 1 is retracted and clamps the support column 22, at this time, the solder cap 21 is avoided in the internal cavity of the test probe 1, so that the solder cap 21 structure is effectively protected under the condition that the metal bump 2 and the test probe 1 are in contact and conduction.

[0036] Wherein, the temperature range and shape type of the memory metal can be diversified through material design and processing technology. The material type of the memory metal can include:

[0037] 1. Low temperature range material: capable of working at temperatures as low as -100°C. For example, copper-based alloys (such as Cu-Zn-Al) can exhibit good shape memory effect in low temperature environments;

[0038] 2. Normal temperature range material: for example, nickel-titanium alloy (Nitinol) generally exhibits the best shape memory effect between -50°C and 100°C;

[0039] 3. High temperature range: nickel-titanium alloy with the addition of hafnium (Hf) or aluminum (Al) can raise the phase transition temperature to 200°C or even higher. For example, the phase transition temperature of Ni-Ti-Hf alloy can reach 200°C to 400°C.

[0040] 4. Ultra-high temperature range: iron-based alloys (such as Fe-Mn-Si) also exhibit shape memory effect in the temperature range of 200°C to 400°C, such materials can be suitable for extremely high temperature environments.

[0041] In one specific embodiment of the present application, the memory metal uses a metal material in the normal temperature range (for example, nickel-titanium alloy), at this time the first preset temperature can be set to normal temperature, the range is 0-70°C; the range of the second preset temperature is greater than 70°C, the first preset temperature can also be preferably set to normal temperature, for example, 0-40°C, which can ensure that the opening end 13 of the test probe 1 is in an open state at normal temperature, and the size of the opening end 13 after opening is greater than the maximum size of the metal bump 2, so that the metal bump 2 can be deeply inserted into the internal cavity of the test probe 1, and in the test process, the test probe 1 is heated by temperature control or the ambient temperature is changed, so that the ambient temperature reaches the second preset temperature range required for the deformation of the test probe 1, at this time the opening end 13 of the test probe 1 is deformed by shrinking inward, until it is attached to the supporting column 22.

[0042] In one specific embodiment of the present application, the probe support can be provided with one or more, when the probe support is provided with multiple, the setting position and number of the probe support correspond to the test probe, that is, one test probe is provided with one probe support, at this time the insulating positioning layer 4 can be provided on the outside of each test probe 1, or a corresponding insulating positioning layer 4 is provided between the two test probes 1 arranged adjacent to each other, the setting of the insulating positioning layer 4 can position and calibrate the test probe 1 and the chip to be tested when they are docked, and can also isolate the two adjacent test probes 1, to avoid collision or signal interference between the test probes 1 during deformation.

[0043] In addition, in order to improve the integration degree of the device and simplify the manufacturing process, the probe support can also be uniformly set, that is, one probe support is provided, such as Figure 5 andFigure 6 As shown, each test probe 1 is formed in an integrated structure through the connecting part 5, that is, the test probes 1 are regularly arranged in an array on the probe support, at this time, the insulating positioning layer 4 can be arranged between the adjacent two test probes 1, or can be arranged only at the edge position of the outermost side of the probe support, and plays a positioning role; it can be known that in the case that the number of test probes 1 is large, a plurality of insulating positioning layers 4 can also be arranged in the middle, that is, the corresponding insulating positioning layer 4 is arranged after a plurality of test probes 1 are spaced, to ensure the regional isolation and positioning function, and the specific number and position are not limited by the utility model, and can be flexibly set according to the structure of the chip to be detected and the test requirements.

[0044] It should be noted that, during the process of testing the chip by the test probe 1, there will be a certain temperature change, in order to avoid mutual interference between the adjacent test probes 1 or the test probe 1 and the test chip, the insulating positioning layer 4 can be arranged outside the base part 11 of the test probe 1, and the material and thickness of the insulating positioning layer 4 can be set according to the specific probe size, and the insulating positioning layer 4 can play the roles of insulation and protection.

[0045] Further, in order to play a positioning role and prevent the test probe 1 from colliding with the solder cap, in the direction parallel to the chip protection layer 3, the length of the insulating positioning layer 4 is not less than the length of the test probe 1, or is set to be the same as the length of the test probe 1, so that when the insulating positioning layer 4 is in contact with the chip protection layer 3, the test probe 1 is located outside the support column 22, and plays a positioning effect. Further, a positioning structure can also be arranged on the chip protection layer 3, when the insulating positioning layer 4 abuts against the chip protection layer 3, the lower end can be limited in the positioning structure at the corresponding position, to prevent the insulating positioning layer 4 from tilting, and improve the positioning accuracy.

[0046] In addition, the insulating positioning layer 4 can adopt various forms such as a plate structure or a columnar structure, when it adopts a plate structure, the positioning and isolation effect is good, but the occupied space is also large, and when a columnar structure is adopted, although the space can be saved, the isolation effect between the test probes 1 can be affected to a certain extent, and the specific setting can be carried out according to the distribution density of the metal bumps 2 on the chip to be detected.

[0047] It should be noted that, since the solder cap 21 on the chip is usually a ball top structure, the support column 22 below it is a cylindrical structure, in order to adapt to the outer shape structure of the metal bump 2, realize that the test probe 1 can effectively contact with the support column 22 when deformed, the cross section of the internal cavity of the test probe 1 (parallel to the direction of the chip protection layer 3) can be set as a circular structure, and ensure that the space of the internal cavity has enough margin to accommodate the solder cap 21, for example, the difference between the cross-sectional size of the internal cavity and the solder cap 21 is in the range of 0-27um, at this time, the solder cap 21 and the test probe 1 can be effectively avoided, and the solder cap 21 can be safely avoided in the internal cavity before and after the opening end 13 of the test probe 1 is retracted and deformed, so as to ensure the integrity of the solder cap 21.

[0048] In the chip insulation test device of the embodiment of the utility model, the test probe 1 is a hollow structure with an opening end 13, an internal cavity communicated with the opening end 13, and a base part 11 connected with the probe support, further, the opening end 13 and the base part 11 are connected through the inclined side arm 12, so as to avoid the solder cap 21 when the opening end 13 is connected with the support column 22; in the first preset temperature range, the size of the opening end 13 is greater than the size D of the solder cap 21, or further smaller than the size E of the internal cavity, at this time, when the test probe 1 is deformed due to temperature influence, since the base part 11 is a solid structure, its deformation has little influence on the size, at the same time, under the action of the inclined side arm 12, the deformation amount of the opening end 13 is maximum, so as to realize the deformation effect of opening outward or shrinking inward.

[0049] It should be noted that, in order to avoid the test probe 1 from shrinking or enlarging as a whole, and cause the internal cavity to collide with the solder cap 21, the opening end 13 part and / or the inclined side arm 12 part of the test probe 1 can be made of memory metal material, while the base part 11 and other parts are made of conventional probe material, so as to ensure that the opening end 13 can be effectively opened or clamped. The cross section of the base part 11 can be set as a rectangle or a square, so as to facilitate fixation on the probe support, and reduce the interference between it and other position test probes 1.

[0050] In addition, the test probe 1 can be connected with an external test system through a PCB, and an adapter plate can also be arranged under special requirements, that is, the test probe is connected and communicated with the PCB through the adapter plate, the PCB is connected with the external test system, and then the test system tests the chip to be tested, in other words, the PCB is arranged on the probe support, the test probe 1 can be fixed on the probe support through the PCB, and in the test process, the external test system is communicated with the test probe 1 through the PCB, so as to realize the transmission of test signals.

[0051] In one specific embodiment of the utility model, the insulation function can also be realized only by the insulation positioning layer 4, at which time the length of the insulation positioning layer 4 can be shortened, and the positioning between the chip to be detected and the test probe can be realized by other positioning structures, and the specific insulation positioning layer structure is as shown in Figure 4

[0052] The process of testing the chip to be detected by the chip insulation test device of the utility model embodiment comprises the following steps: firstly, after moving the test probe above the chip to be detected, the test probe is controlled to descend or the chip to be detected is controlled to ascend until the insulation positioning layer abuts against the chip protection layer; secondly, the opening end of the test probe is controlled to be in contact with the support column, a test signal is sent to the chip to be detected through the test probe, and the chip to be detected is tested through the test signal.

[0053] Specifically, when testing the chip to be detected by using the chip insulation test device, firstly, the probe support and the test probe thereon are moved to the metal bumps on the chip to be detected by the driving device; then, when the opening end of the test probe is in an opening state, the test probe is controlled to move downward or the chip to be detected is controlled to move upward until the insulation positioning layer abuts against the chip protection layer, at which time the opening end is located outside the support column of the metal bump; further, the test probe is controlled to be in a second preset temperature range, due to the characteristics of the memory metal, at this time, the opening end of the test probe will shrink inward and be in contact with the support column, and finally, the external test system completes the related performance detection of the chip through the test probe.

[0054] According to the chip insulation test device of the utility model, the test probe is provided as a deformable cavity structure with an opening end, cooperates with the shape-variable memory metal material, so that the opening end of the test probe can deform correspondingly under the condition of meeting the preset condition, so that the opening end can be in contact with the support column in a clamping jaw type, meanwhile, the positioning between the chip to be detected and the test probe is realized by the insulation positioning layer, and mutual interference between adjacent test probes is avoided, so that the accuracy of detection can be ensured, and the performance and service life of the chip affected due to the damage of the solder cap are avoided.

[0055] The chip insulation test device according to the utility model is described above with reference to the drawings in an exemplary manner. However, those skilled in the art should understand that various improvements can be made to the chip insulation test device of the utility model without departing from the content of the utility model. Therefore, the protection scope of the utility model should be determined by the content of the appended claims.​

Claims

1. A chip insulation testing device, characterized in that, This includes test probes arranged in an array; among which, The metal bumps of the chip to be tested are set on the chip protective layer, including support pillars located on the chip protective layer and solder caps located at the ends of the support pillars; The test probe has an open end, which is used to make contact with the support column to conduct electricity and realize the transmission of test signals. An insulating positioning layer is provided on the outside of the test probe. The insulating positioning layer abuts against the chip protective layer and is used to insulate and position the test probe in contact with the support post.

2. The chip insulation testing device according to claim 1, characterized in that, It also includes a probe holder for fixing the test probe and a drive device for driving the probe holder to move; wherein, The driving device is used to drive the test probe to make contact with the metal bump at the corresponding position through the probe holder.

3. The chip insulation testing device according to claim 2, characterized in that, Multiple probe holders are provided, and each probe holder is correspondingly provided with a test probe; and the insulating positioning layer is provided on the outside of each test probe.

4. The chip insulation testing device according to claim 2, characterized in that, The probe holder is provided with one unit, and the test probes are arranged in an array on the probe holder. The insulating positioning layer is disposed on the outer edge of the probe holder.

5. The chip insulation testing device according to claim 2, characterized in that, The insulating positioning layer has a plate-like structure or a columnar structure.

6. The chip insulation testing device according to claim 1, characterized in that, Along a direction parallel to the chip protective layer, the length of the insulating positioning layer is not less than the length of the test probe.

7. The chip insulation testing device according to claim 1, characterized in that, A positioning structure is provided on the chip protective layer. When the insulating positioning layer abuts against the chip protective layer, the lower end of the insulating positioning layer is limited within the positioning structure.

8. The chip insulation testing device according to claim 1, characterized in that, The test probe has a deformable internal cavity; When preset conditions are met, the open end of the test probe contracts inward and deforms until it contacts and conducts with the support column, and the solder cap is avoided in the internal cavity of the test probe.

9. The chip insulation testing device according to claim 8, characterized in that, The test probe is a shape memory metal component, and the preset condition is a preset temperature condition.

10. The chip insulation testing device according to claim 2, characterized in that, A PCB is mounted on the probe holder, and the test probe is connected to an external test system through the PCB to test the chip under test.

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