Alignment structure, wafer and semiconductor device
By setting a first metal layer with a large coverage area as a background plate in the relative area of the alignment mark, the problem of insufficient recognition of photolithographic alignment marks is solved, thereby improving the process yield and product reliability of semiconductor devices.
Patent Information
- Application Number
- CN202520173407.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2035-01-26
AI Technical Summary
In semiconductor manufacturing, insufficient accuracy in identifying photolithographic alignment marks during photolithography and stacking leads to excessively low metal material density, affecting process yield and product reliability.
By setting a first metal layer in the relative area of the alignment mark, making its coverage area larger than the mark part, it serves as a background plate to ensure accurate recognition by the lithography machine. At the same time, it can be freely arranged on the second metal layer to maintain the overall density of the metal material.
It improves the process yield and product reliability of photolithography and stacking processes, and ensures the accuracy of alignment mark recognition and the density of metal materials.
Smart Images
Figure CN223664904U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and more specifically, to an alignment structure, a wafer, and a semiconductor device. Background Technology
[0002] As semiconductor technology advances towards miniaturization and high performance, 3D stacked chip technology is becoming increasingly critical. During chip stacking, alignment marks are required, such as photolithographic alignment marks and bonding alignment marks. Photolithographic alignment marks are commonly used to ensure precise alignment and positioning between photolithographic layers, while bonding alignment marks are dedicated to achieving seamless connections between upper and lower wafers, between chips, and between chips.
[0003] To ensure the accuracy of the lithography machine's recognition of alignment marks during the photolithography and stacking process, no other layers of patterns are typically placed above or below the area where the alignment marks are located. However, for metal layers, if no other layers of patterns are placed, resulting in a large number of blank areas, the overall density of the metal material will be too low, thereby reducing the process yield and product reliability. Utility Model Content
[0004] The purpose of this invention is to provide an alignment structure that, through the relative arrangement of the first metal layer and the alignment mark, ensures the accuracy of the alignment mark identification while maintaining the overall density of the metal material, thereby improving process yield and product reliability.
[0005] The embodiments of this utility model are implemented as follows:
[0006] In one aspect, this utility model provides an alignment structure, including a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer has an alignment mark, and the alignment mark has at least one marking portion. The second dielectric layer has a first metal layer and a second metal layer formed therein, and the first metal layer and the second metal layer are spaced apart along the stacking direction of the first dielectric layer and the second dielectric layer. The coverage area of the first metal layer is greater than the coverage area of the marking portion.
[0007] Optionally, the first metal layer has a hollow area corresponding to the marking part of the alignment mark, and the orthographic projection area of the hollow area is smaller than the orthographic projection area of the marking part.
[0008] Optionally, the number of markings is four, with the four markings arranged in pairs opposite each other and spaced apart.
[0009] Optionally, the number of marking parts is eight, and the eight marking parts form four marking groups. Each marking group has two parallel and spaced-apart marking parts; the four marking groups are arranged opposite each other and spaced-apart.
[0010] Optionally, the number of markers is four, the four markers are arranged diagonally, and the arrangement directions of adjacent markers are perpendicular to each other.
[0011] Optionally, the outer contour of the first metal layer has a rectangular structure.
[0012] In another aspect, this invention provides a wafer including a body and an alignment structure disposed on the surface of the body.
[0013] Another aspect of this invention provides a semiconductor device, comprising a wafer.
[0014] The beneficial effects of this utility model include at least one of the following:
[0015] This application provides an alignment structure including a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer contains an alignment mark, each marking at least one portion. The second dielectric layer contains a first metal layer and a second metal layer, spaced apart along the stacking direction of the first and second dielectric layers. The coverage area of the first metal layer is larger than the coverage area of the marking portion. Therefore, the first metal layer can serve as a background for the alignment mark, allowing alignment recognition equipment such as lithography machines to still acquire sufficient feature information of the marking portion, thus achieving accurate identification of the alignment mark. Simultaneously, this arrangement avoids creating a large blank area below the alignment mark, allowing for flexible layout of the second metal layer. This alignment structure ensures a certain density of the overall metal material in the product, improving wafer process yield and product reliability.
[0016] This application also provides a wafer including a body and an alignment structure, the alignment structure being disposed on the surface of the body. The wafer, through the provision of the alignment structure, improves the process yield and product reliability of semiconductor devices.
[0017] This application also provides a semiconductor device, including a wafer. The wafer, through the arrangement of alignment structures, improves the process yield and product reliability of the semiconductor device. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 One of the structural schematic diagrams of the alignment structure provided in the embodiment of this utility model;
[0020] Figure 2 A second schematic diagram of the alignment structure provided in this embodiment of the utility model;
[0021] Figure 3 The third schematic diagram of the alignment structure provided in the embodiment of this utility model;
[0022] Figure 4 One of the structural schematic diagrams of the first metal layer of the alignment structure provided in the embodiments of this utility model;
[0023] Figure 5 This is a second schematic diagram of the first metal layer of the alignment structure provided in an embodiment of the present invention.
[0024] Icons: 100 - Alignment structure; 110 - First dielectric layer; 1111 - Marking part; 111 - Alignment mark; 120 - Second dielectric layer; 1211 - Cutout area; 121 - First metal layer; 1221 - Metal block; 122 - Second metal layer; 200 - Wafer. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0028] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0029] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0030] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0031] Please refer to Figure 1 and Figure 2 This embodiment provides an alignment structure 100, including a first dielectric layer 110 and a second dielectric layer 120 stacked together. The first dielectric layer 110 has an alignment mark 111, and the alignment mark 111 has at least one marking portion 1111. The second dielectric layer 120 has a first metal layer 121 and a second metal layer 122 formed therein. The first metal layer 121 and the second metal layer 122 are spaced apart along the stacking direction of the first dielectric layer 110 and the second dielectric layer 120. The coverage area of the first metal layer 121 is larger than the coverage area of the marking portion 1111.
[0032] Specifically, this application provides an alignment structure 100, such as Figure 1As shown, it includes a second metal layer 122, which can contact the body surface of the wafer 200. Next, a second dielectric layer 120 is deposited on the second metal layer 122, and a first metal layer 121 is etched on the second dielectric layer 120, such that the first metal layer 121 and the second metal layer 122 are stacked alternately. The second dielectric layer 120 may contain silicon dioxide, silicon nitride, and silicon carbonitride. A first dielectric layer 110 is deposited on the second dielectric layer 120, stacked with the second dielectric layer 120. Similarly, the first dielectric layer 110 may contain silicon dioxide, silicon nitride, and silicon carbonitride. Alignment marks 111 are etched on the first dielectric layer 110, used to align the mask with the wafer 200. The specific number of the first metal layer 121 and the second metal layer 122 can be adjusted according to actual production needs.
[0033] In existing alignment marks 111, no other patterns can typically be placed on the upper and lower layers to avoid inaccurate identification of the alignment marks 111 during photolithography. Therefore, the coverage area of the first metal layer 121 and the second metal layer 122 on the second dielectric layer 120 is often small to leave blank areas corresponding to the alignment marks 111. However, a small coverage area of the first metal layer 121 and the second metal layer 122 can easily lead to an excessively low overall metal material density, resulting in reduced process yield and product reliability.
[0034] To address the aforementioned issues, this application employs a sophisticated configuration of the relative coverage areas of the first metal layer 121 and the alignment mark 111. The alignment mark 111 has at least one marking portion 1111, which can be used to align the mask with the wafer 200. Correspondingly, the first metal layer 121 is spaced apart in the area opposite to the alignment mark 111. Due to the relative height difference between the first metal layer 121 and the alignment mark 111, a grayscale difference exists between them in actual manufacturing processes, facilitating the differentiation and identification of the alignment mark 111 and the first metal layer 121.
[0035] like Figure 2As shown, to avoid the second metal layer 122 affecting the accurate identification of the alignment mark 111 by the lithography machine during the lithography process, the coverage area of the first metal layer 121 is larger than the coverage area of the mark portion 1111; at this time, the first metal layer 121 is equivalent to the background plate of the alignment mark 111 and will not affect the lithography machine's identification of the alignment mark 111. After setting the first metal layer 121, the second metal layer 122 located below the first metal layer 121 can achieve a free layout of its form and structure, thereby ensuring the overall metal material density together with the first metal layer 121, improving the process yield and product reliability. The second metal layer 122 can be multiple spaced metal blocks 1221, or other metal patterns, or metal interconnects; this application does not limit the specific arrangement of the second metal layer 122.
[0036] In this application, the number and shape of the marking parts 1111 are not limited, and the shape of the second metal layer 122 is not limited. The specific layout structure of the second metal layer 122 can be adjusted according to the density requirements of the product.
[0037] It should be noted that, in one possible implementation of this application, firstly, the number of marking portions 1111 is four, and the four marking portions 1111 are arranged opposite each other and spaced apart.
[0038] Specifically, the number of marking parts 1111 can be four, with the four marking parts 1111 arranged in pairs opposite each other, and there is a certain interval between the two adjacent marking parts 1111; the shape of the marking parts 1111 can be a rectangular structure, or of course other graphic structures; the length and width of the marking parts 1111 are not limited in any way and can be adjusted according to the actual alignment requirements.
[0039] Second, such as Figure 5 As shown, there are eight marking parts 1111, and the eight marking parts 1111 form four marking groups. Each marking group has two parallel and spaced marking parts 1111; the four marking groups are arranged opposite each other and spaced apart.
[0040] Specifically, such as Figure 5As shown, the number of marking portions 1111 can be eight, forming four marking groups. Each marking group has two parallel and spaced-apart marking portions 1111, providing a stable pointing reference in a specific dimension for subsequent key processes such as photolithography and bonding. The two marking portions 1111 in each group are spaced apart to match the optical recognition precision in chip manufacturing. The four marking groups are arranged opposite each other and spaced apart to avoid mutual interference and prevent problems such as electromagnetic interference and optical signal confusion caused by excessive proximity. This arrangement further improves the alignment efficiency of the alignment structure 100. The length and width of the marking portions 1111 are not limited and can be adjusted according to actual alignment requirements.
[0041] Third, such as Figure 4 As shown, there are four marking parts 1111, which are arranged diagonally, and the arrangement directions of two adjacent marking parts 1111 are perpendicular to each other.
[0042] Specifically, such as Figure 4 As shown, the number of marking portions 1111 can be four, arranged diagonally at the four vertices of a square plane. The orientations of adjacent marking portions 1111 are perpendicular to each other, ensuring both horizontal displacement accuracy and precise vertical measurement. For example, in photolithography, the horizontal marking portions 1111 ensure precise horizontal positioning of the pattern, while the vertical marking portions 1111 prevent vertical offset. Together, they improve alignment efficiency, ensuring high precision and high quality in chip manufacturing. The length and width of the marking portions 1111 are not limited and can be adjusted according to actual alignment requirements.
[0043] Fourth, such as Figure 2 , Figure 4 and Figure 5 As shown, the outer contour of the first metal layer 121 is rectangular. The rectangular structure of the first metal layer 121 facilitates processing and also provides sufficient coverage area to ensure that it completely covers the metal block 1221 of the second metal layer 122 without affecting the identification of the alignment mark 111. Of course, the outer contour of the first metal layer 121 can be other structures besides rectangle, such as circles or triangles. This application does not impose any restrictions on its specific structure. In actual production, adjustments can be made according to the metal density rules of the product and the actual area of the alignment mark 111 and the second metal layer 122.
[0044] The alignment structure 100 provided in this application includes a first dielectric layer 110 and a second dielectric layer 120 stacked together. The first dielectric layer 110 has an alignment mark 111, and the alignment mark 111 has at least one marking portion 1111. The second dielectric layer 120 has a first metal layer 121 and a second metal layer 122 formed therein. The first metal layer 121 and the second metal layer 122 are spaced apart along the stacking direction of the first dielectric layer 110 and the second dielectric layer 120. The coverage area of the first metal layer 121 is larger than the coverage area of the marking portion 1111. The second metal layer 122 includes a plurality of metal blocks 1221, and the plurality of metal blocks 1221 are spaced apart in the layer plane. Therefore, the first metal layer 121 can block each metal block 1221 of the second metal layer 122 as a background for the alignment mark 111. Alignment recognition equipment such as lithography machines can still obtain sufficient feature information of the mark 1111, thereby achieving accurate recognition of the alignment mark 111. At the same time, this arrangement avoids setting a large number of blank areas below the alignment mark 111. Therefore, the multiple metal blocks 1221 of the second metal layer 122 can be freely arranged, ensuring that the overall metal material has a certain density, improving the process yield and product reliability of the wafer 200.
[0045] In one possible implementation of this application, such as Figure 3 , Figure 4 and Figure 5 As shown, the first metal layer 121 has a hollow area 1211 corresponding to the marking part 1111 of the aligned mark 111. The orthographic projection area of the hollow area 1211 is smaller than the orthographic projection area of the marking part 1111.
[0046] Specifically, if the size of the marking portion 1111 of the alignment mark 111 is too large, and the coverage area of the first metal layer 121 is greater than the coverage area of the alignment mark 111, the second metal layer 122 may not meet the product metal density rules. Therefore, in this case, if... Figure 3 , Figure 4 and Figure 5 As shown, the first metal layer 121 has a hollow area 1211 corresponding to the marking portion 1111 of the alignment mark 111. The projected area of the hollow area 1211 is smaller than the projected area of the marking portion 1111. By setting the hollow area 1211, the area of the metal block 1221 is reduced without obstructing the marking portion 1111 or affecting the lithography machine's recognition of the alignment mark 111, thereby ensuring that the second metal layer 122 can meet the product's metal density requirements.
[0047] In another aspect of this application, a wafer 200 is provided, including a body and an alignment structure 100, wherein the alignment structure 100 is disposed on the surface of the body.
[0048] Specifically, the wafer 200 includes a body and an alignment structure 100. Typically, the wafer 200 body is made of high-purity single-crystal silicon. Silicon possesses excellent semiconductor properties, enabling the realization of various electrical functions in subsequent chip manufacturing processes. Single-crystal silicon undergoes a series of complex and precise processes such as crystal pulling and dicing to be fabricated into circular wafers with specific thicknesses and extremely high flatness to meet the needs of chip manufacturing at different scales.
[0049] The alignment structure 100 is disposed on the surface of the chip body. In the chip manufacturing process, many complex process steps are involved. Among them, key steps such as photolithography, etching, and bonding require high-precision alignment operations. The setting of the alignment structure 100 can ensure that each circuit pattern and each functional module can be accurately superimposed and work together, laying a solid foundation for the high-precision implementation of subsequent chip manufacturing processes and the high-quality output of finished chips.
[0050] The aforementioned wafer 200, through the arrangement of the alignment structure 100, improves the process yield and product reliability of semiconductor devices. The specific structure and beneficial effects of the alignment structure 100 have been described in detail above and will not be repeated here.
[0051] In another aspect of this application, a semiconductor device is provided, including a wafer 200. The number of wafers 200 can be multiple. When multiple wafers 200 are present, they are stacked, and an alignment structure 100 is disposed on the surface of the topmost wafer 200. The specific structure and beneficial effects of the wafer 200 have been described in detail above and will not be repeated here. The wafer 200, through the arrangement of the alignment structure 100, improves the process yield and product reliability of the semiconductor device.
[0052] The above description is merely an optional embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
[0053] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable way without contradiction. In order to avoid unnecessary repetition, this utility model will not describe the various possible combinations separately.
Claims
1. An alignment structure, characterized in that, The device includes a first dielectric layer (110) and a second dielectric layer (120) stacked together. The first dielectric layer (110) has an alignment mark (111) and the alignment mark (111) has at least one marking portion (1111). The second dielectric layer (120) has a first metal layer (121) and a second metal layer (122) formed therein. The first metal layer (121) and the second metal layer (122) are spaced apart along the stacking direction of the first dielectric layer (110) and the second dielectric layer (120). The coverage area of the first metal layer (121) is larger than the coverage area of the marking portion (1111).
2. The alignment structure according to claim 1, characterized in that, The first metal layer (121) has a hollow area (1211) corresponding to the marking part (1111) of the alignment mark (111), and the orthographic projection area of the hollow area (1211) is smaller than the orthographic projection area of the marking part (1111).
3. The alignment structure according to claim 1, characterized in that, The number of the marking parts (1111) is four, and the four marking parts (1111) are arranged opposite each other and spaced apart.
4. The alignment structure according to claim 1, characterized in that, The number of the marking parts (1111) is eight, and the eight marking parts (1111) form four marking groups. Each marking group has two parallel and spaced marking parts (1111); the four marking groups are arranged opposite each other and spaced apart.
5. The alignment structure according to claim 1, characterized in that, The number of the marking parts (1111) is four, and the four marking parts (1111) are arranged diagonally, and the arrangement directions of two adjacent marking parts (1111) are perpendicular to each other.
6. The alignment structure according to claim 1, characterized in that, The outer contour of the first metal layer (121) is rectangular.
7. A wafer, characterized in that, It includes a body and an alignment structure (100) as described in any one of claims 1-6, wherein the alignment structure (100) is disposed on the surface of the body.
8. A semiconductor device, characterized in that, Includes the wafer (200) as described in claim 7 above.