Resistor chip and electronic device

Abstract

The utility model is suitable for the technical field of electronics, and provides a resistor chip and an electronic device. The resistor chip provided by the utility model comprises a glass substrate, and the glass substrate comprises a first surface and at least two through holes penetrating in the thickness direction of the glass substrate; the through holes are filled with the conductive connection structures, the conductive connection structures extend to the first surface, and interval areas are formed between the conductive connection structures extending to the first surface; and the resistance layer is formed on the first surface where the interval region is located and is connected with the at least two conductive connection structures, and the projection of the resistance layer on the first surface covers the projection of the conductive connection structures on the first surface. According to the resistor chip and the electronic device provided by the invention, the heat loss can be reduced, and the conductive connection structure is covered by the resistive layer, so that the resistor chip has higher process tolerance in the manufacturing process, the production cost is reduced, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a resistance chip and an electronic device. BACKGROUND

[0002] At present, the substrate of the existing resistance chip generally adopts the structure of welding the resistance chip on a mother board. Specifically, the resistance chip includes a mother board and a plurality of substrates arranged on the mother board. The material of the substrate is generally a silicon-based resin substrate. The resistance chip includes a resistance body arranged on the side of the substrate away from the mother board, and a conductive layer arranged on the mother board and the substrate, respectively. The conductive layer is arranged on both sides of the resistance body and both sides of the substrate. When forming a conductive connection structure, the conductive layers on the mother board and the substrate need to be welded to form a conductive connection structure, that is, the resistance chip is formed by welding from the side. However, the existence of the side welding wire leads to large heat loss, which reduces the performance of the resistance chip. CONTENT OF THE UTILITY MODEL

[0003] The present application provides a resistance chip and an electronic device, aiming to solve the technical problem of large heat loss in the manufacturing process of the resistance chip in the prior art, which affects the performance of the resistance chip.

[0004] The present application provides a resistance chip, which includes:

[0005] A glass substrate including a first surface and at least two through holes penetrating in the thickness direction of the glass substrate;

[0006] At least two conductive connection structures filled in the through holes and extending to the first surface, and the conductive connection structures extending to the first surface form a spacing region between them;

[0007] A resistance layer formed on the first surface where the spacing region is located and connected to the at least two conductive connection structures. The projection of the resistance layer on the first surface covers the projection of the conductive connection structures on the first surface.

[0008] In some embodiments, the glass substrate further includes a second surface opposite to the first surface;

[0009] The resistance chip further includes:

[0010] A welding layer located on the second surface, which covers the conductive connection structures of the through holes at the opening position of the second surface.

[0011] In some embodiments, the glass substrate further includes a second surface opposite to the first surface;

[0012] The conductive connection structure also protrudes from the second surface, or protrudes from the second surface and extends to the plane where the second surface is located.

[0013] In some embodiments, the resistance chip further comprises: a first insulating layer, located on the second surface and covering an area other than the solder layer.

[0014] In some embodiments, the resistance chip further comprises: a solder protection layer, located on the surface of the solder layer away from the second surface.

[0015] In some embodiments, the projected area of the resistance layer on the first surface is greater than the projected area of the conductive connection structure on the first surface.

[0016] In some embodiments, the material of the resistance layer is one or more of titanium or a compound of titanium.

[0017] In some embodiments, the cross-sectional area of the through hole gradually decreases in the direction from the first surface to the second surface.

[0018] The present application also provides an electronic device comprising the resistance chip as described in any one of the above.

[0019] The resistance chip and the electronic device provided by the present application can reduce heat loss by filling the conductive connection structure inside the glass substrate, thereby reducing the influence of heat loss on the performance of the resistance chip. In addition, the resistance layer covers the conductive connection structure, which can prevent the corrosion of the conductive connection structure, and also allows the resistance chip to have higher process tolerance during the manufacturing process, thereby improving the yield and reducing the production cost and improving the production efficiency.

[0020] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is one of the structural schematic diagrams of the resistance chip provided by the embodiments of the present application;

[0022] Figure 2 is another of the structural schematic diagrams of the resistance chip provided by the embodiments of the present application;

[0023] Figure 3 is a third of the structural schematic diagrams of the resistance chip provided by the embodiments of the present application;

[0024] Figure 4 is a fourth of the structural schematic diagrams of the resistance chip provided by the embodiments of the present application;

[0025] Figure 5 FIG. 5 is a structural schematic diagram of a resistance chip provided by an embodiment of the present application;

[0026] Figure 6 FIG. 1 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0027] Figure 7 FIG. 2 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0028] Figure 8 FIG. 3 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0029] Figure 9 FIG. 4 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0030] Figure 10 FIG. 5 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0031] Figure 11 FIG. 6 is a manufacturing process schematic diagram of a resistance chip provided by an embodiment of the present application;

[0032] Figure 12 FIG. 7 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation on the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0034] In the description of the present application, it should be understood that the terms "upper", "lower", "back", "front" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0035] In the present application, unless specifically defined and limited otherwise, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher in horizontal height than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the first feature is lower in horizontal height than the second feature.

[0036] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of specific examples are described in the following. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, which does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0037] Figure 1 is one of the structural schematic diagrams of the resistance chip provided by the embodiments of the present application. As shown in Figure 1 , the resistance chip comprises:

[0038] a glass substrate 10, the glass substrate 10 comprises a first surface 101 and at least two through holes 201 penetrating through the thickness direction of the glass substrate;

[0039] at least two conductive connection structures 20, the conductive connection structure 20 is filled in the through hole 201 and extends to the first surface 101, and the conductive connection structure 20 extending to the first surface 101 forms a spacing area between them;

[0040] a resistance layer 30 formed on the first surface 101 where the spacing area is located and connected to the at least two conductive connection structures 20, the projection of the resistance layer 30 on the first surface 101 covers the projection of the conductive connection structure 20 on the first surface 101.

[0041] In actual implementation, the resistance chip comprises the glass substrate 10, the conductive connection structure 20 and the resistance layer 30.

[0042] The glass substrate 10 comprises opposite first surface 101 and second surface 102, and at least two through holes penetrating through the glass substrate 10 along the thickness direction of the glass substrate 10.

[0043] Optionally, the shape and inner diameter of the through hole can be set according to actual needs, and are not specifically limited here. For example, the shape of the through hole can be funnel-shaped, cylindrical, frustum-shaped, or hourglass-shaped, etc.

[0044] The embodiments of this application do not impose specific limitations on the number of through holes, and are not specifically limited herein.

[0045] Optionally, when the number of through holes is even, the multiple through holes can be evenly distributed on both sides of the glass substrate 10. For example: Figure 2 As shown, there are two through holes; one through hole can be provided on each side of the glass substrate 10. Figure 3 As shown, there are 4 through holes, and 2 through holes can also be provided on each side of the glass substrate 10; in other embodiments, there can be 6 through holes, and 3 through holes can also be provided on each side of the glass substrate 10, etc.

[0046] Optionally, when the number of through holes is odd, the multiple through holes can also be unevenly distributed on both sides of the glass substrate 10, without specific limitations. For example, if the number of through holes is 3, one through hole can be provided on the first side of the glass substrate 10, and two through holes can be provided on the second side of the glass substrate 10; if the number of through holes is 5, three through holes can be provided on the first side of the glass substrate 10, and two through holes can be provided on the second side of the glass substrate 10, etc.

[0047] Understandable, Figure 2 This is a top view of the resistor chip. Figure 1 for Figure 2 A cross-sectional view along the A-A1 direction.

[0048] The conductive connection structure 20 filling each through hole extends along the inside of the through hole to the opening position of the through hole on the first surface 101, and also extends onto the first surface 101. In this embodiment, at least two conductive connection structures 20 can be filled in each through hole in a one-to-one correspondence.

[0049] It is understood that the conductive connection structure 20 can be a single layer of metal material or multiple layers of metal material, such as including a conductive adhesion layer and a conductive filler layer. The adhesion layer helps to improve the adhesion between the conductive connection structure 20 as a whole and the glass.

[0050] like Figure 1 As shown, the portion of the conductive connection structure 20 extending to the first surface 101 is called the first conductive connection structure 201, and the portion of the conductive connection structure 20 located within the through hole is called the second conductive connection structure 202. There are interval regions between the first conductive connection structures 201 corresponding to different through holes.

[0051] Optionally, the aperture of the through hole ranges from 10 microns to 500 microns, for example, can be 10 microns, 20 microns, 30 microns, 50 microns, 70 microns, 100 microns, 120 microns, 150 microns, 200 microns, 250 microns, 300 microns, 400 microns or 500 microns, etc.

[0052] As shown in Figure 1 The resistance layer 30 can cover part of the second conductive connection structure 202 on the first surface 101. Figure 4 As shown in The resistance layer 30 can cover all of the second conductive connection structure 202 on the first surface 101, including the edge part of the second conductive connection structure 202. Therefore, the projection of the resistance layer 30 on the first surface 101 covers the projection of the conductive connection structure 20 on the first surface 101.

[0053] In some embodiments, the projection area of the resistance layer 30 on the first surface 101 is greater than the projection area of the conductive connection structure 20 on the first surface 101.

[0054] Figure 4 It can be understood that in order to better prevent the conductive connection structure 20 from being corroded and not in contact with moisture and air, as shown in

[0055] It should be noted that the conductive connection structure 20 is made of a metal material, preferably copper, which has good conductivity, low resistivity and strong resistance to electron migration. By directly filling the conductive connection structure 20 in the through hole, electrical connection with other structures on the two surfaces in the thickness direction can be achieved, ensuring the conductivity of the resistance chip.

[0056] In the related art, a plurality of resistance chips are cut into small chips after the resistance layer 30 and the like are made on a large glass substrate, which is suitable for batch production of resistance chips. Before cutting, most of the resistance layer needs to be etched to facilitate cutting, and the etched resistance layer 30 cannot be utilized, resulting in a decrease in the utilization rate of the resistance layer 30.

[0057] The resistance layer 30 in the embodiments of the present application can cover the interval areas between the first conductive connection structures 201 and the surfaces of the first conductive connection structures 201 away from the first surface 101. The resistance layer 30 can be a resistance pattern with a conductive function, which can not only prevent the corrosion of the conductive connection structure 20 by covering the conductive connection structure 20 on the first surface 101, but also can etch away as few as possible of the resistance layer 30 in the process of forming the resistance layer 30, so as to retain as much as possible of the resistance layer 30, reduce the chemical reagents used for etching, and thus shorten the processing time of the exposure, development, etching and other processes, thereby reducing the manufacturing cost of the resistance chip. In addition, the larger resistance layer is more tolerant to changes in process parameters, which means that even if some process parameters (such as exposure dose, development time, etching rate, etc.) deviate slightly, it will not have a significant impact on the final pattern quality. This higher tolerance can improve the yield.

[0058] The embodiments of the present application use a glass substrate 10 instead of a resin substrate, and at least two through holes penetrating the first surface 101 and the second surface 102 are provided on the glass substrate 10, which can reduce the heat loss in the process of the resistance chip. The glass substrate is used as the carrier plate of the chip, which can maintain stability at high temperature due to the good thermal stability of the glass substrate, and can better withstand higher temperatures during packaging, thereby avoiding distortion or error in the signal transmission process, while reducing warping and deformation. Glass has high insulation performance, usually reaching 1011-1012ohm·m, which is much higher than silicon 2-103ohm·m, and also higher than ceramic, and is an ideal material for high-resistance insulation substrate. In addition, the flatness of the glass substrate is high, and the surface roughness is ≤5nm, which can make high-precision lines and ensure the accuracy of the signal transmission path. Although glass is brittle, the chip size in the present application is small, and the subsequent use process is not affected. In addition, glass has ultra-low insertion loss and small electromagnetic wave interference, so it has become a substrate material with wide application prospect.

[0059] In some embodiments, the material of the resistance layer 30 is one or more of titanium or a compound of titanium.

[0060] In some embodiments, the glass substrate 10 further comprises: a second surface 102 opposite to the first surface 101.

[0061] The conductive connection structure 20 also protrudes from the second surface, or protrudes from the second surface and extends to the plane where the second surface 102 is located.

[0062] As Figure 1 and Figure 4As shown, the glass substrate 10 can include a second surface 102 opposite to the first surface 101. In the embodiment, a portion of the conductive connection structure 20 protruding from the second surface and extending to the second surface 102 can be referred to as a third conductive connection structure 203. There is a spacing region between different through holes corresponding to the third conductive connection structure 203.

[0063] The protruding thickness of the third conductive connection structure 203 can be selected and adjusted according to actual conditions, and the projection area of the third conductive connection structure 203 on the second surface can be equal to or different from the projection area of the first conductive connection structure 201 on the second surface, which is not specifically limited here.

[0064] In some embodiments, the glass substrate 10 further includes: a second surface 102 opposite to the first surface 101;

[0065] The resistance chip further includes: a solder layer 203 located on the second surface 102; and the solder layer 203 covers the conductive connection structure 20 at the opening position of the through hole on the second surface 102.

[0066] It can be understood that the third conductive connection structure 203 can be equivalent to the solder layer 203, and the solder layer 203 is a structure filled after the conductive connection structure 20 is filled, and the third conductive connection structure 203 is a structure formed when the conductive connection structure 20 is filled.

[0067] In another embodiment, the conductive connection structure 20 is filled to the opening position of the second surface 102, and the conductive connection structure 20 does not have a portion protruding from the second surface and extending to the second surface 102.

[0068] In the embodiment, the solder layer 203 can be added at the opening position of the second surface 102. The solder layer 203 is consistent with the material of the conductive connection structure 20, for example, both are copper, so as to ensure that the resistance chip has good conductive performance.

[0069] The solder layer 203 can serve as a conductive pad of the resistance chip, and the conductive pad can be connected with an external circuit. Specifically, the external circuit can be any one of a printed circuit board (PCB), a packaging substrate, or a semiconductor device. The solder layer 203 serves as an output terminal or an input terminal of the resistance chip.

[0070] In some embodiments, the resistance chip further includes: a first insulating layer 40 located on the second surface 102 and covering an area other than the solder layer 203.

[0071] In actual implementation, as Figure 1 and Figure 4As shown, the first insulating layer 40 serves to protect the corners of the solder layer 203 (or the third conductive connection structure 203) from corrosion and from contacting moisture and air, i.e. the thickness of the first insulating layer 40 is greater than or equal to the thickness of the solder layer 203 (or the third conductive connection structure 203), and the first insulating layer 40 does not cover the outer surface of the solder layer 203 (or the third conductive connection structure 203) to ensure that the solder layer 203 (or the third conductive connection structure 203) achieves effective electrical connection.

[0072] In some embodiments, the first insulating layer 40 can be made of organic resin, which is not specifically limited herein.

[0073] In some embodiments, the resistance chip further comprises a solder protection layer 50 located on the surface of the solder layer 203 away from the second surface 102. The solder protection layer 50 can be made of a material having a conductive effect.

[0074] As shown in Figure 1 and Figure 4 The solder protection layer 50 can be used to protect the solder layer 203 (or the third conductive connection structure 203) from external corrosion and can isolate moisture and air. It can be understood that if the resistance chip is in an environment that is not prone to corrosion, such as in a vacuum, the solder protection layer 50 can also not be provided.

[0075] In actual implementation, the solder protection layer 50 can be processed by electroless nickel immersion gold (ENIG) technology.

[0076] In the semiconductor and electronic manufacturing industry, especially in the manufacturing process of printed circuit boards, electroless nickel immersion gold is a common surface treatment technology. Electroless nickel immersion gold is a technology that deposits a combined nickel and gold plating layer on the surface of a metal through a chemical method. The technology first forms a uniform nickel plating layer on the surface of the substrate by chemical nickel plating, and then forms a thin gold plating layer on the basis of this by immersion gold process. The chemical nickel plating process does not require an external power source, but forms a plating layer on the surface of the metal through a chemical reaction.

[0077] The material of the solder protection layer 50 is composed of nickel and gold. Through electroless nickel immersion gold processing, a corrosion-resistant nickel layer can be formed, which provides an effective barrier to prevent the copper circuit from being affected by oxidation or other corrosive substances. A corrosion-resistant gold layer can also be formed, which further enhances the corrosion resistance.

[0078] The electroless nickel immersion gold processing can provide a good contact surface for the solder layer 203 (or the third conductive connection structure 203), which helps to improve the wettability and reliability during soldering.

[0079] In some embodiments, asFigure 1 and Figure 4 As shown, the thickness of the first insulating layer 40 can be greater than or equal to the total thickness of the welding layer 203 and the welding protective layer 50, ensuring that the welding layer 203 (or the third conductive connection structure 203) and the welding protective layer 50 will not be corroded; the thickness of the first insulating layer 40 can also be equal to the thickness of the welding layer 203 (or the third conductive connection structure 203), and the first insulating layer 40 and the welding protective layer 50 together protect the welding layer 203 (or the third conductive connection structure 203), ensuring that the welding layer 203 (or the third conductive connection structure 203) will not be corroded.

[0080] In some embodiments, the thickness of the glass substrate 10 ranges from 10 micrometers to 2 millimeters, and the thickness of the resistive layer 30 ranges from 1000 angstroms to 1 micrometer.

[0081] Optionally, the thickness of the glass substrate 01 ranges from 10 micrometers to 2 millimeters, for example, it can be 10 micrometers, 20 micrometers, 30 micrometers, 50 micrometers, 1 millimeter, 1.5 millimeters or 2 millimeters, and / or the thickness of the resistive layer 30 ranges from 1000 angstroms to 1 micrometer, for example, it can be 1000 angstroms, 2000 angstroms, 3000 angstroms, 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.5 micrometers or 1 micrometer, etc.

[0082] In some embodiments, the cross-sectional area of ​​the through hole gradually decreases along the direction from the first surface 101 to the second surface 102.

[0083] like Figure 5 As shown, after a through hole is formed on one side of the glass substrate 10, a hole that is wider at the top and narrower at the bottom is formed, and the cross-sectional area of ​​the through hole gradually decreases along the direction from the first surface 101 to the second surface 102.

[0084] The following describes the manufacturing process of the resistor chip.

[0085] Step 1: As Figure 6 As shown, a glass substrate 10 is provided; as Figure 7 As shown, at least two through holes penetrating along the thickness direction of the glass substrate 10 can be formed by etching on either the first surface 101 or the second surface 102. The first surface 101 is... Figure 6 The upper surface of the middle glass substrate 10, the second surface 102 is Figure 6 The lower surface of the glass substrate 10.

[0086] Step 2: As Figure 8As shown, the conductive connection structure 20 is filled in the through hole and extends to the first surface 101 and the second surface 102. By directly filling the conductive material in the through hole, the first conductive connection structure 201 filled in the through hole, the second conductive connection structure 202 extending to the first surface, and the third conductive connection structure 203 (or the solder layer 203) extending to the first surface are formed, which is simple and easy to operate and improves the processing efficiency.

[0087] Step 3: as shown in Figure 9 Through completing the dry film pasting, exposure, development, etching and the like, the patterning process is completed, and the resistance layer 30 is formed on the first surface 101. The resistance layer can be a titanium layer or a titanium compound layer, such as titanium carbide, titanium silicide, etc.

[0088] Step 4: as shown in Figure 10 The first insulating layer 40 is arranged on the second surface 102 in the area other than the third conductive connection structure 203 (or the solder layer 203).

[0089] Step 5: as shown in Figure 11 The solder protection layer 50 is formed on the surface of the third conductive connection structure 203 (or the solder layer 203) to prevent the third conductive connection structure 203 (or the solder layer 203) from being corroded.

[0090] Step 6: as shown in Figure 1 The same insulating material can be further used to cover the surface of the first insulating layer 40 to increase the thickness of the first insulating layer 40, so that the thickness of the first insulating layer 40 is greater than or equal to the total thickness of the third conductive connection structure 203 (or the solder layer 203) and the solder protection layer 50.

[0091] Figure 12 is a structural schematic diagram of an electronic device provided by the embodiment of the present application. As shown in Figure 12 The electronic device includes the resistance chip as any one of the above.

[0092] The electronic device can be a terminal product applied to a resistance chip, such as a mobile phone, a computer, a charger, an electronic cigarette or a display, a vehicle, etc., or can be a semi-finished product with a resistance chip, such as various sensors (temperature, thermistor), a PCBA (Printed Circuit Board Assembly), a driving module, a control system, a power management module, etc., which is not specifically limited here.

[0093] In the description of the specification, reference to "some embodiments", "certain embodiments", "exemplary embodiments", "specific embodiments", or "some examples" etc., mean that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0094] Moreover, the above-description of the present application is by way of example, not of limitation, and proper modifications, equivalent substitutions and improvements are intended to be included within the scope of the application.

Claims

1. A resistor chip, characterized in that, include: A glass substrate, including a first surface and at least two through holes extending through the thickness direction of the glass substrate; At least two conductive connection structures are provided, the conductive connection structures are filled in the through hole and extend to the first surface, and the conductive connection structures extending to the first surface form a gap region between them; A resistive layer is formed on the first surface where the spacing region is located and connects the at least two conductive connection structures, wherein the projection of the resistive layer on the first surface covers the projection of the conductive connection structure on the first surface.

2. The resistor chip according to claim 1, characterized in that, The glass substrate further includes: a second surface opposite to the first surface; the resistor chip further includes: A weld layer located on the second surface; the weld layer covers the conductive connection structure at the opening location of the through hole on the second surface.

3. The resistor chip according to claim 1, characterized in that, The glass substrate further includes a second surface opposite to the first surface; The conductive connection structure also protrudes from the second surface, or protrudes from the second surface and extends into the plane containing the second surface.

4. The resistor chip according to claim 2, characterized in that, The resistor chip further includes a first insulating layer, which is located on the second surface and covers the area excluding the solder layer.

5. The resistor chip according to claim 4, characterized in that, The resistor chip further includes a welding protective layer, which is located on the surface of the welding layer away from the second surface.

6. The resistor chip according to any one of claims 1-5, characterized in that, The projected area of ​​the resistive layer on the first surface is greater than the projected area of ​​the conductive connection structure on the first surface.

7. The resistor chip according to claim 2 or 3, characterized in that, Along the direction from the first surface to the second surface, the cross-sectional area of ​​the through hole gradually decreases.

8. An electronic device, characterized in that, include: The resistor chip according to any one of claims 1-7.

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