Signal generation circuit, boundary scanning unit, circuit and electronic equipment

Abstract

The embodiment of the utility model relates to the technical field of chips, and discloses a signal generation circuit, a boundary scanning unit, a circuit and electronic equipment, and the signal generation circuit outputs a first level signal through two input OR gate modules, and outputs a second IO signal through a first data triggering module. A first data trigger module is used for outputting a first level signal, a three-input OR gate module is used for outputting a second level signal, a second data trigger module is used for outputting a selection signal, and a first IO signal input to a two-input OR gate module is set as a high level signal, so that the first level signal is the high level signal, and the second level signal is the high level signal; according to the technical scheme, the selection signal is enabled to be a high-level signal, and when the selection signal is the high-level signal, the IO state of the IO unit is controlled by the boundary scanning unit, so that the IO state of the IO unit can be maintained under the condition that the JTAG switches the IR instruction, and the use scene of the JTAG is expanded.

Description

Technical Field

[0001] This application relates to the field of solid-state drive applications, and in particular to a signal generation circuit, a boundary scanning unit, a circuit, and an electronic device. Background Technology

[0002] JTAG (Joint Test Action Group) is a standard interface and protocol for testing and debugging circuit boards and their internal integrated circuits. It defines test access ports (TAPs) on the chip, which control the chip's internal registers via a serial scan chain, thereby testing and debugging the chip or circuit board.

[0003] In chip applications, there is a need to maintain I / O state. To achieve this, it is often necessary to insert I / O cells with retention functionality during the chip design phase. However, inserting I / O cells with retention functionality inevitably requires the insertion of additional latch structures, resulting in increased area usage.

[0004] Currently, I / O states are typically implemented using the Boundary Scan Cell (BSC) of the IEEE 1149.1 standard. However, this approach, once the BSC takes over I / O control, will cause the BSC to stop controlling I / O if the IR instruction is switched, thus exiting I / O state maintenance. As a result, after I / O state maintenance is implemented, the JTAG port can no longer be used to configure other test data registers (TDR), thereby narrowing the use cases of JTAG. Utility Model Content

[0005] This application provides a signal generation circuit, a boundary scan unit, a circuit, and an electronic device to maintain the IO state and expand the application scenarios of JTAG.

[0006] To address the aforementioned technical problems, this application provides the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a signal generation circuit applied to a boundary scan circuit. The boundary scan circuit includes a boundary scan unit and an I / O unit, with the boundary scan unit connected to the I / O unit. The signal generation circuit includes:

[0008] A two-input OR gate module is used to input a first IO signal to output a first level signal;

[0009] The first data trigger module is connected to the two-input OR gate module and is used to receive the first level signal output by the two-input OR gate module in order to output the second IO signal.

[0010] A three-input OR gate module is connected to a first data trigger module and is used to receive the second IO signal output by the first data trigger module in order to output a second level signal.

[0011] The second data trigger module is connected to the three-input OR gate module and is used to receive the second level signal output by the three-input OR gate module to output a selection signal. When the selection signal is a high level signal, the IO state of the IO unit is controlled by the boundary scan unit.

[0012] Specifically, the first IO signal is set to a high level signal, which makes the first level signal a high level signal, makes the second level signal a high level signal, and thus makes the selection signal a high level signal.

[0013] In some embodiments,

[0014] The second IO signal output by the first data trigger module is input to the two-input OR gate module;

[0015] The selection signal corresponds to an initial selection signal, and the initial selection signal and the first IO signal are input to the three-input OR gate module.

[0016] In some embodiments,

[0017] The boundary scan circuitry includes a test access port controller;

[0018] After the boundary scan circuit executes the I / O instruction, and when the test access port controller is in a specific state, the first I / O signal is set to a high level.

[0019] Among these, the specific states include the Update_IR state.

[0020] In some embodiments,

[0021] The first data triggering module includes a first data trigger, which includes a D trigger.

[0022] The second data triggering module includes a second data trigger, which includes a D trigger.

[0023] In some embodiments,

[0024] The selection signals include the select_jtag_output signal, which is output by the second data trigger. When the select_jtag_output signal is high, the IO state of the IO unit is controlled by the boundary scan unit.

[0025] In some embodiments,

[0026] The two-input OR gate module includes a two-input OR gate circuit, and the two-input OR gate circuit includes a multiplexer;

[0027] A three-input OR gate module includes a three-input OR gate circuit, which includes a multiplexer.

[0028] Secondly, embodiments of this application provide a boundary scanning unit, including:

[0029] Such as the signal generation circuit in the first aspect.

[0030] Thirdly, embodiments of this application provide a boundary scanning circuit, including:

[0031] I / O unit;

[0032] For example, the boundary scan unit in the second aspect is connected to the IO unit and is used to control the IO state of the IO unit.

[0033] Fourthly, embodiments of this application provide an electronic device, including:

[0034] Such as the boundary scan circuit in the third aspect.

[0035] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a signal generation circuit applied to a boundary scan circuit. The boundary scan circuit includes a boundary scan unit and an I / O unit, with the boundary scan unit connected to the I / O unit. The signal generation circuit includes: a two-input OR gate module for inputting a first I / O signal to output a first level signal; a first data trigger module connected to the two-input OR gate module for receiving the first level signal output by the two-input OR gate module to output a second I / O signal; a three-input OR gate module connected to the first data trigger module for receiving the second I / O signal output by the first data trigger module to output a second level signal; and a second data trigger module connected to the three-input OR gate module for receiving the second level signal output by the three-input OR gate module to output a selection signal. When the selection signal is a high-level signal, the I / O state of the I / O unit is controlled by the boundary scan unit. The first I / O signal is set to a high-level signal, making the first level signal high, making the second level signal high, and thus making the selection signal high.

[0036] The first level signal is output through a two-input OR gate module, and the second IO signal is output through a first data trigger module. Then, the second level signal is output through a three-input OR gate module, and finally, the selection signal is output through the second data trigger module. Since the first IO signal input to the two-input OR gate module is set to a high level, the first level signal is high, which in turn makes the second level signal high, and thus the selection signal is high. When the selection signal is high, the IO state of the IO unit is controlled by the boundary scan unit, thereby maintaining the IO state of the IO unit when switching IR instructions in JTAG, thus expanding the application scenarios of JTAG. Attached Figure Description

[0037] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0038] Figure 1 This is a schematic diagram illustrating the connection relationship between a boundary scan unit and an I / O unit according to an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of a select_jtag_output generation circuit provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the structure of a signal generation circuit provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of another signal generation circuit provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of another signal generation circuit provided in the embodiments of this application;

[0043] Figure 6 This is a schematic diagram of the structure of a boundary scanning unit provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the structure of a boundary scan circuit provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0046] Explanation of icon numbers:

[0047]

[0048] Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0051] Before describing the technical solution of this application, the relevant technical terms will be explained.

[0052] (1) Design for Test (DFT) refers to making integrated circuits easier to test and reducing the complexity of subsequent testing by considering test requirements during the design process.

[0053] (2) The Boundary Scan Cell (BSC) is a key component of boundary scan testing technology, primarily used for Design for Test (DFT) of integrated circuits (ICs) and circuit boards. Each BSC is typically connected to an I / O pin, enabling the input of test data from the outside to the chip and the output of internal states to the outside. Multiple BSCs are connected to form a serial boundary-scan chain, transmitting data through the boundary scan register (BSR), allowing data from multiple cells to be transmitted sequentially within the chain. The boundary scan cell selects different operating modes, such as test mode and normal operation mode, using specific control signals (e.g., TCK, TMS, TDI, and TDO).

[0054] (3) The Test Access Port (TAP) is a key component in boundary scan testing technology, primarily used to control and access the boundary scan functionality within an integrated circuit (IC). The TAP is part of the implementation of boundary scan standards (such as IEEE 1149.1), allowing for testing and debugging of devices without direct connection to circuit pins.

[0055] (4) The TAP Controller is a controller used to manage and control the Test Access Port (TAP). It manages and controls the operation of the TAP. Internally, the TAP controller implements a state machine that switches between different states based on the input of the TMS signal. The states of the TAP controller include: Test_Logic_Reset, Run_Test_Idle, Select_DR_Scan, Select_IR_Scan, Capture_DR, Shift_IR, and Shift_DR.

[0056] (5) A Data Flip-Flop (DFF), also known as a D flip-flop, is a basic digital circuit element used to store information in a single bit. It receives and stores input data when triggered at the edge of a clock signal (usually a rising or falling edge). A D flip-flop typically consists of two NAND gates or two NOR gates, with a feedback loop to store information. When the signal at the data input is 1, the D flip-flop stores a 1 state; when the signal at the data input is 0, the D flip-flop stores a 0 state. In JTAG boundary scan testing, each DFF is typically connected to an input or output pin of the circuit. Through the DFF, the test system can control the flow of signals and read the state of the pins in test mode. In a boundary scan chain, multiple DFFs are connected sequentially to form a scan chain. Test data can be serially input into the chain via the JTAG interface, and results can be output from the chain. This allows for fault detection without physical contact with the circuit. DFFs can also be used to monitor the state of the circuit, assisting engineers in debugging and analysis. During testing, DFF can record the state of the circuit at different points in time, thus providing a basis for troubleshooting.

[0057] (6) Test Data Register (TDR): This register stores data transmitted during the boundary scan process. This data may include device status information, control commands, or other signals that need to be tested.

[0058] (7) The I / O cell is a key component connecting the internal logic of the chip with external pins (I / O pins), used to control and detect pin states and signals. The I / O cell is responsible for sending data processed in the internal logic to external pins, or receiving data from external pins and transmitting it to the internal logic. The I / O cell is often connected to a boundary scan register, allowing control and detection of pin level states (high or low) via the test access port (TAP). During testing, the I / O cell captures the state of the external pins based on control signals and stores the results in the boundary scan register.

[0059] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0060] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating the connection relationship between a boundary scan unit and an I / O unit provided in an embodiment of this application.

[0061] like Figure 1 As shown, the boundary scan unit includes two multiplexers (MUX) and two data flip triggers (DFF), wherein the first MUX is connected to the first DFF, the first DFF is connected to the second DFF, and the second DFF is connected to the second MUX.

[0062] When the Shift_DR signal is 1, the boundary scan chain (BSCAN chain) is activated, and the input data enters from the Sin signal and exits from the Sout signal. The Sin signal may come from the Sout or TDI port of the previous boundary scan unit (BCELL), and the Sout signal is transmitted to the Sin or TDO port of the next BCELL.

[0063] When the Shift_DR signal is 0, it is in the Capture state, and the data comes from the func path. At this time, the first register on the left can capture the value of the func path.

[0064] After `Update_DR` is executed, the second register acquires the value of the first register. If `select_jtag_output` is 1 at this point, the second BCELL register takes over the control signals of the right-hand I / O cell. If `select_jtag_output` is 0, the I / O cell is controlled by the `func` path. It's important to note that `select_jtag_output` is only 1 under certain JTAG instructions, such as the `EXTEST` and `CLAMP` instructions; otherwise, the `select_jtag_output` signal is 0. For example, under the `INTEST` instruction, the `select_jtag_output` signal is 0. This is understandable, as the `INTEST` instruction is one of the standard instructions defined in IEEE 1149.1 JTAG, and standard JTAG circuit code will configure the `INTEST` instruction to set `select_jtag_output` to 0.

[0065] Table 1 below shows the values ​​of select_jtag_input and select_jtag_output for some standard JTAG commands.

[0066] select_jtag_input select_jtag_output selected mode 0 0 SAMPLE 0 1 EXTEST 1 0 INTEST 0 0 PRELOAD

[0067] Table 1

[0068] Currently, I / O states are typically implemented using the IEEE 1149.1 standard Boundary Scan Cell (BSC). However, after the BSC takes over the control of I / O, configuring JTAG to other IR commands will cause the select_jtag_output signal to become 0, and the BSC will no longer control the I / O cell.

[0069] like Figure 1 As shown, the JTAG instruction is first configured as the INTEST instruction. At this time, select_jtag_output is 0, and the I / O is still handled by the func circuit. This is configured via JTAG. Figure 1 By configuring the JTAG state machine to Capture_DR->Exit1DR->Update_DR, the value in BCELL will match the value of func. Then, switching the IR instruction to EXTEST will set select_jtag_output to 1. At this point, BCELL takes over the control of the IO, maintaining the IO state. It can be understood that the func circuit is the functional circuit; that is, in normal operating mode, the DFT circuit is inactive, and the IO cell is taken over by the functional path. Figure 1 When select_jtag_output is 0, the second MUX is selected as 0, and the path at this time is the func circuit.

[0070] However, the problem with the above solution is that the IR instruction cannot be switched again, otherwise select_jtag_output will no longer be 1, thus exiting the IO state maintenance.

[0071] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of a select_jtag_output generation circuit provided in an embodiment of this application.

[0072] like Figure 2 As shown, the select_jtag_output signal and the select_jtag_output_int signal have the same value. After switching the IR instruction, the value of the select_jtag_output signal, that is, the value of the select_jtag_output signal is no longer 1, causing the boundary scan unit to no longer control the IO unit, thus exiting the IO state maintenance.

[0073] Because switching IR instructions prevents the use of the JTAG port to configure other TDR registers after the IO state is maintained, the scope of JTAG usage in this scenario is limited.

[0074] Based on this, embodiments of this application provide a signal generation circuit to maintain the IO state of the IO unit, thereby expanding the application scenarios of JTAG.

[0075] Please see Figure 3 , Figure 3 This is a schematic diagram of a signal generation circuit provided in an embodiment of this application.

[0076] like Figure 3 As shown, the signal generation circuit 100 includes a two-input OR gate module 101, a first data trigger module 102, a three-input OR gate module 103, and a second data trigger module 104.

[0077] The two-input OR gate module 101 is connected to the first data trigger module 102. The inputs of the two-input OR gate module 101 are the first IO signal and the output of the first data trigger module 102, namely the second IO signal. The first IO signal and the second IO signal are input to the two-input OR gate module 101, and the two-input OR gate module 101 outputs a first level signal to the first data trigger module 102.

[0078] The first data trigger module 102 is connected to the two-input OR gate module 101 and the three-input OR gate module 103. The input of the first data trigger module 102 is a first level signal, and the output of the first data trigger module 102 is a second IO signal. That is, the first data trigger module 102 outputs the second IO signal to the three-input OR gate module 103 and the two-input OR gate module 101.

[0079] The three-input OR gate module 103 is connected to the first data trigger module 102 and the second data trigger module 104. The inputs of the three-input OR gate module 103 are the initial selection signal, the first IO signal and the second IO signal, and the output of the three-input OR gate module 103 is the second level signal.

[0080] The second data trigger module 104 is connected to the three-input OR gate module 103. The input of the second data trigger module 104 is a second level signal, and the output of the second data trigger module 104 is a selection signal.

[0081] It is understandable that when the selection signal is a high-level signal, the IO state of the IO unit is controlled by the boundary scan unit.

[0082] In this embodiment, the first IO signal is set to a high level signal, which makes the first level signal a high level signal, makes the second level signal a high level signal, and thus makes the selection signal a high level signal. This allows the IO state of the IO unit to be controlled by the boundary scan unit. Furthermore, when switching IR instructions in JTAG, the selection signal can still be maintained as a high level signal, thereby maintaining the IO state of the IO unit and expanding the application scenarios of JTAG.

[0083] In this embodiment, the second IO signal output by the first data trigger module 102 is input to the two-input OR gate module 101; the selection signal corresponds to an initial selection signal, and the initial selection signal and the first IO signal are input to the three-input OR gate module 103.

[0084] In this embodiment, the boundary scan circuit includes a test access port controller (TAP controller). It is understood that the TAP controller is used to send instructions and data to the boundary scan unit, which performs the corresponding operation and returns the result.

[0085] After the boundary scan circuit executes the I / O instruction, and when the test access port controller is in a specific state, the first I / O signal is set to a high level; wherein the specific state includes the Update_IR state.

[0086] Specifically, the IO instructions include the IOHOLD instruction. When the boundary scan circuit executes the IOHOLD instruction and the test access port controller is in the Update_IR state, the first IO signal is set to a high level signal, and the first IO signal is input to the first data trigger module, so that the second IO signal output by the first data trigger module is also a high level signal.

[0087] Subsequently, the first IO signal, the second IO signal, and the initial selection signal are input to the three-input OR gate module. Since the first IO signal and the second IO signal are both high-level signals, the output of the three-input OR gate module is always a high-level signal, regardless of whether the initial selection signal is high-level or low-level. That is, the second level signal is always a high-level signal, which makes the selection signal output by the second data trigger module always a high-level signal, so that the IO unit is always controlled by the boundary scan unit, thereby realizing IO retention.

[0088] In this embodiment, the two-input OR gate module includes a two-input OR gate circuit, the first data trigger module includes a first data flip-flop, the three-input OR gate module includes a three-input OR gate circuit, the second data trigger module includes a second data flip-flop, and the selection signal includes a select_jtag_output signal, which is output by the second data flip-flop. When the select_jtag_output signal is high, the IO state of the IO unit is controlled by the boundary scan unit. Specifically, when the select_jtag_output signal is high, the boundary scan unit controls the IO pins of the IO unit, for example, by sending input data or status information to the I / O pins of the IO unit, or by setting the I / O pins to high or low to control the state of external devices, enabling the boundary scan unit to directly operate and interact with the I / O pins.

[0089] Understandably, the select_jtag_output signal is typically used to select the data to be output from the JTAG interface. The select_jtag_output signal determines which signals or data should be sent to the output of the JTAG interface. By selecting different output signals, testers can monitor different circuit states or logic results.

[0090] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of another signal generation circuit provided in an embodiment of this application;

[0091] like Figure 4As shown, the inputs of the two-input OR gate are the IOHOLD_decoded signal and the iohold_int signal. When the Test Access Port Controller (TAP Controller) is in the Update_IR state, the signal output by the two-input OR gate is saved to the first data flip-flop, and the iohold_int signal output by the first data flip-flop is input to the three-input OR gate. When the Test Access Port Controller (TAP Controller) is in the Update_IR state, the signal output by the three-input OR gate is input to the second data flip-flop, and the second data flip-flop outputs the select_jtag_output signal.

[0092] In this embodiment, by employing a new instruction IOHOLD, after the boundary scan circuit executes the IO instruction and the TAP controller executes the Update_IR state, IOHOLD_decoded will be set to 1, and iohold_int will also be set to 1. Even if select_jtag_output_int and IOHOLD_decoded become 0 due to switching to other IR instructions, select_jtag_output will still be kept stable at 1, ensuring that IO is always controlled by BCELL, thereby achieving IO retention.

[0093] In the embodiments of this application, the first data flip-flop includes a D flip-flop (DFF), and the second data flip-flop includes a D flip-flop (DFF). It can be understood that a D flip-flop is a flip-flop with a data input terminal, and its state is determined by the signal at the data input terminal. When the rising edge of the flip-flop's clock signal arrives, the D flip-flop stores the signal at the data input terminal into the flip-flop, thereby achieving information storage.

[0094] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of another signal generation circuit provided in the embodiments of this application.

[0095] like Figure 5As shown, the inputs of the two-input OR gate are the IOHOLD_decoded signal and the iohold_int signal. When the Test Access Port Controller (TAP Controller) is in the Update_IR state, the signal output by the two-input OR gate is saved to the first DFF. The iohold_int signal output by the first DFF is input to the two-input OR gate and the three-input OR gate. When the Test Access Port Controller (TAP Controller) is in the Update_IR state, the signal output by the three-input OR gate is input to the second DFF, and the second DFF outputs the select_jtag_output signal.

[0096] Among them, the two-input OR gate has two input terminals and one output terminal. The input signals of the two input terminals are IOHOLD_decoded signal and iohold_int signal, respectively. The output signal of the one output terminal is the signal after ORing the IOHOLD_decoded signal and iohold_int signal. For example, when at least one of the IOHOLD_decoded signal and iohold_int signal is a high-level signal (1), the signal after ORing the two signals is a high-level signal (1).

[0097] Among them, the three-input OR gate has three input terminals and one output terminal. The input signals of the three input terminals are select_jtag_output_int signal, IOHOLD_decoded signal and iohold_int signal respectively. When at least one of the select_jtag_output_int signal, IOHOLD_decoded signal and iohold_int signal is a high level signal (1), the signal after the three signals are ORed is a high level signal (1).

[0098] It is understandable that when IOHOLD_decoded is 1 and Update_IR is executed, the signal generation circuit can keep the iohold_int signal always 1. After passing through the three-input OR gate, the output select_jtag_output of the second DFF is kept at 1, thereby maintaining the state of IO.

[0099] It is understood that the signal generation circuit in this application embodiment can be used to maintain the I / O state when performing a scan dump on the chip's product board. Here, scan dump refers to dumping or outputting information about the chip's internal state or test results to the outside for analysis, debugging, or verification.

[0100] In this embodiment, since the IO state of the IO unit is maintained only through the boundary scan unit, the IO unit itself does not need to have IO retention function, thereby avoiding the need to insert additional latches to occupy more area, thus reducing costs. Furthermore, without using the IOHOLD instruction, it can be fully compatible with the original JTAG function and does not affect the use of the original JTAG, thereby expanding the application scenarios of JTAG.

[0101] It should be noted that the implementation steps for IO retention in this application are as follows: steps (1)-(3):

[0102] Step (1): Configure JTAG IR instructions and execute the INTEST instruction to make select_jtag_output 0.

[0103] Step (2): Configure the state machine of JTAG to Capture_DR->Exit1DR->Update_DR, so that BCELL captures the current state of IO.

[0104] Step (3): Configure the JTAG IR instruction and execute the newly added IOHOLD instruction. At this time, select_jtag_output is always 1 and no longer changes with the IR instruction. IO is always controlled by BCELL, thus realizing the IO retention function.

[0105] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of the structure of a boundary scanning unit provided in an embodiment of this application.

[0106] like Figure 6 As shown, the boundary scanning unit 200 includes a signal generation circuit 100.

[0107] It is understood that the boundary scan unit 200 may also include a data input register, a data output register, a boundary scan register, etc., which will not be described in detail here.

[0108] Please refer to the following: Figure 7 , Figure 7 This is a schematic diagram of a boundary scan circuit provided in an embodiment of this application.

[0109] like Figure 7As shown, the boundary scan circuit 500 includes a test access port controller 400, a boundary scan unit 200, and an I / O unit 300, wherein the test access port controller 400 is connected to the boundary scan unit 200 and the I / O unit 300 respectively.

[0110] It is understood that there can be multiple boundary scan units 200 in this embodiment, which are connected in series to form a boundary scan chain. The test access port controller 400 connects to each boundary scan unit 200 to enable the transmission of test signals and control signals between the TAP controller and the boundary scan units. The TAP controller controls the operating mode (e.g., normal operating mode or test mode) of each boundary scan unit according to the received control signals, enabling it to receive or send data accordingly. For example, the TAP controller selects a specific test mode via the TMS signal and configures each boundary scan unit for testing. In test mode, test data is input via TDI, and the data passes through each boundary scan unit, is transmitted under the control of the TCK clock, and is finally output via TDO. The TAP controller can monitor the status of the boundary scan units to ensure that each unit can transmit data correctly and identify potential faults in a timely manner.

[0111] Please refer to the following: Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0112] like Figure 8 As shown, the electronic device 600 includes a boundary scan circuit 500.

[0113] In this embodiment, electronic device 600 refers to any device containing electronic components and circuits that utilizes boundary scan technology for testing and fault diagnosis to ensure its normal operation and high performance. For example, electronic device 600 can be an automated test device, such as a boundary scan test device, like an ATE (Automated Test Equipment) machine.

[0114] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

Claims

1. A signal generation circuit, characterized in that, Applied to a boundary scanning circuit, the boundary scanning circuit includes a boundary scanning unit and an I / O unit, the boundary scanning unit being connected to the I / O unit, wherein the signal generation circuit includes: A two-input OR gate module is used to input a first IO signal to output a first level signal; The first data trigger module is connected to the two-input OR gate module and is used to receive the first level signal output by the two-input OR gate module in order to output the second IO signal. A three-input OR gate module is connected to the first data trigger module and is used to receive the second IO signal output by the first data trigger module in order to output a second level signal. The second data trigger module is connected to the three-input OR gate module and is used to receive the second level signal output by the three-input OR gate module to output a selection signal. When the selection signal is a high level signal, the IO state of the IO unit is controlled by the boundary scan unit. Wherein, the first IO signal is set to a high level signal, so that the first level signal is a high level signal, the second level signal is a high level signal, and thus the selection signal is a high level signal.

2. The signal generation circuit according to claim 1, characterized in that, The second I / O signal output by the first data trigger module is input to the two-input OR gate module; The selection signal corresponds to an initial selection signal, and the initial selection signal and the first IO signal are input to the three-input OR gate module.

3. The signal generation circuit according to claim 1, characterized in that, The boundary scan circuit includes a test access port controller; After the boundary scan circuit executes the I / O instruction, and when the test access port controller is in a specific state, the first I / O signal is set to a high level signal; The specific state includes the Update_IR state.

4. The signal generation circuit according to claim 1, characterized in that, The first data triggering module includes a first data trigger, which includes a D trigger; The second data triggering module includes a second data trigger, which includes a D trigger.

5. The signal generation circuit according to claim 4, characterized in that, The selection signal includes the select_jtag_output signal, which is output by the second data trigger. When the select_jtag_output signal is high, the IO state of the IO unit is controlled by the boundary scan unit.

6. The signal generation circuit according to any one of claims 1-5, characterized in that, The two-input OR gate module includes a two-input OR gate circuit, and the two-input OR gate circuit includes a multiplexer. The three-input OR gate module includes a three-input OR gate circuit, which includes a multiplexer.

7. A boundary scanning unit, characterized in that, include: The signal generation circuit as described in any one of claims 1-6.

8. A boundary scan circuit, characterized in that, include: I / O unit; The boundary scanning unit as described in claim 7 is connected to the IO unit and is used to control the IO state of the IO unit.

9. An electronic device, characterized in that, include: The boundary scan circuit as described in claim 8.

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