Ultrasonic echo detection circuit

Abstract

The utility model relates to the technical field of transducers, and discloses an ultrasonic echo detection circuit, comprising a common-mode module which is connected to a first echo input end and a second echo input end, receives a first input signal and a second input signal, and is used for carrying out common-mode processing on the first input signal and the second input signal and sending the processed signal to a processor; obtaining and outputting a first direct-current signal and a second direct-current signal; the amplification module is connected with the common-mode module, receives the first direct-current signal and the second direct-current signal, amplifies the first direct-current signal and the second direct-current signal respectively, and outputs the amplified first direct-current signal and the amplified second direct-current signal; and the filtering module is respectively connected with the amplification module and the echo output end, receives the amplified first direct current signal and the amplified second direct current signal, filters common-mode signals for the amplified first direct current signal and the amplified second direct current signal to obtain a differential signal, and outputs the differential signal to the echo output end. The problems that detected ultrasonic echo signals are large in signal noise and low in integrity are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to transducer technical field, concretely relates to ultrasonic echo detection circuit. BACKGROUND

[0002] With the development of science and technology, transducer is widely used. The transducer includes a piezoelectric ceramic module, which generates vibration through outputting an alternating current signal to output ultrasonic waves. When the ultrasonic waves are reflected back, the piezoelectric ceramic vibrates again. Through the reflected ultrasonic echo, the time difference between the output ultrasonic waves is detected, so that the distance is detected through the time difference.

[0003] However, the existing ultrasonic echo detection circuit generally adopts a single-ended collection mode, resulting in large signal noise and low integrity. UTILITY MODEL CONTENTS

[0004] Therefore, the utility model provides an ultrasonic echo detection circuit to solve the problem of large signal noise and low integrity of the detected ultrasonic echo signal in the prior art.

[0005] In a first aspect, the utility model provides an ultrasonic echo detection circuit, which comprises:

[0006] A common mode module is connected to the first echo input end and the second echo input end. The common mode module is used to receive the first input signal and the second input signal. After common mode processing of the first input signal and the second input signal, the common mode module outputs the first direct current signal and the second direct current signal.

[0007] An amplification module is connected to the common mode module. The amplification module receives the first direct current signal and the second direct current signal, and outputs the first direct current signal and the second direct current signal after amplification.

[0008] A filter module is connected to the amplification module and the echo output end. The filter module receives the amplified first direct current signal and the amplified second direct current signal, filters the common mode signal of the amplified first direct current signal and the amplified second direct current signal, and outputs the differential signal to the echo output end.

[0009] The ultrasonic echo detection circuit provided by the utility model obtains first input signal through first echo input end, and obtains second input signal through second echo input end, common mode module carries out common mode processing to first input signal and second input signal, obtains first direct current signal and second direct current signal respectively, amplification module transmits to filter out module after amplifying first direct current signal and second direct current signal, filter out module filters out common mode signal in first direct current signal and second direct current signal, obtains differential signal, finally transmits differential signal to echo output end, obtain signal through measuring voltage difference between two input ends, instead of relative to ground, improve the effect of inhibiting noise, and reduce the error of signal caused by noise, at the same time, filter out after superimposing common mode signal, guarantee the integrity of signal, reduce the interference of electromagnetic wave in signal transmission process.

[0010] In an alternative embodiment, the common mode module comprises:

[0011] a first resistor, a first end of the first resistor being connected with the first echo input end, and a second end of the first resistor being connected with a preset reference voltage;

[0012] a second resistor, a first end of the second resistor being connected with the second echo input end, and a second end of the second resistor being connected with the second end of the first resistor;

[0013] a third resistor, a first end of the third resistor being connected with the first echo input end, and a second end of the third resistor being grounded;

[0014] a fourth resistor, a first end of the fourth resistor being connected with the second echo input end, and a second end of the fourth resistor being connected with the second end of the third resistor.

[0015] In an alternative embodiment, the common mode module further comprises:

[0016] a fifth resistor, a first end of the fifth resistor being connected with the preset reference voltage and the second end of the first resistor respectively;

[0017] a first capacitor, a first end of the first capacitor being connected with a second end of the fifth resistor, a second end of the first capacitor being connected with the second end of the third resistor, and being grounded.

[0018] In an alternative embodiment, the amplification module comprises:

[0019] a first amplification unit, a first input end of the first amplification unit being connected with the common mode module, an output end of the first amplification unit being connected with the filter out module, the first amplification unit being used for outputting after amplifying the first direct current signal;

[0020] a second amplification unit, a first input end of the second amplification unit being connected with the common mode module, an output end of the second amplification unit being connected with a filter-out module, the second amplification unit being used for amplifying and outputting a second direct current signal;

[0021] a gain adjustment unit, the gain adjustment unit being connected between a second input end of the first amplification unit and a second input end of the second amplification unit, the gain adjustment unit being used for adjusting an amplification gain.

[0022] In an alternative implementation, the first amplification unit and the second amplification unit each comprise:

[0023] a first operational amplifier, a first input end of the first operational amplifier being connected with the common mode module, a second input end of the first operational amplifier being connected with the gain adjustment unit;

[0024] a sixth resistor, a first end of the sixth resistor being connected with an output end of the first operational amplifier, a second end of the sixth resistor being connected with the gain adjustment unit;

[0025] a second capacitor, a first end of the second capacitor being connected with the output end of the first operational amplifier, a second end of the second capacitor being connected with the gain adjustment unit.

[0026] In an alternative implementation, the gain adjustment unit comprises:

[0027] a seventh resistor, a first end of the seventh resistor being connected with the second input end of the first operational amplifier;

[0028] a third capacitor, a first end of the third capacitor being connected with a second end of the seventh resistor;

[0029] an eighth resistor, a first end of the eighth resistor being connected with a second end of the third capacitor, a second end of the eighth resistor being connected with the second input end of the first operational amplifier.

[0030] In an alternative implementation, the filter-out module comprises:

[0031] a common mode filter-out unit, the common mode filter-out unit being connected with the amplification module, the common mode filter-out unit receiving the amplified first direct current signal and the amplified second direct current signal respectively, the common mode filter-out unit filtering out a common mode signal for the amplified first direct current signal and the amplified second direct current signal to obtain a common mode filter-out signal and output the common mode filter-out signal;

[0032] an adjustment unit, the adjustment unit being connected with the common mode filter-out unit and a echo output end respectively, the adjustment unit being used for adjusting the common mode filter-out signal to obtain a differential signal and outputting the differential signal to the echo output end.

[0033] In an alternative embodiment, the common mode rejection unit comprises:

[0034] a first inductor, a first end of the first inductor is configured to receive the amplified first DC signal, a second end of the first inductor is configured to receive the amplified second DC signal;

[0035] a fourth capacitor, a first end of the fourth capacitor is connected to the first end of the first inductor, a second end of the fourth capacitor is connected to the second end of the first inductor;

[0036] a logarithmic amplifier, a first input of the logarithmic amplifier is connected to the first end of the first inductor, a second input of the logarithmic amplifier is connected to the second end of the fourth capacitor, an output of the logarithmic amplifier is connected to the adjusting unit.

[0037] In an alternative embodiment, the adjusting unit comprises:

[0038] a second operational amplifier, a first input of the second operational amplifier is connected to the output of the logarithmic amplifier, an output of the second operational amplifier is connected to the echo output;

[0039] a ninth resistor, a first end of the ninth resistor is connected to a second input of the second operational amplifier, a second end of the ninth resistor is grounded;

[0040] a tenth resistor, a first end of the tenth resistor is connected to the second input of the second operational amplifier, a second end of the tenth resistor is connected to the output of the second operational amplifier.

[0041] In an alternative embodiment, the ultrasonic echo detection circuit comprises:

[0042] a overvoltage protection module composed of diodes, a first end of the overvoltage protection module is connected to the first echo input, a second end of the overvoltage protection module is connected to the second echo input, the overvoltage protection module is configured to protect the ultrasonic echo detection circuit when the first input signal and / or the second input signal is overvoltage.

[0043] The overvoltage protection module comprises: two protection units, the protection unit comprises:

[0044] a first diode, an anode of the first diode is connected to the first echo input;

[0045] a second diode, a cathode of the second diode is connected to the second echo input, an anode of the second diode is connected to a cathode of the first diode;

[0046] a third diode, a cathode of the third diode is connected with the first echo input end, and an anode of the third diode is connected with a cathode of the first diode;

[0047] a fourth diode, an anode of the fourth diode is connected with the second echo input end, and a cathode of the fourth diode is connected with the cathode of the first diode. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0049] Figure 1 is a structure diagram of an ultrasonic echo detection circuit according to an embodiment of the present application;

[0050] Figure 2 is a structure diagram of a common mode module in an ultrasonic echo detection circuit according to an embodiment of the present application;

[0051] Figure 3 is a structure diagram of an amplification module of an ultrasonic echo detection circuit according to an embodiment of the present application;

[0052] Figure 4 is a detailed structure diagram of an amplification module of an ultrasonic echo detection circuit according to an embodiment of the present application;

[0053] Figure 5 is a structure diagram of a filtering module of an ultrasonic echo detection circuit according to an embodiment of the present application;

[0054] Figure 6 is a detailed structure diagram of a filtering module of an ultrasonic echo detection circuit according to an embodiment of the present application;

[0055] Figure 7 is a structure diagram of another ultrasonic echo detection circuit according to an embodiment of the present application.

[0056] BRIEF DESCRIPTION OF DRAWINGS

[0057] 10 - common mode module; 20 - amplification module; 30 - filter module; 21 - amplification unit; 22 - gain adjustment unit; 23 - second amplification unit; 31 - common mode filter module; 32 - adjustment unit; 40 - overvoltage protection module; R1 - first resistor; R2 - second resistor; R3 - third resistor; R4 - fourth resistor; R5 - fifth resistor; R6 - sixth resistor; R7 - seventh resistor; R8 - eighth resistor; R9 - ninth resistor; R10 - tenth resistor; R11 - eleventh resistor; R12 - twelfth resistor; R13 - thirteenth resistor; R14 - fourteenth resistor; R15 - fifteenth resistor; R16 - sixteenth resistor; R17 - seventeenth resistor; R18 - eighteenth resistor; C1 - first capacitor; C2 - second capacitor; C3 - third capacitor; C4 - fourth capacitor; C5 - fifth capacitor; C6 - sixth capacitor; C7 - seventh capacitor; C8 - eighth capacitor; C9 - ninth capacitor; C10 - tenth capacitor; C11 - eleventh capacitor; C12 - twelfth capacitor; A1 - first operational amplifier; A2 - second operational amplifier; U1 - logarithmic amplifier; L1 - first inductor; D1 - first diode; D2 - second diode; D3 - third diode; D4 - fourth diode. DETAILED DESCRIPTION

[0058] The technical solutions of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0059] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0060] In the description of the utility model, it is necessary to explain that, unless there is definite stipulation and limitation, the term ''installation'', ''connection'' should be understood in a broad sense, for example, it can be fixed connection, also can be detachable connection, or integrally connected, can be mechanical connection, also can be electrical connection, can be direct connection, also can be indirect connection through intermediate medium, also can be the intercommunication of two elements, can be wireless connection, also can be wired connection, for ordinary skilled in the art, the specific meaning of the above-mentioned term in the utility model can be understood according to specific circumstances.

[0061] In addition, the technical features involved in the different embodiments of the utility model described below can be combined with each other as long as there is no conflict between them.

[0062] With the development of science and technology, transducers are widely used. The transducer includes a piezoelectric ceramic module, which generates vibration by outputting an alternating signal to output an ultrasonic wave. When the ultrasonic wave is reflected back, the piezoelectric ceramic vibrates again, and the time difference between the output ultrasonic wave and the reflected ultrasonic echo is detected, so that the distance is detected by the time difference.

[0063] However, the existing ultrasonic echo detection circuit generally adopts a single-ended collection mode, resulting in large signal noise and low integrity.

[0064] To this end, the present embodiment provides an ultrasonic echo detection circuit, as shown in Figure 1 The ultrasonic echo detection circuit comprises:

[0065] A common mode module 10 is connected to a first echo input end IN+ and a second echo input end IN-, the common mode module 10 is used to receive a first input signal and a second input signal, and the common mode module 10 is used to obtain a first direct current signal and a second direct current signal after common mode processing of the first input signal and the second input signal and output;

[0066] Specifically, the common mode module 10 superimposes the same preset direct current component on the first input signal and the second input signal respectively, so that a common mode signal is generated between the first input signal and the second input signal, so that the first direct current signal is obtained after superimposing the preset direct current component on the first input signal, and the second direct current signal is obtained after superimposing the preset direct current component on the second input signal. Thus, the originally opposite first input signal and second input signal are in the same direction after superimposing the same preset direct current component, and then all signals of the first input signal and the second input signal are in an effective state, so that the effective signal range is wider, and finally a more accurate echo signal is obtained. Optionally, the common mode module 10 can be a circuit for superimposing a direct current signal on the first input signal and the second input signal respectively.

[0067] It should be noted that the first direct current signal and the second direct current signal are both superimposed signals of the differential signal and the common mode signal.

[0068] An amplification module 20 is connected with the common mode module 10, used for receiving the first direct current signal and the second direct current signal, and respectively amplifying the first direct current signal and the second direct current signal and then outputting;

[0069] Specifically, the amplification module 20 can amplify the first direct current signal and the second direct current signal respectively, and can calculate the size of the amplified first direct current signal and the amplified second direct current signal respectively. Optionally, the amplification module 20 can be an instrument amplification circuit.

[0070] A filtering module 30 is respectively connected with the amplification module 20 and the echo output end OUT, used for receiving the amplified first direct current signal and the amplified second direct current signal, filtering the common mode signal from the amplified first direct current signal and the amplified second direct current signal to obtain a differential signal, and outputting the differential signal to the echo output end OUT.

[0071] Specifically, the filtering module 30 can filter the common mode signal from the amplified first direct current signal and the amplified second direct current signal to only keep the differential signal. Meanwhile, the filtering module 30 can be an amplification circuit, that is, the common mode signal is filtered while being amplified. In addition, the filtering module 30 can further include a circuit for further adjusting the filtered differential signal. Thus, the adjusted differential signal is within a preset range.

[0072] The ultrasonic echo detection circuit provided by the utility model obtains a first input signal through a first echo input end and a second input signal through a second echo input end, the common mode module 10 performs common mode processing on the first input signal and the second input signal to obtain a first direct current signal and a second direct current signal respectively, the amplification module 20 amplifies the first direct current signal and the second direct current signal and then transmits to the filtering module 30, the filtering module 30 filters the common mode signal in the first direct current signal and the second direct current signal to obtain a differential signal, and finally transmits the differential signal to the echo output end OUT. The voltage difference between the two input ends is measured to obtain the signal, instead of the ground end, which improves the noise suppression effect, reduces the error caused by noise to the signal, and at the same time, through the filtering after superimposing the common mode signal, the integrity of the signal is ensured, and the interference of electromagnetic waves in the signal transmission process is reduced.

[0073] In some optional embodiments, as shown in Figure 2 The common mode module 10 includes:

[0074] a first resistor R1, a first end of the first resistor R1 is connected with the first echo input end IN+, and a second end of the first resistor R1 is connected with a preset reference voltage VDD;

[0075] a second resistor R2, a first end of the second resistor R2 is connected with the second echo input end IN-, and a second end of the second resistor R2 is connected with the second end of the first resistor R1;

[0076] a third resistor R3, a first end of the third resistor R3 is connected with the first echo input end IN+, and a second end of the third resistor R3 is grounded;

[0077] a fourth resistor R4, a first end of the fourth resistor R4 is connected with the second echo input end IN-, and a second end of the fourth resistor R4 is connected with the second end of the third resistor R3.

[0078] Specifically, referring to Figure 2 , the preset reference voltage VDD of direct current flows into the ground end through the first resistor R1 and the third resistor R3, at this time, if the resistance values of the first resistor R1 and the third resistor R3 are the same, half components of the preset reference voltage VDD of direct current are superimposed to the first echo input end IN+. And, if the resistance values of the second resistor R2 and the third resistor R3 are the same, half components of the preset reference voltage VDD of direct current are superimposed to the second echo input end IN-. Thus, the same direct current signal is superimposed on the first input signal and the second input signal to generate common mode signals on the first input signal and the second input signal respectively.

[0079] In some optional embodiments, as Figure 2 shown, the common mode module 10 further comprises:

[0080] a fifth resistor R5, a first end of the fifth resistor R5 is connected with the preset reference voltage VDD and the second end of the first resistor R1 respectively;

[0081] a first capacitor C1, a first end of the first capacitor C1 is connected with a second end of the fifth resistor R5, a second end of the first capacitor C1 is connected with the second end of the third resistor R3 and grounded.

[0082] Specifically, the preset reference voltage VDD is connected to the ground end through the fifth resistor R5 and the first capacitor C1, and the first capacitor C1 plays a filtering role. Since the resistance of the fifth resistor R5 is small, the voltage drop generated is also small, which is equivalent to half components of the preset reference voltage VDD being superimposed to the first input signal and the second input signal respectively, and the fifth resistor R5 plays a buffering role.

[0083] In addition, referring to Figure 2The common-mode module 10 further comprises a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, the fifth capacitor C5 and the sixth capacitor C6 filter the voltage of the divided voltage, and the seventh capacitor C7 and the eighth capacitor C8 filter the first DC signal and the second DC signal respectively.

[0084] In some alternative embodiments, as shown in FIG. 2, the amplification module 20 comprises: Figure 3

[0085] a first amplification unit 21, a first input end of the first amplification unit 21 being connected with the common-mode module 10, an output end of the first amplification unit 21 being connected with the filter module 30, the first amplification unit being configured to amplify and output the first DC signal;

[0086] a second amplification unit 22, a first input end of the second amplification unit 22 being connected with the common-mode module 10, an output end of the second amplification unit 22 being connected with the filter module 30, the second amplification unit being configured to amplify and output the second DC signal;

[0087] a gain adjustment unit 23, the gain adjustment unit 23 being connected between a second input end of the first amplification unit 21 and a second input end of the second amplification unit 22, the gain adjustment unit 23 being configured to adjust the gain of amplification.

[0088] Specifically, the first amplification unit 21, the second amplification unit 22 and the gain adjustment unit 23 constitute an instrumentation amplifier circuit, the first amplification unit 21 is configured to amplify the first DC signal, the second amplification unit 22 is configured to amplify the second DC signal, and the gain adjustment unit 23 is configured to adjust the gain of amplification of the first DC signal and the second DC signal.

[0089] In some alternative embodiments, as shown in FIG. 2, the first amplification unit 21 and the second amplification unit 22 each comprise: Figure 4

[0090] a first operational amplifier A1, a first input end of the first operational amplifier A1 being connected with the common-mode module 10, a second input end of the first operational amplifier A1 being connected with the gain adjustment unit 23;

[0091] a sixth resistor R6, a first end of the sixth resistor R6 being connected with an output end of the first operational amplifier A1, a second end of the sixth resistor R6 being connected with the gain adjustment unit 23;

[0092] a second capacitor C2, a first end of the second capacitor C2 being connected with the output end of the first operational amplifier A1, a second end of the second capacitor C2 being connected with the gain adjustment unit 23. ​​

[0093] Specifically, the first amplification unit 21 and the second amplification unit 22 each further include a ninth capacitor C9, a tenth capacitor C10, an eleventh resistor R11 and a twelfth resistor R12. The ninth capacitor C9 and the eleventh resistor R11 constitute an RC filter circuit. The second input end of the first operational amplifier A1 is attenuated and phase compensated through the ninth capacitor C9 and the eleventh resistor R11, so as to have sufficient margin, and the signal size is not attenuated due to the very low cutoff rate controlled by RC. The tenth capacitor C10 and the twelfth resistor R12 constitute a high-pass filter, and the amplified first direct current signal and the amplified second direct current signal are filtered at low frequency.

[0094] In some alternative embodiments, as shown in FIG. 3, the gain adjustment unit 23 includes: Figure 4

[0095] a seventh resistor R7, a first end of the seventh resistor R7 being connected with the second input end of the first operational amplifier A1;

[0096] a third capacitor C3, a first end of the third capacitor C3 being connected with a second end of the seventh resistor R7;

[0097] an eighth resistor R8, a first end of the eighth resistor R8 being connected with a second end of the third capacitor C3, and a second end of the eighth resistor R8 being connected with the second input end of the first operational amplifier A1.

[0098] Specifically, the third capacitor C3 is used to isolate the first amplification unit 21 and the second amplification unit 22. It should be understood that the seventh resistor R7 and the eighth resistor R8 can be simplified as one resistor, or can be constituted by a plurality of resistors in series and / or in parallel.

[0099] Referring to FIG. 4, Figure 4 Figure 4 V1, V2, V3 and V4 are marked in the figure, wherein V3 can be the amplified first direct current signal, and V4 can be the amplified second direct current signal. V3 can be obtained by the formula First, the capacitive reactance RC3 and RC2 of the third capacitor C3 and the second capacitor C2 are calculated. According to the virtual short and virtual open principle of the operational amplifier, the voltages at the first input end and the second input end of the first operational amplifier A1 are the same. Then, according to the current invariance equation, V3 can be obtained, and V4 can also be obtained according to the same principle.

[0100] In some alternative embodiments, as shown in FIG. 5, the filter module 30 includes: Figure 5

[0101] ​​​A common mode filtering unit 31 is connected with the amplification module 20, receives the amplified first DC signal and the amplified second DC signal respectively, filters the common mode signal for the amplified first DC signal and the amplified second DC signal, obtains a common mode filtering signal and outputs;

[0102] An adjusting unit 32 is connected with the common mode filtering unit 31 and the echo output end OUT respectively, adjusts the common mode filtering signal to obtain a differential signal, and outputs the differential signal to the echo output end OUT.

[0103] Specifically, the common mode filtering unit 31 is used to filter the common mode signal for the amplified first DC signal and the amplified second DC signal, and further amplify to obtain a differential signal. The adjusting unit 32 is used to further amplify or reduce the common mode filtering signal again, so as to adjust the differential signal again.

[0104] Optionally, the common mode filtering unit 31 can adopt logarithmic amplification or differential amplification.

[0105] In some optional embodiments, the common mode filtering unit 31 includes a differential amplifier. It can be understood that the differential amplifier filters the common mode signal of the amplified first DC signal and the amplified second DC signal by subtracting two signals, and further amplifies to obtain a differential signal.

[0106] In some optional embodiments, as shown in Figure 6 The common mode filtering unit 31 includes:

[0107] A first inductor L1, a first end of the first inductor L1 is used to receive the amplified first DC signal, and a second end of the first inductor L1 is used to receive the amplified second DC signal;

[0108] A fourth capacitor C4, a first end of the fourth capacitor C4 is connected with the first end of the first inductor L1, and a second end of the fourth capacitor C4 is connected with the second end of the first inductor L1;

[0109] A logarithmic amplifier U1, a first input end of the logarithmic amplifier U1 is connected with the first end of the first inductor L1, a second input end of the logarithmic amplifier U1 is connected with the second end of the fourth capacitor C4, and an output end of the logarithmic amplifier U1 is connected with the adjusting unit 32.

[0110] Specifically, the first inductor L1 and the fourth capacitor C4 constitute an LC resonant circuit, and by selecting a preset frequency signal, selective amplification and filtering of the logarithmic amplifier U1 are facilitated. In addition, the common-mode filtering unit 31 further comprises an eleventh capacitor C11, a thirteenth resistor R13 and a fourteenth resistor R14, which constitute a filtering circuit for performing a last filtering and smoothing process on the amplified first direct current signal and the amplified second direct current signal before entering the logarithmic amplifier U1, so as to output a suitable value through the logarithmic amplifier U1.

[0111] By adopting the logarithmic amplifier U1, the logarithmic amplifier U1 amplifies or reduces the signal in a logarithmic form, so that there is no deviation between the output differential signal and the ideal value, and the adjustment unit 32 is provided. The logarithmic amplifier U1 adopts a quotient filtering mode to filter the common-mode signal of the amplified first direct current signal and the amplified second direct current signal. When the amplified first direct current signal and the amplified second direct current signal are close to the upper limit, the amplification factor becomes smaller and smaller, thereby preventing the signal from being too large. At the same time, when the amplified first direct current signal and the amplified second direct current signal are very small, the amplification factor becomes smaller and smaller, thereby preventing the problem of the signal being too small.

[0112] In some optional embodiments, as shown in Figure 6 the adjustment unit 32 comprises:

[0113] a second operational amplifier A2, a first input terminal of the second operational amplifier A2 is connected with an output terminal of the logarithmic amplifier U1, and an output terminal of the second operational amplifier A2 is connected with the echo output terminal OUT;

[0114] a ninth resistor R9, a first end of the ninth resistor R9 is connected with a second input terminal of the second operational amplifier A2, and a second end of the ninth resistor R9 is grounded;

[0115] a tenth resistor R10, a first end of the tenth resistor R10 is connected with the second input terminal of the second operational amplifier A2, and a second end of the tenth resistor R10 is connected with the output terminal of the second operational amplifier A2.

[0116] Specifically, the second operational amplifier A2, the ninth resistor R9 and the tenth resistor R10 constitute a same-direction amplification circuit, so as to further adjust the differential signal and output to the echo output terminal OUT.

[0117] In addition, as shown in Figure 6 , Figure 6 V5, V6 and V7 are marked in the figure, wherein V7 is the adjusted differential signal. According to the principle of virtual short and virtual open, V5 = V6, and according to the current invariance equation, V7 is obtained. The adjusting unit 32 further comprises a thirteenth capacitor C13 and a fifteenth resistor R15 for supplying power to the second operational amplifier. The adjusting unit 32 further comprises a sixteenth resistor R16 for current limiting the adjusted differential signal to prevent damage to an ADC (analog-to-digital converter) or an MCU (Microcontroller Unit) connected to the echo output terminal OUT.

[0118] In some alternative embodiments, as shown in FIG. 2, the ultrasonic echo detection circuit comprises: Figure 7

[0119] A overvoltage protection module 40 composed of diodes, a first end of the overvoltage protection module 40 is connected to the first echo input terminal IN+, a second end of the overvoltage protection module 40 is connected to the second echo input terminal IN-, the overvoltage protection module is used to protect the ultrasonic echo detection circuit when the first input signal and / or the second input signal is overvoltage.

[0120] Specifically, when the voltage between the first echo input terminal IN+ and the second echo input terminal IN- is greater than the conduction voltage of the diode, it is equivalent to a short-circuit state, that is, high voltage will not enter the subsequent circuit. When the voltage between the first echo input terminal IN+ and the second echo input terminal IN- is less than the conduction voltage of the diode, it is equivalent to an open-circuit state, that is, low voltage will not enter the subsequent circuit, thereby playing a protection role. Alternatively, the overvoltage protection module 40 can be a forward diode and a reverse diode.

[0121] In some alternative embodiments, as shown in FIG. 2, the overvoltage protection module 40 comprises: Figure 7

[0122] A first diode D1, an anode of the first diode D1 is connected to the first echo input terminal IN+;

[0123] A second diode D2, a cathode of the second diode D2 is connected to the second echo input terminal IN-, an anode of the second diode D2 is connected to a cathode of the first diode D1;

[0124] A third diode D3, a cathode of the third diode D3 is connected to the first echo input terminal IN+, an anode of the third diode D3 is connected to the cathode of the first diode D1;

[0125] A fourth diode D4, an anode of the fourth diode D4 is connected to the second echo input terminal IN-, a cathode of the fourth diode D4 is connected to the cathode of the first diode D1. ​​

[0126] Specifically, by setting two protection units 41, the stability of the overvoltage protection is improved. When the voltage of the first echo input end IN+ and the second echo input end IN- is smaller, the current formed is smaller, and the voltage drop of the forward conduction is also smaller, so that the voltage signal obtained after the voltage drop is not too low. Therefore, the problem of low circuit protection capability and easy to cause the damage of the board circuit is solved.

[0127] In addition, the ultrasonic echo detection circuit further comprises a seventeenth resistor R17 and an eighteenth resistor R18, which function as current limiting resistors, limit the current flowing through the overvoltage protection module 40, prevent the forward current and pulse current of the overvoltage protection module 40 from exceeding, and damage the diode and the subsequent circuit.

[0128] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. An ultrasonic echo detection circuit, characterized by comprising: The ultrasonic echo detection circuit comprises: A common mode module connected to the first echo input end and the second echo input end, configured to receive the first input signal and the second input signal, and output the first DC signal and the second DC signal after common mode processing of the first input signal and the second input signal; An amplification module connected to the common mode module, configured to receive the first DC signal and the second DC signal, and output after amplifying the first DC signal and the second DC signal, respectively; A filtering module connected to the amplification module and the echo output end, configured to receive the amplified first DC signal and the amplified second DC signal, obtain the differential signal after filtering the common mode signal from the amplified first DC signal and the amplified second DC signal, and output the differential signal to the echo output end.

2. The ultrasonic echo detection circuit of claim 1, wherein, The common mode module comprises: A first resistor, a first end of the first resistor connected to the first echo input end, and a second end of the first resistor connected to a preset reference voltage; A second resistor, a first end of the second resistor connected to the second echo input end, and a second end of the second resistor connected to the second end of the first resistor; A third resistor, a first end of the third resistor connected to the first echo input end, and a second end of the third resistor grounded; A fourth resistor, a first end of the fourth resistor connected to the second echo input end, and a second end of the fourth resistor connected to the second end of the third resistor.

3. The ultrasonic echo detection circuit of claim 2, wherein, The common mode module further comprises: A fifth resistor, a first end of the fifth resistor connected to the preset reference voltage and the second end of the first resistor, respectively; A first capacitor, a first end of the first capacitor connected to a second end of the fifth resistor, a second end of the first capacitor connected to the second end of the third resistor, and grounded.

4. The ultrasonic echo detection circuit of claim 1, wherein, The amplification module comprises: A first amplification unit, a first input end of the first amplification unit connected to the common mode module, an output end of the first amplification unit connected to the filtering module, and the first amplification unit configured to output after amplifying the first DC signal; A second amplification unit, a first input end of the second amplification unit connected to the common mode module, an output end of the second amplification unit connected to the filtering module, and the second amplification unit configured to output after amplifying the second DC signal; A gain adjustment unit connected between a second input end of the first amplification unit and a second input end of the second amplification unit, and configured to adjust the gain of amplification.

5. The ultrasonic echo detection circuit of claim 4, wherein, The first amplification unit and the second amplification unit each comprise: A first operational amplifier, a first input end of the first operational amplifier connected to the common mode module, and a second input end of the first operational amplifier connected to the gain adjustment unit; A sixth resistor, a first end of the sixth resistor connected to an output end of the first operational amplifier, and a second end of the sixth resistor connected to the gain adjustment unit; A second capacitor, a first end of the second capacitor is connected with an output end of the first operational amplifier, and a second end of the second capacitor is connected with the gain adjusting unit.

6. The ultrasonic echo detection circuit of claim 5, wherein, The gain adjusting unit comprises: A seventh resistor, a first end of the seventh resistor is connected with a second input end of the first operational amplifier; A third capacitor, a first end of the third capacitor is connected with a second end of the seventh resistor; An eighth resistor, a first end of the eighth resistor is connected with a second end of the third capacitor, and a second end of the eighth resistor is connected with the second input end of the first operational amplifier.

7. The ultrasonic echo detection circuit of claim 3, wherein, The filtering module comprises: A common-mode filtering unit, the common-mode filtering unit is connected with the amplifying module, the common-mode filtering unit receives the amplified first direct current signal and the amplified second direct current signal respectively, and obtains common-mode filtered signals by filtering common-mode signals of the amplified first direct current signal and the amplified second direct current signal, and outputs the common-mode filtered signals; An adjusting unit, the adjusting unit is connected with the common-mode filtering unit and a echo output end respectively, and is used for adjusting the common-mode filtered signals to obtain differential signals, and outputting the differential signals to the echo output end.

8. The ultrasonic echo detection circuit of claim 7, wherein, The common-mode filtering unit comprises: A first inductor, a first end of the first inductor is used for receiving the amplified first direct current signal, and a second end of the first inductor is used for receiving the amplified second direct current signal; A fourth capacitor, a first end of the fourth capacitor is connected with the first end of the first inductor, and a second end of the fourth capacitor is connected with the second end of the first inductor; A logarithmic amplifier, a first input end of the logarithmic amplifier is connected with the first end of the first inductor, a second input end of the logarithmic amplifier is connected with the second end of the fourth capacitor, and an output end of the logarithmic amplifier is connected with the adjusting unit.

9. The ultrasonic echo detection circuit of claim 8, wherein, The adjusting unit comprises: A second operational amplifier, a first input end of the second operational amplifier is connected with the output end of the logarithmic amplifier, and an output end of the second operational amplifier is connected with the echo output end; A ninth resistor, a first end of the ninth resistor is connected with a second input end of the second operational amplifier, and a second end of the ninth resistor is grounded; A tenth resistor, a first end of the tenth resistor is connected with the second input end of the second operational amplifier, and a second end of the tenth resistor is connected with the output end of the second operational amplifier.

10. The ultrasonic echo detection circuit of claim 1, wherein, The ultrasonic echo detection circuit comprises: An overvoltage protection module composed of diodes, a first end of the overvoltage protection module is connected with the first echo input end, a second end of the overvoltage protection module is connected with the second echo input end, and the overvoltage protection module is used for protecting the ultrasonic echo detection circuit when the first input signal and / or the second input signal is overvoltage; The overvoltage protection module comprises: two protection units, and each protection unit comprises: A first diode, an anode of the first diode is connected with the first echo input end; A second diode, a cathode of the second diode is connected with the second echo input end, and an anode of the second diode is connected with a cathode of the first diode. a third diode, a cathode of the third diode being connected to the first echo input, an anode of the third diode being connected to a cathode of the first diode; a fourth diode, an anode of the fourth diode being connected to the second echo input, a cathode of the fourth diode being connected to the cathode of the first diode.

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