Chip packaging structure
By setting trenches within the chip and filling them with an insulating layer, the problem of uneven HBM chip stacking is solved, improving the stability and uniformity of chip connections and preventing warping.
Patent Information
- Application Number
- CN202423095527.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-13
AI Technical Summary
In existing high bandwidth memory (HBM) chip stacking processes, the upper and lower layers of chips are prone to uneven stacking, resulting in difficulty in filling and unstable chip connections.
A trench extending inward from the edge and penetrating the upper and lower surfaces is formed within the chip and filled with an insulating layer to disperse the stress during the hot pressing process and prevent the chip edge from warping.
It improves the flatness of upper and lower layer chips in the chip stacking process, enhances the stability and filling uniformity of chip connections, and prevents warping.
Smart Images
Figure CN223680100U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of chip packaging especially relates to a chip packaging structure. BACKGROUND
[0002] High Band width Memory (HBM) is used for high-speed data transmission between a graphics processing unit (GPU) and a central processing unit (CPU). The uniqueness of HBM is mainly reflected in the stacking and interconnection. HBM vertically stacks multiple memories (DRAM) by using advanced packaging (such as through-silicon via (TSV) technology, micro-bump technology), and is packaged together with the graphics processing unit through an interposer, thereby realizing high capacity, high bandwidth, low latency, and low power consumption in a small physical space.
[0003] The existing HBM adopts a Mass Reflow bonding with Molded Underfill (MR-MUF) process. The specific steps of the MR-MUF process are as follows: (1) the micro-bumps of the chips are adhered with solder, and axial bonding stacking is completed; (2) all the micro-bump solders are melted at one time and pressed, the micro-bump axes are shortened, and the chip and circuit connection is completed after cooling; and (3) liquid epoxy molding compound (LMC) is used to fill the gaps between the chips or the substrates, and insulation and molding are simultaneously performed. However, the MR-MUF process has problems such as great difficulty in filling and uneven stacking of the upper and lower chips.
[0004] Therefore, how to improve the uneven stacking of the upper and lower chips in the chip stacking process is a problem to be solved at present. SUMMARY
[0005] The utility model wants to solve the technical problem of how to improve the uneven stacking of the upper and lower chips in the chip stacking process, and provides a chip packaging structure.
[0006] In order to solve the above problems, the utility model provides a chip packaging structure, which comprises a substrate, a chip stacking structure located on the surface of the substrate and comprising multiple layers of chips stacked in sequence, wherein the chip comprises an upper surface and a lower surface, the chip between the uppermost chip of the chip stacking structure and the substrate comprises a groove extending inward from the edge of the chip and penetrating the upper surface and the lower surface of the chip, and the groove is filled with an insulating layer, and a plastic encapsulation layer filled between at least adjacent chips and covering the surface of the insulating layer.
[0007] In some embodiments, the groove extends from the midpoint of the edge of the chip to the center of the chip.
[0008] In some embodiments, the length of the groove is less than half of the size of the chip.
[0009] In some embodiments, the chip comprises a plurality of the grooves, and the plurality of the grooves are arranged at intervals along the circumference of the chip.
[0010] In some embodiments, a plurality of through silicon vias are arranged in the chip, and the lower surface of the chip is provided with micro-bumps electrically connected to the through silicon vias.
[0011] In some embodiments, the lower surface of the chip is further provided with a buffer layer, and the buffer layer partially wraps the micro-bumps, and the micro-bumps are electrically connected to the through silicon vias of the lower chip.
[0012] In some embodiments, the lower surface of the insulating layer is exposed to the buffer layer, and the buffer layer forms a first flow guide groove at the corresponding position of the insulating layer.
[0013] In some embodiments, the thickness of the insulating layer is the same as that of the chip, the upper surface of the insulating layer is flush with the upper surface of the chip, and the lower surface of the insulating layer is flush with the lower surface of the chip.
[0014] In some embodiments, the thickness of the insulating layer is less than that of the chip, and the surfaces of the insulating layer and the chip have a height difference.
[0015] In some embodiments, the upper surface of the insulating layer is flush with the upper surface of the chip, and the lower surface of the insulating layer has a height difference with the lower surface of the chip.
[0016] In some embodiments, the lower surface of the insulating layer is flush with the lower surface of the chip, and the upper surface of the insulating layer has a height difference with the upper surface of the chip.
[0017] In some embodiments, the chip further comprises a second flow guide groove located at the edge of the upper surface of the chip.
[0018] The above technical solution disperses the stress generated during the chip stacking and hot pressing process by arranging a groove extending inward from the edge of the chip and penetrating through the upper and lower surfaces of the chip and filling an insulating layer, preventing the edge of the chip from warping, and thereby improving the uneven stacking of upper and lower chips in the chip stacking process.
[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Techniques, methods and devices known to those skilled in the related art can not be discussed in detail, but should be considered as part of the authorized description under appropriate circumstances. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the specific embodiments of this utility model, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0021] Figure 1 This is a schematic diagram of one embodiment of the chip packaging structure described in this utility model.
[0022] Figure 2 for Figure 1 A top view of the top chip after removing the molding compound and the chip stack structure.
[0023] Figure 3 This is a schematic diagram of another embodiment of the chip packaging structure described in this utility model.
[0024] Figure 4 for Figure 3 A top view of the top chip after removing the molding compound and the chip stack structure. Detailed Implementation
[0025] The technical solutions in the embodiments of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0026] Please see Figures 1-2 ,in, Figure 1 This is a schematic diagram of one embodiment of the chip packaging structure described in this utility model; Figure 2 for Figure 1 A top view of the top chip after removing the molding compound and the chip stack structure. (e.g., ...) Figures 1-2 As shown, the chip packaging structure includes: a substrate 11, a chip stacking structure 12, and a molding compound 18. The chip stacking structure 12 is located on the surface of the substrate 11 and includes multiple layers of chips 13 stacked sequentially. Each chip 13 includes an upper surface S1 and a lower surface S2. The chip 13 between the uppermost chip of the chip stacking structure 12 and the substrate 11 includes a trench 14 extending inward from the edge of the chip 13 and penetrating the upper and lower surfaces of the chip 13. The trench 14 is filled with an insulating layer 15. The molding compound 18 fills at least between adjacent chips 13 and covers the surface of the insulating layer 15.
[0027] The technical scheme above disperses the stress generated in the chip stacking and hot-pressing process by arranging the grooves extending from the edge of the chip inward and penetrating through the upper and lower surfaces of the chip and filling the insulating layer, prevents the warping of the edge of the chip, and further improves the uneven stacking of the upper and lower chips in the chip stacking process.
[0028] In some embodiments, the substrate 11 can be a wafer, a substrate, or a board for electrically connecting the chip 13 to other devices outside.
[0029] In some embodiments, the chip 13 can be obtained by separating a semiconductor substrate such as a wafer into multiple pieces using a die sawing process. The chip 13 can correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip), or a system on chip (SoC). The memory chip can include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip can include a logic circuit integrated on a semiconductor substrate.
[0030] In the present embodiment, the plastic encapsulation layer 18 is located on the surface of the substrate 11 and covers the chip stacking structure 12. The material of the plastic encapsulation layer 18 can include an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), FR-4, a bismaleimide triazine (BT), etc. The plastic encapsulation layer 18 can avoid mechanical or chemical damage to the chip 13 and ensure the stable function of the chip 13.
[0031] In some embodiments, the chip 13 includes a plurality of grooves 14, and the plurality of grooves 14 are arranged at intervals along the circumference of the chip 13. The grooves 14 extend from the midpoint of the edge of the chip 13 to the center of the chip 13. In the present embodiment, the chip 13 is a rectangular chip including four edges, and the four grooves 14 extend from the midpoint of the edge of the chip 13 to the center of the chip 13 in directions perpendicular to the four edges of the chip 13, respectively, to uniformly release the stress at different positions of the chip 13, avoid the warping of the chip, and further improve the uneven stacking of the upper and lower chips 13 in the chip stacking process.
[0032] In some embodiments, the length of the groove 14 is less than half of the size of the chip 13. The groove 14 extends to the center of the chip 13, but does not extend to the center of the chip 13 to avoid being too close to other grooves 14 and causing the chip 13 to break when stressed.
[0033] In some embodiments, a plurality of through silicon vias 130 are arranged in the chip 13, and the lower surface S2 of the chip 13 is provided with micro bumps 16 electrically connected to the through silicon vias 130, and the micro bumps 16 are electrically connected to the through silicon vias 130 of the lower chip 13. The through silicon vias 130 are used for electrical connection between the upper and lower chips 13, and the micro bumps 16 are used for soldering the upper and lower chips 13.
[0034] In some embodiments, the lower surface S2 of the chip 13 is further provided with a buffer layer 17, and the buffer layer 17 partially wraps the micro bumps 16. The buffer layer 17 is an organic buffer layer, and the material thereof can be polyimide (PI) or the like. The buffer layer 17 is arranged on the lower surface S2 of the chip 13 to expose the solder pad of the lower surface S2 of the chip 13, the micro bumps 16 are formed on the solder pad, the buffer layer 17 wraps the edges of the micro bumps 16, reduces the stress of the micro bumps 16, and prevents the micro bumps 16 from cracking.
[0035] In some embodiments, the lower surface S4 of the insulating layer 15 is exposed to the buffer layer 17, and the buffer layer 17 forms a first flow guide groove 191 at the corresponding position of the insulating layer 15. The buffer layer 17 forms the first flow guide groove 191 at the corresponding position of the insulating layer 15, and when plastic packaging, the epoxy plastic packaging material can enter between two adjacent chips 13 along the first flow guide groove 191, thereby improving the uniformity of the filling between the chips 13.
[0036] In some embodiments, the thickness of the insulating layer 15 is the same as that of the chip 13, the upper surface S3 of the insulating layer 15 is flush with the upper surface S1 of the chip 13, and the lower surface S4 of the insulating layer 15 is flush with the lower surface S2 of the chip 13.
[0037] Please refer to Figures 3-4 , wherein Figure 3 is a structural schematic diagram of another embodiment of the chip packaging structure of the utility model; Figure 4 is Figure 3 a top view of the plastic packaging layer and the top chip of the chip stacking structure. Figures 3-4 The embodiments shown are not limited to Figures 1-2The difference between the shown embodiment and the embodiment is that in the embodiment, the thickness of the insulation layer 35 is less than the thickness of the chip 33, and the surface of the insulation layer 35 has a height difference with the surface of the chip 33, thereby forming the first flow guide groove 391, which is conducive to the introduction of the plastic sealing material from the first flow guide groove 391, and improves the uniformity of the filling between the chips 33.
[0038] In some embodiments, the upper surface S3 of the insulation layer 35 is flush with the upper surface S1 of the chip 33, and the lower surface S4 of the insulation layer 35 has a height difference with the lower surface S2 of the chip 33, that is, the first flow guide groove 391 is formed on the lower surface S2 of the chip 33.
[0039] In some embodiments, the upper surface S3 of the insulation layer 35 can also have a height difference with the upper surface S1 of the chip 33, and the lower surface S4 of the insulation layer 35 is flush with the lower surface S2 of the chip 33, that is, the first flow guide groove 391 is formed on the upper surface S1 of the chip 33.
[0040] In other embodiments, the upper surface S3 of the insulation layer 35 can also have a height difference with the upper surface S1 of the chip 33, and the lower surface S4 of the insulation layer 35 also has a height difference with the lower surface S2 of the chip 33, that is, the first flow guide groove 391 is formed on the upper surface S1 and the lower surface S2 of the chip 33, further increasing the uniformity of the filling of the plastic sealing material between the chips 33.
[0041] In some embodiments, the chip 33 further includes a second flow guide groove 392 located at the edge of the upper surface S1 of the chip 33. The second flow guide groove 392 is separately arranged on the surface of the chip 33 from the first flow guide groove 391, which can increase the adhesion strength between the chip 33 and the plastic sealing material.
[0042] It should be noted that the reference to "one embodiment", "an embodiment", "exemplary embodiment", "some embodiments", etc. in the description indicates that the described embodiment can include a particular feature, structure, or characteristic, but each embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted within the knowledge of those skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0043] Generally, terms can be understood to be contextually defined by their use in the specification. For example, the term "one or more," as used herein, can be used in either a singular sense or a plural sense depending on the context in which it is used. Similarly, terms such as "a," "an," or "the," again, can be understood to be contextually defined by their use in the specification. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead can also allow for existence of other factors that are not necessarily expressly described. It should also be noted in the description that "connected" or "coupled" are intended to mean either a direct coupling or an indirect coupling through one or more intervening components.
[0044] It should be noted that the terms "comprising" and "having" and their derivatives, as involved in the file of the present utility model, are intended to cover a non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence, unless the context clearly indicates otherwise, and it should be understood that the data thus used can be interchanged under appropriate circumstances. In addition, the embodiments and features in the present utility model can be combined with each other without conflict. Furthermore, in the above description, the description of known components and technologies is omitted to avoid unnecessary confusion of the concept of the present utility model. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between each embodiment can be referred to each other.
[0045] The above is only the preferred embodiment of the present utility model, and it should be noted that for ordinary skilled in the art, without departing from the principles of the present utility model, a number of improvements and refinements can also be made, which should be considered as the protection scope of the present utility model.
Claims
1. A chip package structure, characterized by, The chip stack structure comprises: a substrate; a chip stack structure on the surface of the substrate, comprising a plurality of chips stacked in sequence; each chip comprises an upper surface and a lower surface, and the chip between the uppermost chip of the chip stack structure and the substrate comprises a groove extending inward from the edge of the chip and penetrating the upper surface and the lower surface of the chip, and the groove is filled with an insulating layer; a plastic encapsulation layer at least filled between adjacent chips and covering the surface of the insulating layer.
2. The chip package structure of claim 1, wherein, The groove extends from the midpoint of the edge of the chip to the center of the chip.
3. The chip package structure of claim 1, wherein, The length of the groove is less than half the size of the chip.
4. The chip package structure of claim 1, wherein, The chip comprises a plurality of grooves, and the plurality of grooves are arranged at intervals along the circumference of the chip.
5. The chip package structure of claim 1, wherein, A plurality of through silicon vias are arranged in the chip, and the lower surface of the chip is provided with micro-bumps electrically connected to the through silicon vias, and the micro-bumps are electrically connected to the through silicon vias of the lower chip.
6. The chip package structure of claim 5, wherein, The lower surface of the chip is further provided with a buffer layer, and the buffer layer partially wraps the micro-bumps.
7. The chip package structure of claim 6, wherein, The lower surface of the insulating layer is exposed to the buffer layer, and the buffer layer forms a first flow guide groove at the corresponding position of the insulating layer.
8. The chip package structure of any one of claims 1-7, wherein, The thickness of the insulating layer is the same as that of the chip, the upper surface of the insulating layer is flush with the upper surface of the chip, and the lower surface of the insulating layer is flush with the lower surface of the chip.
9. The chip package structure of any one of claims 1-7, wherein, The thickness of the insulating layer is less than that of the chip, and the surface of the insulating layer has a height difference with the surface of the chip, thereby forming a first flow guide groove.
10. The chip package structure of claim 9, wherein, The upper surface of the insulating layer is flush with the upper surface of the chip, and the lower surface of the insulating layer has a height difference with the lower surface of the chip.
11. The chip package structure of claim 9, wherein, The lower surface of the insulating layer is flush with the lower surface of the chip, and the upper surface of the insulating layer has a height difference with the upper surface of the chip.
12. The chip package structure of any one of claims 1-7, wherein, The chip further comprises a second flow guide groove located at the edge of the upper surface of the chip.