Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a substrate; the chip stacking structure is located on the surface of the substrate and comprises multiple layers of chips which are stacked in sequence; the chip comprises an upper surface and a lower surface, a plurality of through silicon vias penetrating through the chip are formed in the chip, a plurality of supporting blocks electrically connected with the through silicon vias are formed on the upper surface of the chip between the uppermost chip of the chip stacking structure and the substrate, first solder bumps and second solder bumps electrically connected with the through silicon vias are formed on the lower surfaces of all the chips, and the first solder bumps and the second solder bumps are arranged in the stacking direction of the chips. The size of the second solder bump is smaller than that of the first solder bump; the supporting blocks of the chips make contact with the second solder protruding blocks of the adjacent upper-layer chips, and the second solder protruding blocks of the chips make contact with the supporting blocks of the adjacent lower-layer chips. According to the technical scheme, the supporting structure composed of the supporting block and the second welding flux protruding block can provide good supporting force for the first welding flux protruding block with the large size in the hot pressing combination process, and excessive deformation of the first welding flux protruding block is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of chip packaging especially relates to a chip packaging structure. BACKGROUND

[0002] In the existing chip stacking process, non-solidified adhesive layer can be used to fix adjacent chips, and a hot-press bonding process is performed on the stacked chips to melt the solder bumps between the chips to form deformed solder bumps, thereby saving complicated welding procedures.

[0003] However, it is difficult to reasonably and accurately control the pressure during the chip stacking process: if the pressure is too small, it may lead to poor welding; and if the pressure is too large, it may lead to excessive deformation of the solder balls. In addition, when performing multi-layer chip stacking and welding, due to the differences in the sizes of the welding bumps and the temperature differences between the chips of different layers, it is likely that under the same pressure, some chips may have severe solder ball deformation or insufficient compression, making it difficult to consider the welding bump extrusion deformation of all layers of chips, thereby increasing the difficulty of the process.

[0004] Therefore, how to avoid uneven deformation of the solder bumps in the hot-press bonding process to cause poor welding is a problem to be solved at present. SUMMARY

[0005] The technical problem to be solved by the utility model is how to avoid uneven deformation of the solder bumps in the hot-press bonding process to cause poor welding, and a chip packaging structure is provided.

[0006] To solve the above problems, the utility model provides a chip packaging structure, which comprises a substrate, a chip stacking structure located on the surface of the substrate and comprising a plurality of stacked layers of chips, each chip comprising an upper surface and a lower surface, a plurality of through-silicon vias formed in each chip, a plurality of support blocks formed on the upper surface of the uppermost chip of the chip stacking structure and electrically connected to the through-silicon vias, and a plurality of first solder bumps and second solder bumps formed on the lower surface of each chip and electrically connected to the through-silicon vias, wherein the size of the second solder bumps is smaller than that of the first solder bumps in the stacking direction of the chips.

[0007] In some embodiments, the substrate surface is also provided with a plurality of support blocks in contact with the second solder bumps on the lower surface of the bottommost chip of the chip stacking structure.

[0008] In some embodiments, the surface of the support block has a groove for accommodating the second solder bump.

[0009] In some embodiments, the first solder bumps and the second solder bumps of the same chip are alternately distributed.

[0010] In some embodiments, the support blocks are disposed at edges of the chips.

[0011] In some embodiments, the positions of the support blocks of different chips are the same.

[0012] In some embodiments, the positions of the support blocks of adjacent chips are staggered.

[0013] In some embodiments, the support blocks are integrally formed structures.

[0014] In some embodiments, the support blocks comprise support portions and conductive portions penetrating the support portions, the conductive portions being used for electrically connecting the second solder bumps and the through silicon vias.

[0015] In some embodiments, the conductive portions are disposed on bottom surfaces of the grooves.

[0016] In some embodiments, the support portions are elastic members.

[0017] The above technical solution sets the support blocks and the second solder bumps in contact with each other between adjacent chips. Since the second solder bumps are small in size, the deformation caused by the second solder bumps is also small. Therefore, the support structure composed of the support blocks and the second solder bumps can provide better support force for the first solder bumps which are large in size during the thermal compression bonding process, thereby avoiding excessive deformation of the first solder bumps and resulting in poor welding, reducing the process difficulty, making the chip stacking structure more uniform and flat, and improving the quality and yield of the product.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. The technology, methods and devices known to those skilled in the related art can not be discussed in detail, but under appropriate circumstances, the technology, methods and devices should be considered as part of the authorized description. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings needed in the description of the specific embodiments will be briefly introduced. Obviously, the drawings in the following description are only some specific embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without creative labor.

[0020] Figure 1 The structural schematic diagram of the first embodiment of the chip packaging structure of the present application.

[0021] Figure 2 Figure 2 is a structural schematic view of a second embodiment of the chip packaging structure according to the present application.

[0022] Figure 3 Figure 3 is a structural schematic view of a third embodiment of the chip packaging structure according to the present application.

[0023] Figure 4 Figure 4 is a structural schematic view of a support block of a first embodiment of the chip packaging structure according to the present application.

[0024] Figure 5 Figure 5 is a structural schematic view of a support block of a fourth embodiment of the chip packaging structure according to the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0026] Please refer to Figure 1 Figure 1 is a structural schematic view of a first embodiment of the chip packaging structure according to the present application. As shown in Figure 1 the chip packaging structure comprises a substrate 11 and a chip stack structure 12. The chip stack structure 12 is located on the surface of the substrate 11 and comprises a plurality of layers of chips 13 stacked in sequence. The chip 13 comprises an upper surface 131 and a lower surface 132, and a plurality of through-silicon vias 130 are formed in the chip 13 and penetrate the upper and lower surfaces. A plurality of support blocks 14 are formed on the upper surface 131 of the chip 13 between the uppermost layer of the chip stack structure 12 and the substrate 11, and the support blocks 14 are electrically connected to the through-silicon vias 130. The lower surface 132 of all the chips 13 is provided with a first solder bump 15 and a second solder bump 16 electrically connected to the through-silicon vias 130. In the direction of the chip stack, the size of the second solder bump 16 is smaller than that of the first solder bump 15. The support block 14 of the chip 13 is in contact with the second solder bump 16 of the adjacent upper layer of the chip 13, and the second solder bump 16 of the chip 13 is in contact with the support block 14 of the adjacent lower layer of the chip 13.

[0027] The technical scheme sets the support block and the second solder bump in contact with each other between the adjacent chips, the size of the second solder bump is small, and the deformation caused by the second solder bump is also small, so that the support structure composed of the support block and the second solder bump can provide better support force for the first solder bump with a larger size in the thermal compression bonding process, avoids excessive deformation of the first solder bump to cause poor welding, reduces the process difficulty, makes the chip stacking structure more uniform and flat, and improves the quality and yield of products.

[0028] In some embodiments, the substrate 11 can be a wafer, a substrate or a board for electrically connecting the chips 13 to other devices outside.

[0029] In some embodiments, the chips 13 can be obtained by separating a semiconductor substrate such as a wafer into multiple pieces by using a die sawing process. The chips 13 can correspond to memory chips, logic chips (including application specific integrated circuit (ASIC) chips) or system on chips (SoC). The memory chips can include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, NAND-type flash memory circuits, NOR-type flash memory circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits or phase change random access memory (PcRAM) circuits integrated on a semiconductor substrate. The logic chips can include logic circuits integrated on a semiconductor substrate.

[0030] In the embodiment, the substrate 11 is also provided with a plurality of support blocks 14 in contact with the second solder bumps 16 of the lower surface 132 of the chip 13 of the bottom layer of the chip stacking structure 12.

[0031] In the embodiment, the chip packaging structure further includes an encapsulation layer 17 located on the surface of the substrate 11 and encapsulating the chip stacking structure 12. The encapsulation layer 17 is made of epoxy molding compound (EMC), which can avoid mechanical or chemical damage of the chips 13 and ensure stable function of the chips 13.

[0032] Please refer to Figure 4 which is a structural schematic view of the support block of the first embodiment of the chip packaging structure of the utility model. Please refer to Figure 4 and Figure 1In some embodiments, the support block 14 has a groove 140 on its surface for accommodating the second solder bump 16. The support block 14 with the groove 140 is arranged correspondingly to the second solder bump 16 with a smaller size, which helps to assist the positioning of the two adjacent chips 13, and this structure can help to fix the two adjacent chips 13.

[0033] In some embodiments, the support block 14 is an integrally formed structure. In order to ensure the conductive performance of the support block 14, the material of the support block 14 is a metal material.

[0034] Please continue to refer to Figure 1 In some embodiments, the first solder bump 15 and the second solder bump 16 of the same chip 13 are alternately distributed. Accordingly, the support blocks 14 of the lower layer chips 13 correspondingly distributed with the second solder bump 16 of the chip 13 are spaced apart from the upper surface of the lower layer chip 13 adjacent to the chip 13, which can improve the uniformity of the distribution of the support block 14, provide more uniform support for the chip stacking structure 12, avoid uneven stress on the solder bump during the thermal compression bonding process, and thus cause uneven deformation of the solder bump, and further assist the positioning between the two adjacent chips 13.

[0035] In some embodiments, the positions of the support blocks 14 of different chips 13 are the same. The distribution of the support blocks 14 and the second solder bump 16 on the surface of the plurality of chips 13 is the same, which can reduce the complexity of the process of manufacturing the support block 14, reduce the possibility of errors in the packaging process, and improve the yield of the product.

[0036] In some embodiments, in the direction of chip stacking, the height of the first solder bump 15 and the height of the support structure composed of the support block 14 and the second solder bump 16 are flush, so as to ensure the uniformity of the distribution of the chips 13 and ensure good conduction performance between the chips 13.

[0037] Please refer to Figure 2 It is a structural schematic view of the second embodiment of the chip packaging structure. Figure 2 The embodiments shown are different from Figure 1 The support block 24 is arranged at the edge of the chip 23. Accordingly, the second solder bump 26 of the adjacent upper layer chip 23 is arranged at the edge of the chip 23. By arranging the support block 24 only at the edge of the chip 23, the support effect of the support block 24 on the chip 23 is ensured, and the process cost and process complexity of forming the support block 24 are further reduced.

[0038] In some embodiments, the support block 24 is arranged corresponding to the through silicon via 230 of the chip 23 edge.

[0039] Referring to Figure 3 which is a structural schematic view of a third embodiment of the chip packaging structure. Figure 3 The embodiments shown Figure 1 The difference between the embodiments is that the positions of the support blocks 34 adjacent to the chip 33 are staggered. The support blocks 34 arranged staggered on the surface of the adjacent chip 33 further improve the uniformity of the distribution of the support blocks 34 in the entire chip stacking structure 32, that is, the uniformity of the stress of the entire chip stacking structure 32 in the thermal compression bonding process is improved, the deformation of the solder bumps is more uniform, the welding result is better, and the uniformity of the distribution of the chip 33 is also improved; at the same time, better positioning between the adjacent chips 33 can be achieved to prevent deviation.

[0040] Referring to Figure 5 which is a structural schematic view of a support block of a fourth embodiment of the chip packaging structure. Figure 5 The embodiments shown Figure 4 The difference between the embodiments shown is that the support block 54 includes a support part 541 and a conductive part 542 penetrating through the support part 541, and the conductive part 542 is used for electrically connecting the second solder bump and the through silicon via. The material of the conductive part 542 is a metal material. In the embodiment, the conductive part 542 is arranged on the groove bottom surface to increase the contact area of the conductive part 542 and the second solder bump, reduce the contact resistance, and improve the conductive performance.

[0041] In some embodiments, the support part 541 is an elastic member to protect the second solder bump from being damaged and can release the stress around the conductive part 542 and the second solder bump. The material of the support part 541 is a high-temperature-resistant elastic material that can withstand high temperature in the process and protect the second solder bump from being damaged.

[0042] It should be noted that the reference to "one embodiment", "an embodiment", "exemplary embodiment", "some embodiments" and the like indicates that a described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that embodiments can or can not include such features, structures, or characteristics, whether or not explicitly described above.

[0043] Generally, terms can be understood to be contextually defined by their use in the specification. For example, the term "one or more," as used herein, can be used in either a singular sense or a plural sense depending on the context in which it is used. Similarly, terms such as "a," "an," or "the," again, can be understood to be contextually defined by their use in the specification. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead can also allow for existence of other factors that are not necessarily expressly described. It should also be noted in the description that "connected" or "coupled" are intended to mean either a direct coupling or an indirect coupling through one or more intervening components.

[0044] It should be noted that the terms "comprising" and "having" and their derivatives, as involved in the file of the present utility model, are intended to cover a non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence, unless the context clearly indicates otherwise, and it should be understood that the data thus used can be interchanged under appropriate circumstances. In addition, the embodiments and features in the present utility model can be combined with each other without conflict. Furthermore, in the above description, the description of known components and technologies is omitted to avoid unnecessary confusion of the concept of the present utility model. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between each embodiment can be referred to each other.

[0045] The above is only the preferred embodiment of the present utility model, and it should be noted that for ordinary skilled in the art, without departing from the principles of the present utility model, a number of improvements and refinements can also be made, which should be considered as the protection scope of the present utility model.

Claims

1. A chip package structure, characterized by, The application relates to a chip stack structure, comprising: a substrate; a chip stack structure on the surface of the substrate, comprising a plurality of chips stacked in sequence; each chip comprises an upper surface and a lower surface, a plurality of through-silicon vias are formed in the chip, a plurality of support blocks are formed on the upper surface of the chip between the uppermost chip of the chip stack structure and the substrate, the support blocks are electrically connected with the through-silicon vias, the lower surface of each chip is provided with first solder bumps and second solder bumps which are electrically connected with the through-silicon vias, the size of the second solder bump is smaller than that of the first solder bump in the direction of the chip stack; the support block of the chip is in contact with the second solder bump of the upper adjacent chip, and the second solder bump of the chip is in contact with the support block of the lower adjacent chip.

2. The chip package structure of claim 1, wherein, The surface of the substrate is also provided with a plurality of support blocks which are in contact with the second solder bump of the lower surface of the bottommost chip of the chip stack structure.

3. The chip package structure of claim 1, wherein, The surface of the support block is provided with a groove for accommodating the second solder bump.

4. The chip package structure of claim 1, wherein, The first solder bump and the second solder bump of the same chip are alternately distributed.

5. The chip package structure of claim 1, wherein, The support block is arranged at the edge of the chip.

6. The chip package structure of claim 1, wherein, The positions of the support blocks of different chips are the same.

7. The chip package structure of claim 1, wherein, The positions of the support blocks of adjacent chips are staggered.

8. The chip package structure of claim 1, wherein, The support block is an integral structure.

9. The chip package structure of claim 3, wherein, The support block comprises a support part and a conductive part penetrating through the support part, the conductive part is used for electrically connecting the second solder bump and the through-silicon via.

10. The chip package structure of claim 9, wherein, The conductive part is arranged on the bottom surface of the groove.

11. The chip package structure of claim 9, wherein, The support part is an elastic member.

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