On-chip tandem edge-emitting semiconductor laser array
By using an on-chip tandem side-emitting semiconductor laser array structure, coplanar electrode design, and lateral current diffusion suppression trench, the problems of complex semiconductor laser array processes and high costs are solved, achieving low-cost, high-power pulsed laser output.
Patent Information
- Application Number
- CN202423311890.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In existing technologies, semiconductor laser arrays are complex and costly to manufacture, making it difficult to achieve high power output and low-cost manufacturing.
By employing an on-chip tandem side-emitting semiconductor laser array structure, and through coplanar electrode design and lateral current diffusion suppression trenches, the process flow is simplified and costs are reduced, enabling single-step electrode deposition.
It reduces the requirements for the driving circuit, improves the uniformity of light emission, and enables low-cost, high-power pulsed laser output.
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Figure CN223680569U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of laser technology, and more particularly to an on-chip tandem side-emitting semiconductor laser array. Background Technology
[0002] LiDAR has great application prospects in many fields. Semiconductor lasers are currently the most effective coherent light source, and have advantages such as small size, low cost, long lifespan, and electric pumping, making them the preferred light source for LiDAR systems. LiDAR systems typically require short-pulse laser operation, have low heat dissipation requirements, but require high peak power to increase detection range.
[0003] To achieve high output power and scanning speed, multi-channel high-power laser arrays are required. Achieving high output power necessitates high current operation at each emission point. Traditional semiconductor laser arrays are parallel structures, resulting in extremely high operating current and placing high demands on the driving circuitry. In related technologies, series-type semiconductor laser array structures require separate deposition of P-type and N-type electrodes, followed by separate lift-off processes, which are complex and costly. Utility Model Content
[0004] This application provides an on-chip tandem side-emitting semiconductor laser array to solve the problems of complex process and high cost of semiconductor laser arrays in the prior art.
[0005] This application provides an on-chip tandem edge-emitting semiconductor laser array, which, from bottom to top, includes a semi-insulating substrate, an undoped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding layer, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding layer, and a P-type capping layer.
[0006] The laser array has multiple light-emitting units. The two mesa surfaces of each light-emitting unit are deeply etched into the P-type heavily doped layer. The upper and lower electrodes of each light-emitting unit are fabricated in a single process. A lateral current diffusion suppression groove is provided between the bottoms of any two adjacent light-emitting units.
[0007] According to the on-chip tandem side-emitting semiconductor laser array provided in this application, the upper electrode of each light-emitting unit is electrically connected to the lower electrode of the adjacent light-emitting unit on one side.
[0008] According to an on-chip tandem edge-emitting semiconductor laser array provided in this application, each of the light-emitting units has an electrically insulating layer deposited on the top and bottom surfaces of its mesa, excluding the current injection region.
[0009] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the lateral current diffusion suppression groove between adjacent light emitting units is prepared by proton injection or etching process, and the bottom of the lateral current diffusion suppression is located in the non-doped buffer layer or the semi-insulating substrate.
[0010] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the upper metal electrode and the lower metal electrode of each light emitting unit are composed of the same group, and the upper electrode and the lower electrode of the same light emitting unit are disconnected.
[0011] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the active region is a single-layer or multi-layer quantum well, quantum dot or quantum wire.
[0012] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the thickness of the N-type waveguide layer and the P-type waveguide layer is different.
[0013] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the thickness of the N-type cladding layer and the P-type cladding layer is different.
[0014] According to the on-chip series type edge-emitting semiconductor laser array provided in the application, the semi-insulating substrate is any one of GaAs, InP, GaSb and GaN.
[0015] The on-chip series type edge-emitting semiconductor laser array provided in the application adopts the on-chip series type edge-emitting semiconductor laser array structure, reduces the parasitic effect through the coplanar electrode design, and the upper and lower electrodes can be prepared through a single process to reduce the cost. The lateral current diffusion suppression groove arranged between the light emitting units can reduce the crosstalk, each light emitting unit works in series under the same injection current, which can effectively reduce the driving circuit requirement and improve the light emitting uniformity. In addition, the structure realizes single-step electrode deposition through the tunnel junction, which can effectively reduce the process cost and save the process time, and is conducive to realizing low-cost and high-power pulse laser output. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0017] Figure 1 is a structure schematic diagram of the on-chip series type edge-emitting semiconductor laser array provided in the application;
[0018] Figure 2A semiconductor laser wafer epitaxial structure diagram provided by the present application.
[0019] Figure 3 A plurality of light emitting unit mesa etching structure diagrams of a semiconductor laser array provided by the present application.
[0020] Figure 4 A preparation lateral current diffusion inhibition groove between adjacent light emitting units of a semiconductor laser array provided by the present application.
[0021] Figure 5 A semiconductor laser array preparation structure diagram of deposition of an electrically insulating layer and opening of a current injection window provided by the present application.
[0022] Figure 6 A semiconductor laser array preparation structure diagram of deposition of a metal electrode layer and after stripping provided by the present application.
[0023] Reference signs:
[0024] 100, on-chip series type edge emitting semiconductor laser array;
[0025] 1, semi-insulating substrate; 2, undoped buffer layer; 3, P-type heavily doped layer; 4, P-type tunnel junction layer; 5, N-type tunnel junction layer; 6, N-type cladding layer; 7, N-type waveguide layer; 8, active region; 9, P-type waveguide layer; 10, P-type cladding layer; 11, P-type cap layer;
[0026] E, light emitting unit; E1, light emitting unit; E2, light emitting unit; E3, light emitting unit; E4, light emitting unit;
[0027] B, lateral current diffusion inhibition groove;
[0028] M1, upper electrode window; M2, lower electrode window; C, electrically connecting layer;
[0029] 12, electrically insulating layer; 13, metal electrode. DETAILED DESCRIPTION
[0030] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0031] The on-chip series type edge emitting semiconductor laser array 100 of the present application will be described below. Figures 1-6 The on-chip series type edge emitting semiconductor laser array 100 of the present application will be described below. It is worth understanding that the following description is only exemplary and is not a specific limitation of the present application.
[0032] The on-chip series type edge-emitting semiconductor laser array 100 according to the embodiment of the present application comprises, from bottom to top, a semi-insulating substrate 1, a non-doped buffer layer 2, a P-type heavily doped layer 3, a P-type tunnel junction layer 4, an N-type tunnel junction layer 5, an N-type cladding layer 6, an N-type waveguide layer 7, an active region 8, a P-type waveguide layer 9, a P-type cladding layer 10, and a P-type cap layer 11.
[0033] It should be noted that the substrate 1 can be a semi-insulating non-doped III-V compound, such as GaAs, InP, GaN, GaSb, etc. The non-doped buffer layer 2 is grown on the substrate 1, and the non-doped buffer layer 2 is usually the same material as the substrate 1, which is used to bury the defects of the substrate 1 itself. The P-type heavily doped layer 3 is on the non-doped buffer layer 2, and the P-type heavily doped layer 3 has the same lattice constant as the substrate 1 material, which is used as an ohmic contact layer for the lower electrode of the laser.
[0034] The P-type tunnel junction layer 4 is on the P-type heavily doped layer 3, and the P-type tunnel junction layer 4 can be P-type extremely high doping, and the P-type tunnel junction layer 4 has the same lattice constant as the substrate 1 material, and the thickness is relatively thin, which is usually between 10 nm and 200 nm.
[0035] The N-type tunnel junction layer 5 is on the P-type heavily doped layer 3, and the N-type tunnel junction layer 5 can be N-type extremely high doping, and the N-type tunnel junction layer 5 has the same lattice constant as the substrate 1 material, and the thickness is relatively thin, which is usually between 10 nm and 200 nm.
[0036] The N-type cladding layer 6 is grown on the N-type tunnel junction layer 5, and the N-type cladding layer 6 is N-type doped.
[0037] The N-type waveguide layer 7 is grown on the N-type cladding layer 6, and the N-type waveguide layer 7 is N-type low doping or non-doped, and the refractive index of the N-type waveguide layer 7 is higher than that of the N-type cladding layer 6, but the band gap is lower than that of the N-type cladding layer 6, which is used to limit the expansion of the optical field to the substrate 1.
[0038] The active layer is located above the N-type waveguide layer 7, which is the gain region of the semiconductor laser, and is usually undoped, which can be quantum well, quantum dot and other materials.
[0039] The P-type waveguide layer 9 is located above the active layer, which is usually partially undoped and partially P-type low doping.
[0040] The P-type cladding layer 10 is located above the P-type waveguide layer 9, and the band gap of the P-type cladding layer 10 is higher than that of the P-type waveguide layer 9, but the refractive index is lower than that of the P-type waveguide layer 9, and it is usually P-type doped.
[0041] The P-type cap layer 11 is located above the P-type cladding layer 10, and it is P-type high doping, which is conducive to the ohmic contact of the upper electrode.
[0042] The laser array has a plurality of light emitting units E, for example, seeFigure 1 As shown, the light emitting units E are four, and are respectively light emitting unit El, light emitting unit E2, light emitting unit E3 and light emitting unit E4, wherein the light emitting units El, E2, E3 and E4 are different light emitting points in the array.
[0043] The two sides of each of the light emitting units E are etched to the P-type heavily doped layer 3. In other words, the two sides of each of the light emitting units E are etched to form a groove, and the groove is etched to the P-type heavily doped layer 3. The upper electrode and the lower electrode of each of the light emitting units are prepared by a single process. The bottom of any two adjacent light emitting units E has a lateral current diffusion suppression groove B for suppressing lateral diffusion of current, which can be realized by proton bombardment, etching of the doped layer, etc.
[0044] According to the on-chip series type edge emitting semiconductor laser array 100 of the embodiments of the present application, by etching the two sides of each of the light emitting units E to the P-type heavily doped layer 3, and by providing the bottom of any two adjacent light emitting units E with a lateral current diffusion suppression groove B for suppressing lateral diffusion of current, the process of the semiconductor laser array can be simplified, and the manufacturing cost can be reduced.
[0045] According to some embodiments of the present application, on each of the light emitting units E, the surface of the mesa top and the mesa bottom except the current injection area is deposited with an electrically insulating layer 12. For example, refer to Figure 1 As shown, the upper surface of the mesa and the etched groove is deposited with an electrically insulating layer 12, and an electrode window is formed on the electrically insulating layer 12. Further, the electrically insulating layer 12 is etched away at the upper electrode window Ml position on the mesa top to expose a part of the P-type cap layer 11, and the electrically insulating layer 12 is etched away at the lower electrode window M2 position on the mesa bottom to expose a part of the P-type heavily doped layer 3, so as to limit the current injection area.
[0046] A metal electrode 13 is deposited on the upper electrode window Ml, the lower electrode window M2 and the electrically connecting layer C, and the metal electrode 13 is realized by a single-step deposition and lift-off process, wherein the metal electrode 13 forms an ohmic contact with the P-type cap layer 11 on the mesa top of each of the light emitting units E which is not covered by the electrically insulating layer 12, and the metal electrode 13 forms an ohmic contact with the P-type heavily doped layer 3 on the mesa bottom of each of the light emitting units E which is not covered by the electrically insulating layer 12, so as to realize current injection, and there is no metal electrode 13 between the upper electrode and the lower electrode of the same light emitting unit E.
[0047] According to the on-chip series edge-emitting semiconductor laser array 100 of the embodiments of the present application, the on-chip series edge-emitting semiconductor laser array 100 structure is adopted, the parasitic effect is reduced through the coplanar electrode design, the lateral current diffusion suppression groove B is arranged between the light emitting units E to reduce the crosstalk, each light emitting unit E works in series under the same injection current, the driving circuit requirement can be effectively reduced and the light emitting uniformity can be improved; in addition, the single-step electrode deposition is realized through the tunnel junction, the process cost can be effectively reduced, the process time can be saved, and the low-cost and high-power pulse laser output is beneficial to be realized.
[0048] According to some embodiments of the present application, the upper electrode of each light emitting unit E is electrically connected with the lower electrode of the adjacent light emitting unit E. In some embodiments, the electric connection layer C is arranged between different light emitting units E to sequentially connect the lower electrode of the device and the upper electrode of the adjacent device, forming the series current injection.
[0049] According to some embodiments of the present application, the lateral current diffusion suppression groove B between the adjacent light emitting units E is prepared through the proton injection or etching process, and the bottom of the lateral current diffusion suppression is located in the undoped buffer layer 2 or the semi-insulating substrate 1.
[0050] According to some embodiments of the present application, the upper metal electrode 13 and the lower metal electrode 13 of each light emitting unit E are composed of the same component, and the upper electrode and the lower electrode of the same light emitting unit E are disconnected. In some embodiments, the component of the upper metal electrode 13 and the component of the lower metal electrode 13 can be the same.
[0051] According to some embodiments of the present application, the active region 8 is a single-layer or multi-layer quantum well, quantum dot or quantum wire.
[0052] According to some embodiments of the present application, the thicknesses of the N-type waveguide layer 7 and the P-type waveguide layer 9 are different. In some embodiments, the component of the N-type waveguide layer 7 and the component of the P-type waveguide layer 9 can be the same. In some embodiments, the substrate 1 is any one of GaAs, InP, GaSb and GaN. In some embodiments, the thicknesses of the N-type cladding layer 6 and the P-type cladding layer 10 are different. In some embodiments, the component of the N-type cladding layer 6 and the component of the P-type cladding layer 10 can be the same.
[0053] According to the laser emitter circuit provided by the present application, the on-chip series edge-emitting semiconductor laser array 100 as described above is included.
[0054] According to the laser emitter circuit of the embodiment of the present application, the two sides of each light emitting unit E are etched to the P-type heavily doped layer 3, and the bottom of any two adjacent light emitting units E is provided with a lateral current diffusion suppression groove B, so as to suppress the lateral diffusion of the current, thereby simplifying the process of the semiconductor laser array and reducing the manufacturing cost.
[0055] The embodiment of the present application provides a process method of the on-chip series type edge-emitting semiconductor laser array 100. The on-chip series type edge-emitting semiconductor laser array 100 is the on-chip series type edge-emitting semiconductor laser array 100 as described above.
[0056] Specifically, the process method comprises the following steps.
[0057] S1: growing an epitaxial layer on the upper surface of the substrate 1; for example, in this step, the MOCVD (Metal-organic Chemical Vapor Deposition) device or the MBE (Molecular beam epitaxy) device can be used to grow, on the upper surface of the semi-insulating GaAs, InP, GaN, GaSb, etc. substrate 1, a non-doped buffer layer 2, a P-type heavily doped layer 3, a P-type tunnel junction layer 4, an N-type tunnel junction layer 5, an N-type cladding layer 6, an N-type waveguide layer 7, an active region 8, a P-type waveguide layer 9, a P-type cladding layer 10, and a P-type cap layer 11 in sequence, so as to obtain the epitaxial layer of the semiconductor laser, as shown in FIG. 1. Figure 2
[0058] S2: preparing a light emitting gain mesa; on the upper surface of the epitaxial layer, the gain region of each light emitting unit E is prepared through the processes of cleaning, uniform coating, exposure, development, and mesa etching, and the two side grooves of the mesa are etched to the P-type heavily doped layer 3, wherein the angle between the sidewall of the mesa and the surface of the epitaxial layer is less than 90°; in this way, the thickness of the insulating layer and the deposition of the electrical connection layer can be ensured, as shown in FIG. 2. Figure 3
[0059] S3: preparing a lateral current diffusion suppression groove B; in this step, the lateral current diffusion suppression groove B mask is prepared through the processes of cleaning, uniform coating, exposure, and development, and then the lateral current diffusion suppression groove B is prepared through the technical approach of ion implantation or etching, so as to suppress the lateral carrier diffusion between different light emitting units E, as shown in FIG. 3. Figure 4
[0060] S4: depositing an electrically insulating layer 12 to prepare a current injection area. In this step, the wafer is cleaned and the electrically insulating layer 12 is deposited on the wafer surface, and then a window is opened by means of spin coating, photoetching, developing, etching, etc. to remove the electrically insulating layer 12 of the current injection area, to prepare the upper current injection area M1 (i.e. the upper electrode window M1) and the lower current injection area M2 (i.e. the lower electrode window M2), as shown in Figure 5 . .
[0061] S5: depositing a metal electrode 13 and achieving ohmic contact and electrically connecting layer preparation by means of negative photoresist stripping. In this step, the electrode deposition pattern is prepared by means of spin coating, photoetching and developing, and then the upper metal electrode 13 and the lower metal electrode 13 are deposited, and then the unwanted metal layer is removed by means of stripping to complete the injection electrode and electrically connecting layer preparation, as shown in Figure 6 . .
[0062] S6: thinning the substrate 1. In this step, the semi-insulating substrate 1 is thinned by means of grinding, and then polished to facilitate subsequent cleaving, etc. After the lower surface of the substrate 1 is thinned and polished, a layer of metal electrode 13 can also be deposited for subsequent packaging.
[0063] According to the process method of the on-chip series type edge-emitting semiconductor laser array 100 of the embodiments of the present application, the two sides of each of the light-emitting units E are etched to the P-type heavily doped layer 3, and the bottom of any two adjacent light-emitting units E is provided with a lateral current diffusion suppression groove B, to suppress the lateral diffusion of the current, so that the process of the semiconductor laser array can be simplified and the manufacturing cost can be reduced. Further, by adopting the on-chip series type edge-emitting semiconductor laser array 100 structure, the parasitic effect is reduced by means of the coplanar electrode design, and the upper and lower electrodes can be prepared by a single process to reduce the cost, the current lateral diffusion suppression groove is provided between the light-emitting units E to reduce the crosstalk, and each of the light-emitting units E works in series under the same injection current, to effectively reduce the requirement of the driving circuit and improve the light-emitting uniformity; in addition, the single-step electrode deposition is achieved by means of the tunnel junction, to effectively reduce the process cost and save the process time, which is conducive to realizing low-cost and high-power pulsed laser output.
[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. An on-chip tandem side-emitting semiconductor laser array, characterized in that, From bottom to top, the layers consist of a semi-insulating substrate, an undoped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding layer, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding layer, and a P-type capping layer. The laser array has multiple light-emitting units. The two mesa surfaces of each light-emitting unit are deeply etched into the P-type heavily doped layer. The upper and lower electrodes of each light-emitting unit are fabricated in a single process. A lateral current diffusion suppression groove is provided between the bottoms of any two adjacent light-emitting units.
2. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The upper electrode of each light-emitting unit is electrically connected to the lower electrode of the adjacent light-emitting unit on one side.
3. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, On each of the light-emitting units, an electrically insulating layer is deposited on the top and bottom surfaces of its mesa, excluding the current injection region.
4. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The lateral current diffusion suppression trench between adjacent light-emitting units is prepared by proton injection or etching process, and the bottom of the lateral current diffusion suppression is located in an undoped buffer layer or a semi-insulating substrate.
5. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The upper and lower metal electrodes of each of the light-emitting units have the same composition, and the upper and lower electrodes of the same light-emitting unit are disconnected.
6. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The active region is a single-layer or multi-layer quantum well, quantum dot, or quantum wire.
7. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The N-type waveguide layer and the P-type waveguide layer have different thicknesses.
8. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The N-type cladding and the P-type cladding have different thicknesses.
9. The on-chip tandem side-emitting semiconductor laser array according to claim 1, characterized in that, The semi-insulating substrate is any one of GaAs, InP, GaSb, and GaN.