Double-battery-pack parallel circuit suitable for standard charging interface and electric vehicle

Abstract

The embodiment of the utility model relates to the technical field of integrated circuits, and discloses a double-battery-pack parallel circuit suitable for a standard charging interface and an electric vehicle. The circuit comprises a master battery pack and a slave battery pack, the external interfaces are respectively provided with two power pins, four communication pins, a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface and a 485-B interface; the two power pins comprise a power positive electrode and a power negative electrode; the four communication pins comprise a single-wire serial port, an address allocation and access detection function multiplexing interface and a 485-A and single-wire serial port multiplexing interface; when connected with a standard charger, the power supply anode interface and the power supply cathode interface of the standard charger are respectively connected with the power supply anode and the power supply cathode; the interlocking interfaces are respectively connected with the cathode of the power supply; a 485-A interface of the standard charger is respectively connected with the 485-A and single-wire serial port multiplexing interface; the 485-B interface of the standard charger is respectively connected with the 485-B interface; a reserved interface of the standard charger is suspended. By adopting the scheme, the compatibility between the lithium battery double-pack parallel connection and the standard charging interface can be realized by defining the interface pins.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a double battery pack parallel circuit suitable for a standard charging interface and an electric vehicle. BACKGROUND

[0002] In recent years, with the rapid development of electric vehicle technology, a new standard for the safety of electric vehicle chargers has been officially implemented. This new standard aims to address the waste of resources and potential safety risks caused by non-uniform charging interfaces, and to promote the standardization process of the charger market. According to the different voltage algorithms of lithium-ion and lead-acid batteries, the new national standard designs two types of plugs: the lead-acid battery plug adopts a 2+2 (two power pins and two communication pins) structure, while the lithium-ion battery plug adopts a 2+4 (two power pins and four communication pins) structure. Currently, lithium battery double-pack parallel products on the market often have relatively high costs, and do not meet the requirements of the new national standard 2+4 charging port, which requires more PIN support to meet the demand. The communication method with the vehicle is also relatively single, and the compatibility is not strong. However, lithium battery double-pack parallel has a great help to the performance of electric vehicles, so how to solve the compatibility problem of lithium battery double-pack parallel is an industry pain point. CONTENT OF THE INVENTION

[0003] An object of the present application is to provide a double battery pack parallel circuit suitable for a standard charging interface and an electric vehicle, at least to solve the problem of incompatibility between lithium battery double-pack parallel and the new standard charging interface. The circuit described in the present application comprises: a master battery pack and a slave battery pack; the master battery pack and the slave battery pack are respectively provided with two power pins: a positive power supply, a negative power supply, four communication pins: a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface; when connected with a standard charger, the positive power supply interface and the negative power supply interface of the standard charger are respectively connected with the positive power supply and the negative power supply of the master battery pack and the slave battery pack; the interlock interface of the standard charger is respectively connected with the negative power supply of the master battery pack and the slave battery pack; the 485-A interface of the standard charger is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack; the 485-B interface of the standard charger is respectively connected with the 485-B interface of the master battery pack and the slave battery pack; the reserved interface of the standard charger is suspended. By defining the interface pins, the compatibility problem of lithium battery double-pack parallel and the standard charging interface can be solved.

[0004] To achieve the above-mentioned object, some embodiments of the present application provide the following aspects:

[0005] In a first aspect, some embodiments of the present application also provide a dual battery pack parallel circuit suitable for a standard charging interface, the circuit comprising:

[0006] a master battery pack and a slave battery pack;

[0007] The master battery pack and the slave battery pack are respectively provided with two power pins: a power positive pin and a power negative pin, and four communication pins: a single-wire serial port, an address allocation and access detection multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface.

[0008] When connected with a standard charger, the power positive interface and the power negative interface of the standard charger are respectively connected with the power positive pin and the power negative pin of the master battery pack and the slave battery pack.

[0009] The interlock interface of the standard charger is respectively connected with the power negative pin of the master battery pack and the slave battery pack.

[0010] The 485-A interface of the standard charger is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack.

[0011] The 485-B interface of the standard charger is respectively connected with the 485-B interface of the master battery pack and the slave battery pack.

[0012] The reserved interface of the standard charger is suspended.

[0013] Further, the circuit further comprises an electric vehicle control center.

[0014] The electric vehicle control center comprises:

[0015] The 485-A and single-wire serial port multiplexing pin is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack.

[0016] The 485-B communication pin is respectively connected with the 485-B interface of the master battery pack and the slave battery pack.

[0017] The master battery pack and the slave battery pack are by default in a single-wire serial port communication mode; when it is detected that the electric vehicle control center is in 485 communication, the communication mode is switched to 485 communication.

[0018] Further, the electric vehicle control center further comprises a first detection pin and a second detection pin.

[0019] The second detection pin is connected with the address allocation and access detection function multiplexing interface of the slave battery pack.

[0020] The address allocation and access detection function multiplexing interface of the slave battery pack is connected with a reference voltage through a first resistor.

[0021] The first resistor and the second resistor have the same resistance value, and whether the slave battery pack is connected to the electric vehicle is detected according to the voltage division value of the second resistor.

[0022] Further, the electric vehicle control center further comprises a first detection pin and a third detection pin.

[0023] The third detection pin is connected with the address allocation and access detection function multiplexing interface of the master battery pack.

[0024] The address allocation and access detection function multiplexing interface of the master battery pack is connected with a reference voltage through a first resistor.

[0025] The first resistor has a resistance value twice that of the third resistor, and whether the master battery pack is connected to the electric vehicle is detected according to the voltage division value of the third resistor.

[0026] Further, the circuit further comprises a controller.

[0027] The controller is connected with the electric vehicle control center through a 485 pin, and is used to send the state information of the double battery packs to the controller.

[0028] Further, the master battery pack and the slave battery pack are connected through a single-wire serial port.

[0029] In a second aspect, some embodiments of the present application also provide an electric vehicle comprising the double battery pack parallel circuit suitable for a standard charging interface.

[0030] Compared with the related art, the scheme provided by the embodiment of the application, the circuit comprises: a master battery pack and a slave battery pack; the master battery pack and the slave battery pack are respectively provided with, in an external interface, two power pins: a power positive electrode and a power negative electrode, and four communication pins: a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface; when connected with a standard charger, the power positive electrode interface and the power negative electrode interface of the standard charger are connected with the power positive electrode and the power negative electrode of the master battery pack and the slave battery pack respectively; the interlocking interface of the standard charger is connected with the power negative electrode of the master battery pack and the slave battery pack respectively; the 485-A interface of the standard charger is connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack respectively; the 485-B interface of the standard charger is connected with the 485-B interface of the master battery pack and the slave battery pack respectively; and the reserved interface of the standard charger is suspended. By defining the interface pins, the compatibility problem of lithium battery double-pack parallel connection and standard charging interface can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0031] One or more embodiments are illustrated by way of example in the figures that are part of this document and which illustrate key / representative principles of the one or more embodiments. Such embodiments do not constitute an exhaustive list of embodiments that can be made as a consequence of the disclosure, and the figures are not necessarily to scale unless otherwise expressly set out in the specification. The figures in the accompanying drawings do not constitute a limitation on the scope of the embodiments.

[0032] Figure 1 A schematic diagram of a double-battery-pack parallel circuit suitable for a standard charging interface according to some embodiments of the application;

[0033] Figure 2 A schematic diagram of interface functions of a standard charging interface according to some embodiments of the application;

[0034] Figure 3 An exemplary structural diagram of the electronic device is disclosed. DETAILED DESCRIPTION

[0035] To make the objects, technical solutions, and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in conjunction with the accompanying drawings of the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0036] First embodiment

[0037] The first embodiment of the present application relates to a double battery pack parallel circuit suitable for a standard charging interface. As shown in Figure 1 The circuit can include:

[0038] A master battery pack and a slave battery pack;

[0039] The master battery pack and the slave battery pack are respectively provided with two power pins: a power positive pole and a power negative pole, and four communication pins: a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface.

[0040] When connected with a standard charger, the power positive pole interface and the power negative pole interface of the standard charger are respectively connected with the power positive pole and the power negative pole of the master battery pack and the slave battery pack.

[0041] The interlock interface of the standard charger is respectively connected with the power negative pole of the master battery pack and the slave battery pack.

[0042] The 485-A interface of the standard charger is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack.

[0043] The 485-B interface of the standard charger is respectively connected with the 485-B interface of the master battery pack and the slave battery pack.

[0044] The reserved interface of the standard charger is suspended.

[0045] The master battery pack and the slave battery pack can be two parallel lithium battery packs, and the internal structures and external interfaces of the two battery packs can be the same.

[0046] The power positive pole is mainly used for connecting the positive output line of the battery pack to provide power source for external devices. It usually has high current carrying capacity to ensure stable output of electric energy. Safety and reliability are considered in design to prevent damage to the battery pack and external devices caused by short circuit, overcurrent, etc.

[0047] The power negative pole is connected with the negative output line of the battery pack to form a complete power loop with the power positive pole serial port. It also needs to have good conductivity and safety. It generally works with the positive pole serial port to ensure stable current flow and normal operation of the device.

[0048] The single-wire serial port uses a single-wire serial communication method inside the master battery pack and the slave battery pack. Compared with other serial ports, the single-wire serial port structure is relatively simple, and only one signal line is needed to realize data transmission. It can be used in some specific application scenarios, such as transmitting a small amount of status information or simple control instructions.

[0049] The address allocation and access detection function multiplexing interface is mainly responsible for allocating the physical address of the battery pack and detecting access. In terms of address allocation, the battery pack can determine its physical address according to different voltage signals. In terms of access detection, the battery pack can determine whether it is connected to the whole vehicle through this interface. It has high precision and reliability, and can accurately allocate addresses and detect access. At the same time, it may communicate with other control systems to realize intelligent battery management.

[0050] 485-A and single-wire serial port multiplexing interface, which can switch between 485 logical communication and single-wire serial port communication. 485 logical communication is usually used in long-distance, multi-point communication scenarios, and can realize data exchange between multiple devices. Single-wire serial port communication is suitable for some simple and low-cost application scenarios. It has flexibility and can choose the appropriate communication method according to different application requirements. During switching, the stability and reliability of communication need to be ensured.

[0051] 485-B interface, mainly used for 485 logical communication, and data exchange with other devices supporting 485 communication. It has high anti-interference ability and long communication distance, and can realize reliable data transmission. It is usually used in industrial automation, intelligent instruments and other fields.

[0052] Figure 2 The interface function of a standard charging interface according to some embodiments of the present application is shown in the schematic diagram. Figure 2 As shown, the standard charger includes: a positive power supply interface, a negative power supply interface, an interlock interface, a 485-A interface, a 485-B interface, and a reserved interface.

[0053] The positive and negative power supply interfaces are connected to the positive and negative power supply serial ports of the master and slave battery packs, respectively. The interlock interface of the standard charger is connected to the negative power supply serial ports of the master and slave battery packs, respectively. The 485-A interface of the standard charger is connected to the 485-A and single-wire serial port multiplexing interface of the master and slave battery packs, respectively. The 485-B interface of the standard charger is connected to the 485-B interface of the master and slave battery packs, respectively. The reserved interface of the standard charger is suspended.

[0054] The scheme provided by the embodiment of the application comprises: a master battery pack and a slave battery pack; the master battery pack and the slave battery pack are respectively provided with two power pins, namely a power positive electrode and a power negative electrode, and four communication pins, namely a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface; when connected with a standard charger, the power positive electrode interface and the power negative electrode interface of the standard charger are connected with the power positive electrode and the power negative electrode of the master battery pack and the slave battery pack respectively; the interlocking interface of the standard charger is connected with the power negative electrode of the master battery pack and the slave battery pack respectively; the 485-A interface of the standard charger is connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack respectively; the 485-B interface of the standard charger is connected with the 485-B interface of the master battery pack and the slave battery pack respectively; and the reserved interface of the standard charger is suspended. By defining the interface pins, the compatibility problem of lithium battery double-pack parallel connection and standard charging interface can be solved.

[0055] In one embodiment, the circuit further comprises an electric vehicle control center.

[0056] The electric vehicle control center comprises:

[0057] The 485-A and single-wire serial port multiplexing pins are connected with the 485-A and single-wire serial port multiplexing interfaces of the master battery pack and the slave battery pack respectively.

[0058] The 485-B communication pins are connected with the 485-B interfaces of the master battery pack and the slave battery pack respectively.

[0059] The master battery pack and the slave battery pack are by default in a single-wire serial port communication mode; when it is detected that the electric vehicle control center is in 485 communication, the communication mode is switched to 485 communication.

[0060] The electric vehicle control center is provided with 485-A and single-wire serial port multiplexing pins and 485-B communication pins, and is further provided with other pins.

[0061] Specifically, as shown in Figure 1 After the two battery packs are confirmed to be connected to the vehicle through ADDR / DETD, the addresses A / B of the battery packs are distinguished by different voltage values provided by the instrument / control center, wherein A is the master battery pack and B is the slave battery pack. The master battery pack and the slave battery pack are by default in a single-wire serial port communication mode; when it is detected that the vehicle is in 485 communication, the communication mode is switched to 485 communication, otherwise the single-wire serial port communication mode is maintained.

[0062] The scheme can realize the switching of the communication mode by connecting the 485-A and single-wire serial port multiplexing pins with the 485-A and single-wire serial port multiplexing interfaces of the master battery pack and the slave battery pack.

[0063] Wherein, the ADDR / DETD pin of the parallel battery pack is used for function multiplexing, and the multiplexing principle is that the resistance of R1 is B- of the battery at the reference ground of the battery end, and R2 and R3 are respectively connected to the positive electrode P+ of the battery at the instrument end.

[0064] In one embodiment, the electric vehicle control center further comprises a first detection pin and a second detection pin;

[0065] A second resistor is arranged between the first detection pin and the second detection pin, the first detection pin is connected in series with the positive electrode of the power supply of the master battery pack and the slave battery pack, and the second detection pin is connected with the address allocation and access detection function multiplexing interface of the slave battery pack.

[0066] The address allocation and access detection function multiplexing interface of the slave battery pack is connected with a reference voltage through a first resistor.

[0067] Wherein, the first resistor and the second resistor have the same resistance value, and whether the slave battery pack is connected to the electric vehicle is detected according to the voltage division value of the second resistor.

[0068] In one embodiment, the electric vehicle control center further comprises a first detection pin and a third detection pin;

[0069] A third resistor is arranged between the first detection pin and the third detection pin, the first detection pin is connected with the positive electrode of the power supply of the master battery pack and the slave battery pack, and the third detection pin is connected with the address allocation and access detection function multiplexing interface of the master battery pack.

[0070] The address allocation and access detection function multiplexing interface of the master battery pack is connected with a reference voltage through a first resistor.

[0071] Wherein, the resistance value of the first resistor is twice the resistance value of the third resistor, and whether the master battery pack is connected to the electric vehicle is detected according to the voltage division value of the third resistor.

[0072] The ADDR / DETD detection principle of the master battery pack A package: the positive electrode P+ of the battery, the instrument end resistor R2, and the battery resistor R0 form the ADDR / DETD detection circuit of the A package, and R2=R1 resistor is designed, wherein the R1 resistor is R resistor in Figure 1 , because the master battery pack and the slave battery pack are the same, Figure 1The R1 resistor is used to distinguish the address of the A battery pack, so the voltage of the R1 resistor is 1 / 2 of the Vbat (Vbat is the voltage of the A battery pack), and the address of the A battery pack is the default address. The voltage of the electrical node between the R1 resistor and the R2 resistor is converted into a high or low level signal. When the A battery pack is not connected to the whole vehicle, the high level signal is the default address, and the low level signal is the address of the A battery pack.

[0073] The ADDR / DETD detection principle of the B battery pack is as follows: the positive electrode P+, the instrument end resistor R3, and the battery resistor R1 form an ADDR / DETD detection circuit of the B battery pack. The R1 resistor is designed to be 2R3, so the voltage of the R1 resistor is 2 / 3 of the Vbat (Vbat is the voltage of the B battery pack), and the address of the B battery pack is the default address. The voltage of the electrical node between the R1 resistor and the R3 resistor is converted into a high or low level signal. When the B battery pack is not connected to the whole vehicle, the high level signal is the default address, and the low level signal is the address of the B battery pack.

[0074] In the scheme, the ADDR / DETD pins of the parallel battery packs are multiplexed, so that the setting of the functional pins is saved, and the peripheral circuit does not need to be increased, and the cost increase problem caused by the peripheral circuit does not need to be considered.

[0075] In one embodiment, the circuit further comprises a controller.

[0076] The controller is connected to the central control of the electric vehicle through a 485 pin, and is used to send the state information of the double battery packs to the controller.

[0077] In one embodiment, the master battery pack and the slave battery pack are connected through a single-wire serial port.

[0078] In the scheme, the A battery pack queries the voltage, current, SOC, fault state, and other information of the B battery pack through a single-wire serial port (1-wire2), to determine the state of the B battery pack and send a corresponding instruction to control the power-on state of the B battery pack. The whole vehicle (instrument / central control) queries the information of the A / B battery pack through 485-A / 1-wire1 and 485-B respectively, and forwards the related information (power-on state, maximum allowed discharge / feedback power, etc.) to the controller (FOC).

[0079] In the scheme, the state information of the double battery packs can be provided to the controller through the central control of the electric vehicle, to control and real-time control the state of the double battery packs. In addition, the single-wire serial port connection between the two battery packs can ensure that the two batteries can communicate information after being put into the electric vehicle, and can avoid information isolation caused by mutual independence.

[0080] Second embodiment

[0081] The second embodiment of the present application relates to an electric vehicle. The electric vehicle provided by the embodiment can include:

[0082] The dual battery pack parallel circuit suitable for a standard charging interface as described in the first embodiment above.

[0083] It can be understood that the electric vehicle provided by the embodiment has the corresponding connection circuit and beneficial effects of the first embodiment above, which will not be described here again.

[0084] In addition, some embodiments of the present application also provide an electronic device. The electronic device can be various forms of digital computers, such as a laptop computer, a desktop computer, a workstation, a personal digital assistant, a server, a blade server, a mainframe computer, and the like. The electronic device can also be various forms of mobile devices, such as a personal digital assistant, a cellular phone, a smart phone, a wearable device, and other similar computing devices.

[0085] The electronic device includes the dual battery pack parallel circuit suitable for a standard charging interface and the electric vehicle as described above. Figure 3 An exemplary structural diagram of the electronic device is disclosed. As shown in Figure 3 The electronic device includes one or more processors 301, a memory 302, and interfaces for connecting components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other by different buses, and can be installed on a common mainboard or in other ways as needed. The processor can process instructions executed within the electronic device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device, such as a display device coupled to the interface. In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple storage devices, if necessary. Similarly, multiple electronic devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Among them, the components shown herein, their connections and relationships, and their functions are only examples, and are not intended to limit the implementation of the present application described and / or claimed herein.

[0086] The electronic device can also include an input device 303 and an output device 304. The processor 301, the memory 302, the input device 303, and the output device 304 can be connected by a bus or other means, Figure 3 for example, by a bus connection.

[0087] The input device 303 can receive input digital or character information, and generate key signal inputs in connection with a user setting of the electronic device and a function control, such as a touch screen, a keypad, a mouse, a track, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 304 can include a display device, an auxiliary lighting device (e.g., an LED), a haptic feedback device (e.g., a vibration motor), etc. The display device can include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. In some embodiments, the display device can be a touch screen.

[0088] To provide for interaction with a user, the electronic device can be a computer. The computer has a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0089] In the embodiments of the present application, the computer program / instruction is stored on the computer readable medium, and the computer program / instruction is executed by the processor to implement the steps of the method provided by any one or more of the embodiments. The computer readable medium can be included in the electronic device described in the above embodiments; or can exist separately and not be assembled into the device. The computer readable medium carries one or more computer readable instructions.

[0090] The memory 302 can be used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs and modules. The processor 301 executes various function applications and data processing of the server by running the non-transitory software programs, instructions and modules stored in the memory 302, so as to implement the program instructions / modules corresponding to the method provided by any one or more of the embodiments.

[0091] The memory 302 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs, and / or data required by at least one function. The data storage area can store data created by the electronic device, etc. In addition, the memory 302 can include a high-speed random access memory and can also include a non-transitory memory such as at least one disk memory device, a flash memory device, or other non-transitory solid state memory device. In some embodiments, the memory 302 can optionally include a memory that is remotely located from the processor 301 and can be connected to the electronic device via a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0092] It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or apparatus.

[0093] The computer-readable medium includes permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0094] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0095] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. For example, the embodiments can be implemented by an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In some embodiments, the software programs of the embodiments can be executed by a processor to implement the above steps or functions. Similarly, the software programs (including related data structures) of the embodiments can be stored in a computer readable recording medium, such as a RAM memory, a magnetic or optical drive or a floppy disk and the like. In addition, some steps or functions of the embodiments can be implemented by hardware, such as a circuit cooperating with a processor to perform the steps or functions.

[0096] The computer program product provided by the embodiments of the present application includes one or more computer programs / instructions, which, when executed by a processor, generate all or part of the processes or functions described in the embodiments of the present application. The computer can be a general purpose computer, a special purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center and the like integrated with one or more available media. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)) and the like.

[0097] The computer program product of the present application can be a computer program embedded in a computer readable medium such as hard disk drive, floppy disk, optical storage, CD-ROM, DVD, Blu-ray Disc, Blu-ray Disc 3D, USB stick, memory card, ROM, RAM, EEPROM, and the like. Here, the computer readable medium is tangible and non-transitory. The computer program product can also be a downloadable computer program such as a computer program distributed over the network or a computer program adapted to be downloaded and installed on demand as an applet, for example, on a platform. The computer readable medium can also be a memory medium, for example, a memory in a server based on demand, for example, a server of an application store. The computer readable medium can also be a transitory medium, for example, an electronic network which transmits computer program over the electronic network. The flowcharts or block diagrams in the drawings are illustrations of possible architectures, functions, and operations according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code which comprises one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by dedicated hardware-based systems which perform the specified functions or operations, or by combinations of dedicated hardware and computer instructions.

[0098] The scope of the application is defined by the claims appended hereto rather than by the description appearing in the application and therefore all changes that come within the meaning and range of equivalents of the claims are to be embraced within their scope. No reference signs in the claims shall be construed as limiting the scope of the claims. Furthermore, the words "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive rather than an exclusive sense, that is, as meaning "including but not limited to". Multiple units or devices recited in a device claim can also be implemented by one unit or device by means of software or hardware. The words "first", "second" and the like, when used in the description or claims, do not imply any particular order but are used for identification only. The embodiments described herein are merely exemplary and not limiting.

[0099] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily make changes or replacements within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be defined by the protection scope of the claims, and the above-described embodiments should be regarded as exemplary and non-limiting.

Claims

1. A dual battery pack parallel circuit suitable for a standard charging interface, characterized in that, The circuit comprises: a master battery pack and a slave battery pack; The master battery pack and the slave battery pack are respectively provided with two power pins, a power positive pole and a power negative pole, and four communication pins, a single-wire serial port, an address allocation and access detection function multiplexing interface, a 485-A and single-wire serial port multiplexing interface, and a 485-B interface. When connected with a standard charger, the power positive pole interface and the power negative pole interface of the standard charger are respectively connected with the power positive pole and the power negative pole of the master battery pack and the slave battery pack. The interlocking interface of the standard charger is respectively connected with the power negative pole of the master battery pack and the slave battery pack. The 485-A interface of the standard charger is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack. The 485-B interface of the standard charger is respectively connected with the 485-B interface of the master battery pack and the slave battery pack. The reserved interface of the standard charger is suspended.

2. The dual battery pack parallel circuit adapted for a standard charging interface of claim 1, wherein, The circuit further comprises an electric vehicle central control. The electric vehicle central control comprises: a 485-A and single-wire serial port multiplexing pin, which is respectively connected with the 485-A and single-wire serial port multiplexing interface of the master battery pack and the slave battery pack; a 485-B communication pin, which is respectively connected with the 485-B interface of the master battery pack and the slave battery pack; The master battery pack and the slave battery pack are by default in a single-wire serial port communication mode; when it is detected that the electric vehicle central control is in 485 communication, the communication mode is switched to 485 communication.

3. The dual battery pack parallel circuit adapted for a standard charging interface of claim 2, wherein, The electric vehicle central control further comprises a first detection pin and a second detection pin. A second resistor is arranged between the first detection pin and the second detection pin, the first detection pin is connected with the power positive pole of the master battery pack and the slave battery pack, and the second detection pin is connected with the address allocation and access detection function multiplexing interface of the slave battery pack. The address allocation and access detection function multiplexing interface of the slave battery pack is connected with a reference voltage through a first resistor. The first resistor and the second resistor have the same resistance value, and whether the slave battery pack is connected with the electric vehicle is detected according to the voltage division value of the second resistor.

4. The dual battery pack parallel circuit adapted for a standard charging interface of claim 2, wherein, The electric vehicle central control further comprises a first detection pin and a third detection pin. A third resistor is arranged between the first detection pin and the third detection pin, the first detection pin is connected with the power positive pole of the master battery pack and the slave battery pack, and the third detection pin is connected with the address allocation and access detection function multiplexing interface of the master battery pack. The address allocation and access detection function multiplexing interface of the master battery pack is connected with a reference voltage through a first resistor. The resistance value of the first resistor is twice the resistance value of the third resistor, and whether the master battery pack is connected with the electric vehicle is detected according to the voltage division value of the third resistor.

5. The dual battery pack parallel circuit adapted for a standard charging interface of claim 2, wherein, The circuit further comprises a controller. The controller is connected with the electric vehicle central control through a 485 pin, and is used to send state information of the double battery packs to the controller.

6. The dual battery pack parallel circuit adapted for a standard charging interface of claim 1, wherein, The master battery pack and the slave battery pack are connected through a single-wire serial port.

7. An electric vehicle, characterized by The electric vehicle includes the dual battery pack parallel circuit suitable for a standard charging interface according to any one of claims 1-6.

Images