Multi-port charger circuit and multi-port charger

Abstract

The utility model provides a multi-port charger circuit and a multi-port charger, which are applied to the technical field of charging, and the multi-port charger circuit comprises an independent fast charging module, a shared fast charging module and a main control chip, the independent fast charging module and the shared fast charging module are both connected with a preset power supply module; and the main control chip is connected with the independent fast charging module and the shared fast charging module. According to the invention, one charging port is arranged in the independent fast charging module, a plurality of charging ports are arranged in the shared fast charging module, and the plurality of charging ports can be controlled through the control function of one main control chip, so that the effect that the plurality of charging ports can charge at the same time is achieved. According to the multi-port charger, only one chip is needed, so that the cost of the multi-port charger can be greatly reduced, and the purpose of reducing the cost of the multi-port charger is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to charging technical field especially, relate to a multi -outlet charger circuit and multi -outlet charger. BACKGROUND

[0002] Nowadays, electronic equipment all need through the charger charges, for satisfying the portability demand of user, the multi -outlet charger on market can simultaneously power supply for multiple terminal equipment. However, the more output interface of multi -outlet charger can be, the more protocol chip required for designing multi -outlet charger, thereby leading to the cost of multi -outlet charger is higher.

[0003] Therefore, how to reduce the cost of multi -outlet charger is the technical problem that the technical personnel in the field have yet to solve. UTILITY MODEL CONTENT

[0004] The application provides a multi -outlet charger circuit and multi -outlet charger, which aims to solve the technical problem of how to reduce the cost of multi -outlet charger.

[0005] To solve the above problems, the application provides a multi -outlet charger circuit, which comprises an independent fast charging module, a shared fast charging module and a master control chip.

[0006] The independent fast charging module and the shared fast charging module are connected with a preset power module.

[0007] The master control chip is connected with the independent fast charging module and the shared fast charging module.

[0008] In an embodiment, the independent fast charging module comprises a USB interface and a first MOS tube and a first resistor.

[0009] The drain electrode of the first MOS tube is connected with the power module, the gate electrode of the first MOS tube is connected with the master control chip, and the source electrode of the first MOS tube is connected with the power voltage pin of the USB interface and the master control chip.

[0010] The configuration channel pin, data positive pin and data negative pin of the USB interface are connected with the master control chip.

[0011] The first end of the first resistor is connected with the ground pin of the USB interface and the master control chip.

[0012] The second end of the first resistor is connected with the master control chip, and the second end of the first resistor is grounded.

[0013] In an embodiment, the shared fast charging module comprises a shared control chip, a first shared unit and a second shared unit.

[0014] The power input pin of the shared control chip is connected with the power module, the enable control pin of the shared control chip is connected with the master control chip, and the power output pin of the shared control chip is connected with the first shared unit and the second shared unit.

[0015] In an embodiment, the shared fast charging module further comprises a first chip protection unit and a second chip protection unit.

[0016] The first end of the first chip protection unit is connected with the power output pin of the shared control chip, and the second end of the first chip protection unit is connected with the first shared unit.

[0017] The first end of the second chip protection unit is connected with the power output pin of the shared control chip, and the second end of the second chip protection unit is connected with the second shared unit.

[0018] In an embodiment, the first shared unit comprises a first shared USB interface, a first MOS tube control subunit and a second resistor.

[0019] The first shared USB interface is connected with the power output pin of the shared control chip and the first MOS tube control subunit.

[0020] The first MOS tube control subunit is connected with the power module and the master control chip.

[0021] The ground pin of the first shared USB interface is connected with the master control chip and the first end of the second resistor, the second end of the second resistor is also connected with the master control chip, and the second end of the second resistor is grounded.

[0022] In an embodiment, the first MOS tube control subunit comprises a second MOS tube, a third MOS tube and a fourth MOS tube.

[0023] The source of the second MOS tube is connected with the power module and the gate of the second MOS tube, the gate of the second MOS tube is connected with the master control chip, and the drain of the second MOS tube is connected with the power output pin of the shared control chip, the power output pin of the first shared USB interface and the master control chip.

[0024] The source and the gate of the third MOS tube are both connected with the master control chip, and the drain of the third MOS tube is connected with the data positive pin of the first shared USB interface.

[0025] The source and the gate of the fourth MOS tube are both connected with the master control chip, and the drain of the fourth MOS tube is connected with the data negative pin of the first shared USB interface.

[0026] In an embodiment, the second sharing unit comprises a second sharing USB interface, a second MOS tube control subunit and a third resistor;

[0027] The second sharing USB interface is connected with the power output pin of the sharing control chip and the second MOS tube control subunit;

[0028] The second MOS tube control subunit is connected with the power module and the master control chip;

[0029] The ground pin of the second sharing USB interface is connected with the master control chip and the first end of the third resistor, the second end of the third resistor is also connected with the master control chip, and the second end of the third resistor is grounded.

[0030] In an embodiment, the second MOS tube control subunit comprises a fifth MOS tube, a sixth MOS tube and a seventh MOS tube;

[0031] The source of the fifth MOS tube is connected with the power module and the gate of the fifth MOS tube, and the gate of the fifth MOS tube is connected with the master control chip, the drain of the fifth MOS tube is connected with the power output pin of the sharing control chip, the power output pin of the second sharing USB interface and the master control chip;

[0032] The source and the gate of the sixth MOS tube are both connected with the master control chip, and the drain of the sixth MOS tube is connected with the data positive pin of the second sharing USB interface;

[0033] The source and the gate of the seventh MOS tube are both connected with the master control chip, and the drain of the seventh MOS tube is connected with the data negative pin of the second sharing USB interface.

[0034] In an embodiment, the multi-port charger circuit further comprises a charging current selection module; the charging current selection module comprises a resistor unit and a capacitor unit;

[0035] The first end of the resistor unit is connected with the master control chip, the second end of the resistor unit is connected with the first end of the capacitor unit, the independent fast charging module and the shared fast charging module;

[0036] The second end of the capacitor unit is grounded.

[0037] In addition, to solve the above problems, the application further provides a multi-port charger, which comprises the multi-port charger circuit according to any one of the above.

[0038] In the embodiment of the present application, the multi-port charger circuit comprises an independent fast charging module, a shared fast charging module and a master control chip; wherein the independent fast charging module and the shared fast charging module are connected with a preset power module; and the master control chip is connected with the independent fast charging module and the shared fast charging module. In the multi-port charger circuit of the present application, one charging port is arranged in the independent fast charging module, and a plurality of charging ports are arranged in the shared fast charging module, and the plurality of charging ports can be controlled by the control function of one master control chip, so that the plurality of charging ports can be charged simultaneously. Compared with the conventional method that each charging port needs a protocol chip for control, since only one chip is needed in the present application, the cost of the multi-port charger can be greatly reduced, so that the purpose of reducing the cost of the multi-port charger is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.

[0040] Figure 1 The module connection schematic diagram of the first embodiment of the multi-port charger circuit of the present application is shown in the figure.

[0041] Figure 2 The schematic diagram of the independent fast charging module 10 in the multi-port charger circuit of the present application is shown in the figure.

[0042] Figure 3 The schematic diagram of the shared fast charging module 20 in the multi-port charger circuit of the present application is shown in the figure.

[0043] Figure 4 The schematic diagram of a specific embodiment of the shared fast charging module 20 in the multi-port charger circuit of the present application is shown in the figure.

[0044] Figure 5 The schematic diagram of the master control chip 30 in the multi-port charger circuit of the present application is shown in the figure.

[0045] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the drawings.

[0046] Explanation of reference numerals:

[0047] 10, independent fast charging module; 20, shared fast charging module; 30, master control chip; 40, power module; 201, shared control chip; 202, first shared unit; 203, second shared unit. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0049] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture, and if the certain posture changes, the directional indications also change accordingly.

[0050] In addition, if the embodiments of the present application involve descriptions such as "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, "and / or" or "and / or" appearing throughout the text means that the three parallel schemes are included, for example, "A and / or B" includes A scheme, or B scheme, or A and B simultaneously satisfy the scheme. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection claimed by the present application.

[0051] Based on the above, the first embodiment of the multi-port charger circuit of the present application is proposed. Please refer to Figure 1 , Figure 1 The first embodiment of the multi-port charger circuit of the present application is a module connection schematic diagram.

[0052] In the present embodiment, the multi-port charger circuit comprises an independent fast charging module 10, a shared fast charging module 20 and a master control chip 30;

[0053] The independent fast charging module 10 and the shared fast charging module 20 are connected with a preset power module 40;

[0054] The master control chip 30 is connected with the independent fast charging module 10 and the shared fast charging module 20.

[0055] It can be understood that the power module 40 is used to provide the electric energy required for charging, the independent fast charging module 10 is provided with one charging port, and the shared fast charging module 20 is provided with a plurality of charging ports. For the plurality of charging ports in the application, the master control chip 30 can autonomously control the charging process of the charging port to the external device based on the connection relationship between the independent fast charging module 10 and the shared fast charging module 20 and the master control chip 30. Therefore, the application can reduce the cost of multiple chips to the cost of one chip, thereby reducing the development cost of the multi-port charger circuit.

[0056] It should be noted that the control function of the master control chip 30 is the function possessed by the master control chip 30 itself, and the application realizes the effect of reducing the development cost through the specific connection relationship between the master control chip 30 and the independent fast charging module 10 and the shared fast charging module 20.

[0057] In a feasible implementation manner, the master control chip 30 in the application can be a chip of the TPS65982 / TPS65983 series of TI, and can also be a chip of the STUSB4500 series of STMicron Electronics, and the application does not limit the specific model of the master control chip 30.

[0058] Please refer to Figure 2 , Figure 2 is a schematic view of the independent fast charging module 10 in the multi-port charger circuit of the application. In Figure 2 , the independent fast charging module 10 comprises a shared USB interface, a first MOS tube and a first resistor.

[0059] The drain electrode of the first MOS tube is connected with the power module 40, the gate electrode of the first MOS tube is connected with the master control chip 30, and the source electrode of the first MOS tube is connected with the power voltage pin of the shared USB interface and the master control chip 30.

[0060] The configuration channel pin, the data positive pin and the data negative pin of the shared USB interface are connected with the master control chip 30.

[0061] The first end of the first resistor is connected with the ground pin of the shared USB interface and the master control chip 30.

[0062] The second end of the first resistor is connected with the master control chip 30, and the second end of the first resistor is grounded.

[0063] It should be noted that in Figure 2In the embodiment, USB_C1 is a USB interface for exclusive use, Q1A is a first MOS tube, and R8 is a first resistor. SRCG_C1, VBUSC_C1, CC1_C1, DP_C1, DM_C1, CC2_C1, CSN_C1, and CSP_C1 are connection points between the main control chip 30. In the embodiment, SRCG_C1 is used to turn on Q1A, VBUSC_C1 is used to access a signal so that the main control chip 30 can determine whether a device is inserted, CC1_C1, DP_C1, DM_C1, and CC2_C1 are communication types of respective output ports, which facilitate communication between a terminal device and the main control chip 30 to determine whether to output fast charging, and CSN_C1 and CSP_C1 are used for output port current detection.

[0064] In the embodiment, when USB_C1 is inserted, the voltage output by the VBUSC_C1 pin of the main control chip 30 will change from high level to low level, and then the SRCG_C1 of the main control chip 30 outputs high level, which can turn on Q1A. When VOUT1+ outputs a 5V voltage, the terminal device connected to the USB_C1 port can communicate through CC1 or DP and DM, so that the voltage required by the terminal device can be output to meet the requirement of fast charging.

[0065] Please refer to Figure 3 In an embodiment, the shared fast charging module 20 includes a shared control chip 201, a first shared unit 202, and a second shared unit 203.

[0066] The power input pin of the shared control chip 201 is connected to the power module 40, the enable control pin of the shared control chip 201 is connected to the main control chip 30, and the power output pin of the shared control chip 201 is connected to the first shared unit 202 and the second shared unit 203.

[0067] It should be noted that the shared control chip 201 is used to cooperatively manage multiple shared units. In an embodiment, the shared control chip 201 can be connected to a third shared unit, a fourth shared unit, and the like in addition to the first shared unit 202 and the second shared unit 203. That is, the number of shared units in the shared fast charging module 20 is not limited in the present application.

[0068] In each shared unit in the shared fast charging module 20, a USB interface is provided in each shared unit to access a terminal device that needs to be charged.

[0069] Please refer to Figure 4 Specifically, the first shared unit 202 includes a first shared USB interface, a first MOS tube control subunit, and a second resistor.

[0070] The first shared USB interface is connected with the power output pin of the shared control chip 201 and the first MOS control subunit;

[0071] The first MOS control subunit is connected with the power module 40 and the master control chip 30;

[0072] The ground pin of the first shared USB interface is connected with the master control chip 30 and the first end of the second resistor, the second end of the second resistor is also connected with the master control chip 30, and the second end of the second resistor is grounded.

[0073] Specifically, the first MOS control subunit includes a second MOS, a third MOS, and a fourth MOS;

[0074] The source of the second MOS is connected with the power module 40 and the gate of the second MOS, and the gate of the second MOS is connected with the master control chip 30, the drain of the second MOS is connected with the power output pin of the shared control chip 201, the power output pin of the first shared USB interface and the master control chip 30;

[0075] The source and the gate of the third MOS are both connected with the master control chip 30, and the drain of the third MOS is connected with the data positive pin of the first shared USB interface;

[0076] The source and the gate of the fourth MOS are both connected with the master control chip 30, and the drain of the fourth MOS is connected with the data negative pin of the first shared USB interface.

[0077] Specifically, the second shared unit 203 includes a second shared USB interface, a second MOS control subunit, and a third resistor;

[0078] The second shared USB interface is connected with the power output pin of the shared control chip 201 and the second MOS control subunit;

[0079] The second MOS control subunit is connected with the power module 40 and the master control chip 30;

[0080] The ground pin of the second shared USB interface is connected with the master control chip 30 and the first end of the third resistor, the second end of the third resistor is also connected with the master control chip 30, and the second end of the third resistor is grounded.

[0081] Specifically, the second MOS control subunit includes a fifth MOS, a sixth MOS, and a seventh MOS;

[0082] The source of the fifth MOS tube is connected with the power module 40 and the gate of the fifth MOS tube, and the gate of the fifth MOS tube is connected with the master control chip 30, and the drain of the fifth MOS tube is connected with the power output pin of the shared control chip 201, the power output pin of the second shared USB interface and the master control chip 30;

[0083] The source and the gate of the sixth MOS tube are both connected with the master control chip 30, and the drain of the sixth MOS tube is connected with the data positive pin of the second shared USB interface;

[0084] The source and the gate of the seventh MOS tube are both connected with the master control chip 30, and the drain of the seventh MOS tube is connected with the data negative pin of the second shared USB interface.

[0085] It should be noted that, in Figure 4 , the first shared USB interface is USB_A1, the second shared USB interface is USB_A2, the second resistor is R19, the third resistor is R20, U1 is the shared control chip 201, the second MOS tube is Q7, the third MOS tube is Q2, the fourth MOS tube is Q1, the fifth MOS tube is Q8, the sixth MOS tube is Q4, and the seventh MOS tube is Q3. LDO_EN1, SRCG_A, SRCG_A1, SRCG_C3, SRCG_A2, CSP_A1, CSN_A1, CSP_A2, CSN_A2, DM_C3, DP_C3, VBUSC_A1 and VBUSC_A2 are all connection places between the master control chip 30. Among them, VBUSC_A1 and VBUSC_A2 are used for output port voltage detection to determine whether there is a device inserted, CSN_A1, CSP_A1, CSN_A2 and CSP_A2 are output port current detection, LDO_EN1 is used to determine whether the shared control chip 201 is enabled, and SRCG_A, SRCG_A1, SRCG_C3 and SRCG_A2 are used to drive the MOS tube.

[0086] In the embodiment, when the USB_A2 is inserted, the VBUSC_A2 voltage of the master chip 30 changes from high level to low voltage, the SRCG_C3 outputs high level, Q8 is opened, VOUT3+ outputs 5V voltage, the SRCG_A2 outputs high level, Q3 and Q4 are opened, at this time, the terminal equipment connected to the USB_A2 port communicates with the output equipment through DP_C3 and DM_C3, and outputs the voltage (9V, 12V, 20V, etc.) required by the equipment. If the USB_A2 has been inserted, at this time, the terminal is inserted into the USB_A1, the VBUSC_A1 voltage of the master chip 30 changes from high level to low voltage, the LOD_EN1 outputs high level, the shared control chip 201 outputs 5V, the SRCG_A1 outputs high level, Q1 and Q2 are opened, at this time, the terminal equipment connected to the USB_A1 port communicates with the output equipment through DP_C3 and DM_C3, and outputs the voltage required by the equipment. It should be noted that if the voltage requested by the USB_A1 and the voltage requested by the USB_A2 are the same at this time, the level output by the SRCG_C3 can open Q8, so that two devices can be fast charged at the same time. If the voltage requested by the USB_A1 and the voltage requested by the USB_A2 are different at this time, the master chip 30 can control the voltage output by VOUT3+ to decrease from the fast charging voltage to 5V, the SRCG_A outputs high level to open Q7, the SRCG_C3 opens Q8, at this time, the VBUSC_A1 and the VBUSC_A2 both output 5V, so as to protect the terminal equipment connected from being burned out.

[0087] Please continue to refer to Figure 4 In a possible implementation, the shared fast charging module 20 further comprises a first chip protection unit and a second chip protection unit.

[0088] The first end of the first chip protection unit is connected with the power output pin of the shared control chip 201, and the second end of the first chip protection unit is connected with the first shared unit 202.

[0089] The first end of the second chip protection unit is connected with the power output pin of the shared control chip 201, and the second end of the second chip protection unit is connected with the second shared unit 203.

[0090] It can be understood that the first chip protection unit includes a first diode D1 and a resistor R1. The anode of the first diode is connected to the power output pin of the sharing control chip 201, the cathode of the first diode is connected to one end of R1, and the other end of R1 is connected to the first shared USB interface in the first sharing unit 202. The second chip protection unit includes a second diode D1 and a resistor R2. The anode of the second diode is connected to the power output pin of the sharing control chip 201, the cathode of the second diode is connected to one end of R2, and the other end of R2 is connected to the second shared USB interface in the second sharing unit 203.

[0091] In the embodiment, the application can avoid the problem of damage of the shared USB interface caused by the voltage output by the sharing control chip 201 being too large by connecting the diode and the resistor in series between the power output pin of the sharing control chip 201 and the power output pin of the shared USB interface, thereby prolonging the service life of the multi-port charger circuit.

[0092] In a possible implementation, the multi-port charger circuit further includes a charging current selection module; the charging current selection module includes a resistor unit and a capacitor unit.

[0093] The first end of the resistor unit is connected to the master control chip 30, and the second end of the resistor unit is connected to the first end of the capacitor unit, the independent fast charging module 10, and the shared fast charging module 20.

[0094] The second end of the capacitor unit is grounded.

[0095] Please refer to Figure 5 , Figure 5 The connection diagram of the master control chip 30 of the multi-port charger circuit is shown in FIG. 12. Figure 5 In FIG. 12, U2 is the master control chip 30, the resistor unit includes R200, R24, R25, R26, R27, R28, R29, and R30, and the capacitor unit includes C24, C29, C31, C33, C34, C35, C36, and C38.

[0096] In the embodiment, the application can filter the signals accessed by the independent fast charging module 10 and the shared fast charging module 20 through the capacitor unit and the resistor unit, thereby accurately implementing fast charging of the terminal device based on the communication signals of the accessed terminal device.

[0097] In addition, it should be further pointed out that Figure 5The pins of the main control chip 30 can be connected with the independent fast charging module 10 and the shared fast charging module 20 through the connection of "LDO_EN1", "SRCG_A2", "VBUSC_C1", etc. The FBO3 connection in the main control chip 30 can be externally connected with a DCDC circuit to achieve the purpose of regulating the VOUT3+ output voltage. Figure 2 、 Figure 4 and Figure 5 The multi-port charger circuit composed of the above can independently fast charge the terminal equipment connected with the USB_C1, and fast charge the terminal equipment connected when only the USB_A1 or the USB_A2 is inserted. The independent fast charging module 10 will not be affected by the shared fast charging module 20, and the output voltage of each USB interface in the shared fast charging module 20 can be automatically regulated by the multi-port charger circuit when multiple terminal equipments are connected, so as to achieve the purpose of multi-port fast charging.

[0098] In the embodiment, the independent fast charging module 10 in the multi-port charger circuit is provided with one charging port, and the shared fast charging module 20 is provided with multiple charging ports, which can be controlled by the control function of the main control chip 30, so as to achieve the effect that multiple charging ports can be charged at the same time. Compared with the traditional method that each charging port needs a protocol chip for control, the application only needs to use one chip, so the cost of the multi-port charger can be greatly reduced, thereby achieving the purpose of reducing the cost of the multi-port charger.

[0099] In addition, the application also provides a multi-port charger, which comprises the multi-port charger circuit as described above.

[0100] The above is only an optional embodiment of the application, and does not limit the patent range of the application, and any equivalent structural transformation made by using the content of the application specification and drawings, or direct / indirect application in other related technical fields under the application concept of the application is included in the patent protection range of the application.

Claims

1. A multi-port charger circuit, characterized in that, The multi-port charger circuit includes: an independent fast charging module, a shared fast charging module, and a main control chip; Both the independent fast charging module and the shared fast charging module are connected to a preset power module; The main control chip is connected to the independent fast charging module and the shared fast charging module.

2. The multi-port charger circuit as described in claim 1, characterized in that, The independent fast charging module includes: a dedicated USB interface, a first MOSFET, and a first resistor; The drain of the first MOSFET is connected to the power module, the gate of the first MOSFET is connected to the main control chip, and the source of the first MOSFET is connected to the power voltage pin of the dedicated USB interface and the main control chip. The configuration channel pin, positive data pin, and negative data pin of the dedicated USB interface are connected to the main control chip; The first end of the first resistor is connected to the ground pin of the dedicated USB interface and the main control chip; The second end of the first resistor is connected to the main control chip, and the second end of the first resistor is grounded.

3. The multi-port charger circuit as described in claim 1, characterized in that, The shared fast charging module includes: a shared control chip, a first shared unit, and a second shared unit; The power input pin of the shared control chip is connected to the power module, the enable control pin of the shared control chip is connected to the main control chip, and the power output pin of the shared control chip is connected to the first shared unit and the second shared unit.

4. The multi-port charger circuit as described in claim 3, characterized in that, The shared fast charging module further includes: a first chip protection unit and a second chip protection unit; The first end of the first chip protection unit is connected to the power output pin of the shared control chip, and the second end of the first chip protection unit is connected to the first shared unit. The first end of the second chip protection unit is connected to the power output pin of the shared control chip, and the second end of the second chip protection unit is connected to the second shared unit.

5. The multi-port charger circuit as described in claim 3, characterized in that, The first shared unit includes: a first shared USB interface, a first MOS transistor control subunit, and a second resistor; The first shared USB interface is connected to the power output pin of the shared control chip and the first MOS transistor control subunit; The first MOS transistor control subunit is connected to the power module and the main control chip; The ground pin of the first shared USB interface is connected to the main control chip and the first end of the second resistor. The second end of the second resistor is also connected to the main control chip, and the second end of the second resistor is grounded.

6. The multi-port charger circuit as described in claim 5, characterized in that, The first MOS transistor control subunit includes: a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; The source of the second MOSFET is connected to the power module and the gate of the second MOSFET, and the gate of the second MOSFET is connected to the main control chip. The drain of the second MOSFET is connected to the power output pin of the shared control chip, the power output pin of the first shared USB interface, and the main control chip. The source and gate of the third MOS transistor are both connected to the main control chip, and the drain of the third MOS transistor is connected to the positive data pin of the first shared USB interface. The source and gate of the fourth MOS transistor are both connected to the main control chip, and the drain of the fourth MOS transistor is connected to the negative data pin of the first shared USB interface.

7. The multi-port charger circuit as described in claim 3, characterized in that, The second shared unit includes: a second shared USB interface, a second MOSFET control subunit, and a third resistor; The second shared USB interface is connected to the power output pin of the shared control chip and the second MOS transistor control subunit; The second MOS transistor control subunit is connected to the power module and the main control chip; The ground pin of the second shared USB interface is connected to the main control chip and the first end of the third resistor. The second end of the third resistor is also connected to the main control chip, and the second end of the third resistor is grounded.

8. The multi-port charger circuit as described in claim 7, characterized in that, The second MOS transistor control subunit includes: a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; The source of the fifth MOS transistor is connected to the power module and the gate of the fifth MOS transistor, and the gate of the fifth MOS transistor is connected to the main control chip. The drain of the fifth MOS transistor is connected to the power output pin of the shared control chip, the power output pin of the second shared USB interface, and the main control chip. The source and gate of the sixth MOS transistor are both connected to the main control chip, and the drain of the sixth MOS transistor is connected to the positive data pin of the second shared USB interface. The source and gate of the seventh MOS transistor are both connected to the main control chip, and the drain of the seventh MOS transistor is connected to the negative data pin of the second shared USB interface.

9. The multi-port charger circuit as described in claim 1, characterized in that, The multi-port charger circuit further includes: a charging current selection module; the charging current selection module includes a resistor unit and a capacitor unit; The first end of the resistor unit is connected to the main control chip, and the second end of the resistor unit is connected to the first end of the capacitor unit, the independent fast charging module, and the shared fast charging module. The second terminal of the capacitor unit is grounded.

10. A multi-port charger, characterized in that, The multi-port charger includes the multi-port charger circuit as described in any one of claims 1 to 9.

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