Packaging structure, chip and electronic equipment

Abstract

The embodiment of the utility model discloses a packaging structure, a chip and electronic equipment, relates to the technical field of integrated circuit packaging, and can effectively reduce return loss of signals and improve signal integrity. The packaging structure comprises an interconnection layer and at least one crystal grain bearing cavity. The crystal grain bearing cavity is formed by the interconnection layer located on a supporting plate and at least one opening of the supporting plate; the interconnection layer comprises a metal pattern layer and a dielectric layer which are alternately stacked, and each opening penetrates through the supporting plate and exposes the surface of the metal pattern layer; wherein the surface of the exposed metal pattern layer forms a crystal grain bearing surface of the crystal grain bearing cavity, and the crystal grain bearing surface is used for being coupled with crystal grains placed in the crystal grain bearing cavity. The embodiment of the utility model is suitable for chip packaging.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit packaging technical field especially, relate to a kind of packaging structure, chip and electronic equipment. BACKGROUND

[0002] With the continuous improvement of chip performance such as CPU (central processing unit) and GPU (graphics processing unit), the signal transmission rate is also getting faster and faster. Consequently, the design of the packaging substrate faces great challenges, and it is necessary to realize the interconnection of high-speed signals in a limited space.

[0003] In the related art, the packaging substrate is mostly supported by a core layer, and a buildup layer is formed on both sides of the core layer for signal transmission. The signals on one side of the core layer need to be transmitted to the other side of the core layer through the drill holes in the core layer. Since the diameter of the drill holes in the core layer is relatively large, impedance mismatching may occur in the signal transmission path, resulting in a large echo loss of the signals, which seriously affects the signal integrity. SUMMARY

[0004] Therefore, the utility model embodiment provides a packaging structure, a chip and an electronic device, which can effectively reduce the echo loss of signals and improve the signal integrity.

[0005] In a first aspect, the utility model embodiment provides a packaging structure, which includes an interconnection layer and at least one die carrier cavity. The die carrier cavity is formed by the interconnection layer on a support plate and at least one opening of the support plate. The interconnection layer includes alternately stacked metal pattern layers and dielectric layers. Each opening penetrates the support plate and exposes the surface of the metal pattern layer. The exposed surface of the metal pattern layer forms a die carrier surface of the die carrier cavity, which is used to couple with a die placed in the die carrier cavity.

[0006] In an embodiment, the metal pattern layer includes a first layer of metal pattern layer, which is located on the surface of the support plate. The first layer of metal pattern layer includes a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the die carrier surface.

[0007] In an embodiment, the first layer of metal pattern layer further includes a metal pattern portion, wherein the width of the metal pattern portion is greater than the width of the first metal contact.

[0008] In an embodiment, the first metal contact includes a metal bump.

[0009] In one embodiment, the metal pattern layers include a last layer of the metal pattern layers, the last layer of the metal pattern layers is located on a surface of a medium layer away from the first layer of the metal pattern layers; and the last layer of the metal pattern layers includes a plurality of second metal contacts.

[0010] In one embodiment, the second metal contacts include pads.

[0011] In one embodiment, each of the medium layers includes a conductive via, and different metal pattern layers are coupled through corresponding conductive vias.

[0012] In a second aspect, an embodiment of the utility model also provides a chip, including a die and any one of the packaging structures provided by the embodiments of the utility model, wherein the die is arranged in the die bearing cavity and is coupled with the die bearing surface.

[0013] In one embodiment, the chip further includes an adhesive layer between the die and the die bearing cavity, used for bonding the die and the die bearing cavity.

[0014] In one embodiment, the number of the die bearing cavities is at least two; and the chip further includes a packaging substrate, the interconnection layer is used as an interlayer between the die and the packaging substrate, and is coupled with the die and the packaging substrate respectively.

[0015] In a third aspect, an embodiment of the utility model also provides an electronic device, including a printed circuit board and any one of the chips provided by the embodiments of the utility model, and the chip is arranged on the printed circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the utility model or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0017] Figure 1 One structural schematic view of the packaging structure provided by the embodiments of the utility model;

[0018] Figure 2 Another structural schematic view of the packaging structure provided by the embodiments of the utility model;

[0019] Figure 3 One structural schematic view of the chip provided by the embodiments of the utility model;

[0020] Figure 4 Another schematic diagram of the chip structure provided for an embodiment of this utility model;

[0021] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0022] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0023] It should be understood that the described embodiments are merely some embodiments of this utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0024] This invention provides a packaging structure that can effectively reduce signal return loss and improve signal integrity.

[0025] like Figure 1 As shown, the packaging structure 42 provided in the embodiment of this utility model may include an interconnect layer 103 and at least one die carrier cavity 80; the die carrier cavity 80 is formed by the interconnect layer 103 located on the support plate 116 and at least one opening 120 of the support plate 116; the interconnect layer 103 includes alternating stacked metal pattern layers 114 and dielectric layers 110, each opening 120 penetrating the support plate 116 and exposing the metal pattern layers 114; wherein, the exposed metal pattern layers 114 form the die carrier surface 1031 of the die carrier cavity 80, and the die carrier surface 1031 is used for coupling with the die placed in the die carrier cavity 80.

[0026] The packaging structure 42 provided in this embodiment of the present invention has an interconnect layer 103 disposed on a support plate 116 to provide support for the interconnect layer 103. An opening 120 in the interconnect layer 103 and the support plate 116 can form a die carrier cavity 80. A metal pattern layer 114 exposed from the opening 120 can form a die carrier surface 1031. Since the die carrier surface 1031 can be used to couple with the die placed in the die carrier cavity 80, signals in the die can enter the interconnect layer 103 through the die carrier surface 1031 and be transmitted through the metal pattern layer 114 in the interconnect layer 103. The entire packaging structure has no core layer, and there is no signal transmission from one side of the core layer to the other. Therefore, it can greatly improve the impedance consistency in the signal transmission line, effectively reduce signal return loss, and improve signal integrity.

[0027] In an embodiment of the present application, the support plate 116 mainly supports the interconnection layer 103 and does not participate in signal transmission, thus, as long as the plate material with hardness and strength meeting the support requirement can be used as the support plate 116. For example, in an embodiment of the present application, the support plate 116 can include any one of the following: a resin plate, a glass plate, and a ceramic plate.

[0028] In an embodiment of the present application, the support plate 116 can be provided with an opening 120, and the specific position of the opening 120 on the support plate 116 is not limited, as long as the support effect of the support plate 116 on the interconnection layer 103 is not affected. For example, in one example, the opening 120 can be located at the center of the support plate 116.

[0029] The shape and size of the opening 120 can be adapted to the shape and size of the crystal grain, so as to place and accommodate the corresponding crystal grain in the crystal grain bearing cavity 80. Among them, the adaptation means that after the crystal grain is placed in the corresponding crystal grain bearing cavity 80, the crystal grain can be coupled with the crystal grain bearing surface 1031, and excessive space waste is not caused. For example, in one example, the shape of the opening 120 can be the same as that of the crystal grain, and the size of the opening can be slightly larger than that of the crystal grain, for example, the side length of the opening 120 can be 1-2 mm larger than the corresponding side length of the crystal grain.

[0030] Further, according to the different number of crystal grains to be packaged, the number of openings 120 in the support plate 116 can also be correspondingly different. For example, in one example, the number of openings 120 can be one, and in another example, the number of openings 120 can also be two or more, wherein each opening 120 forms a crystal grain bearing cavity 80 for placing and accommodating a corresponding crystal grain.

[0031] In an embodiment of the present application, the interconnection layer 103 can include alternately stacked metal pattern layers 114 and dielectric layers 110. Among them, the metal pattern layer 114 can be used for signal transmission, and the dielectric layer 110 can be used for insulating and isolating different metal pattern layers 114.

[0032] In a specific implementation, the dielectric layer 110 can include various insulating materials, for example, in one example, the material of the dielectric layer 110 can include polyimide, and in another example, the material of the dielectric layer 110 can include an ABF film. The materials of the dielectric layers 110 can be the same or different, and the embodiments of the present application do not limit this.

[0033] The number of metal pattern layers 114 can be multiple, and according to the different positions of the metal pattern layers 114 in the interconnection layer 103, the specific structures of the metal pattern layers 114 can also be different. Specifically, as shown in FIG. 1, the metal pattern layers 114 in the interconnection layer 103 can include a first metal pattern layer 1141, a second metal pattern layer 1142, and a third metal pattern layer 1143. Figure 2As shown, the metal pattern layer 114 can include a first layer of metal pattern layer 1141, which is located on the surface of the support plate 116, and the first layer of metal pattern layer 1141 includes a plurality of first metal contacts 21, and the opening 120 exposes the surface of the plurality of first metal contacts 21 as the die carrier surface 1031. In a specific implementation, the specific form of the first metal contact 21 can be set and adjusted as needed, for example, in one example, the first metal contact 21 can include a metal bump. The first metal contact 21 can be used for electrical connection with the die.

[0034] In an embodiment of the present application, the first layer of metal pattern layer 1141 can also include a metal pattern portion 23, wherein the width of the metal pattern portion 23 is greater than the width of the first metal contact 21. The metal pattern portion 23 can be located in the region of the first layer of metal pattern layer 1141 that is not exposed by the opening 120.

[0035] Again referring to Figure 2 In another embodiment of the present application, the metal pattern layer 114 can also include a last layer of metal pattern layer 1142, which is located on the surface of the dielectric layer 110 away from the first layer of metal pattern layer 1141; the last layer of metal pattern layer 1142 can include a plurality of second metal contacts 22. In one example, the second metal contact 22 can include a solder pad. The second metal contact 22 can be used to electrically connect the package structure with other components or devices, such as a mainboard.

[0036] Further, in addition to the first layer of metal pattern layer 1141 and the second layer of metal pattern layer 1142, in an embodiment of the present application, the metal pattern layer 114 can also include at least one metal wiring layer 1143, which can be located between the first layer of metal pattern layer 1141 and the second layer of metal pattern layer 1142. The metal wiring layer 1143 can be used for redistribution of signals led out of one die, or for interconnection of two or more dies, and the embodiments of the present application do not limit this. In an embodiment of the present application, the first layer of metal pattern layer 1141, the second layer of metal pattern layer 1142 and the metal wiring layer 1143 can be separated by different dielectric layers 110. Each dielectric layer 110 can include a conductive via 104, and different metal pattern layers 114 such as the first layer of metal pattern layer 1141, the second layer of metal pattern layer 1142 and the metal wiring layer 1143 can be coupled through the corresponding conductive via 104. Compared with the mechanical drilling of the core layer in the prior art, the size of each conductive via 104 in the interconnection layer 103 is small and uniform, so there is no impedance discontinuity and the resulting return loss.

[0037] Corresponding to the packaging structure provided by the foregoing embodiments, as shown in Figure 3 The embodiment of the present application also provides a chip 4, which can include a die 101 and a packaging structure 42 provided by any of the foregoing embodiments. The die 101 is disposed in the die carrying cavity 80 and coupled to the die carrying surface 1031.

[0038] Since the chip 4 provided by the embodiment of the present application includes any of the packaging structures 42 provided by the foregoing embodiments, the corresponding beneficial technical effects can also be achieved, which are described in detail above and will not be repeated here.

[0039] In an embodiment, the chip 4 can further include an adhesive layer between the die 101 and the die carrying cavity 80, for bonding the die 101 and the die carrying cavity 80.

[0040] Further, as shown in Figure 4 In an embodiment of the present application, the number of die carrying cavities 80 can be at least two; the chip 4 can further include a packaging substrate 3, and the interconnection layer 103 can serve as an interposer between the die 101 and the packaging substrate 3, coupled to the die 101 and the packaging substrate 3 respectively, thereby forming a 2.5D packaging for the die 101. In this way, the interconnection layer 103 can interconnect a part of signals between the dies 101, and transmit another part of signals in the dies 101 to the packaging substrate 3, for interconnection or redistribution through the packaging substrate 3.

[0041] Correspondingly, as shown in Figure 5 The embodiment of the present application also provides an electronic device 5, which can include a printed circuit board 51 and any of the chips 4 provided by the foregoing embodiments, and the chip 4 is disposed on the printed circuit board 51.

[0042] Since the electronic device 5 provided by the embodiment of the present application includes any of the chips 4 provided by the foregoing embodiments, the corresponding beneficial technical effects can also be achieved, which are described in detail above and will not be repeated here.

[0043] It is to be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0044] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments.

[0045] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A package structure, characterized by, The interconnection layer and at least one die-carrying cavity; the die-carrying cavity is formed by the interconnection layer on the support plate and at least one opening of the support plate; The interconnection layer comprises alternately stacked metal pattern layers and dielectric layers, each of the openings penetrates the support plate and exposes a surface of the metal pattern layer; wherein the exposed surface of the metal pattern layer forms a die-carrying surface of the die-carrying cavity, which is used to couple with a die placed in the die-carrying cavity.

2. The package structure of claim 1, wherein, The metal pattern layer comprises a first layer of metal pattern layer located on the surface of the support plate, the first layer of metal pattern layer comprises a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the die-carrying surface.

3. The package structure of claim 2, wherein, The first layer of metal pattern layer further comprises a metal pattern portion, wherein the width of the metal pattern portion is greater than the width of the first metal contact.

4. The package structure of claim 2, wherein, The first metal contact comprises a metal bump.

5. The package structure of claim 2, wherein, The metal pattern layer comprises a last layer of the metal pattern layer located on the surface of the dielectric layer away from the first layer of the metal pattern layer; the last layer of the metal pattern layer comprises a plurality of second metal contacts.

6. The package structure of claim 5, wherein, The second metal contact comprises a solder pad.

7. The package structure of claim 1, wherein, Each of the dielectric layers comprises a conductive via, and different metal pattern layers are coupled through corresponding conductive vias.

8. A chip, characterized by The chip of any one of claims 1-7, wherein the die is disposed in the die-carrying cavity and coupled with the die-carrying surface.

9. The chip of claim 8, wherein, Further comprising an adhesive layer between the die and the die-carrying cavity, for adhering the die and the die-carrying cavity.

10. The chip of claim 8, wherein, The number of the die-carrying cavities is at least two; the chip further comprises a package substrate, and the interconnection layer serves as an interposer between the die and the package substrate and is coupled with the die and the package substrate, respectively.

11. An electronic device, comprising: The printed circuit board and the chip of any one of claims 8-10, wherein the chip is disposed on the printed circuit board.

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