Light emitting diode

Abstract

The utility model provides a light emitting diode, comprising an epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, the doping type of the first semiconductor layer is opposite to that of the second semiconductor layer, a first through hole is formed in the epitaxial layer, and the first through hole penetrates through the second semiconductor layer and the active layer and exposes the first semiconductor layer; the first DBR layer is located on the inner wall of the first through hole and extends to the surface of the second semiconductor layer on the periphery of the first through hole, a second through hole is formed in the first DBR layer on the periphery of the first through hole, and the second through hole penetrates through the first DBR layer and exposes the second semiconductor layer; the first bottom anti-reflection layer is at least located on a part of the surface, far away from the epitaxial layer, of the first DBR layer at the opening of the first through hole, and the first bottom anti-reflection layer absorbs near ultraviolet light and transmits visible light; the first metal reflection layer is at least located on the face, away from the epitaxial layer, of the first bottom anti-reflection layer at the opening of the first through hole, the first metal reflection layer further extends into the second through hole, and the first metal reflection layer is electrically connected with the second semiconductor layer. According to the utility model, the light emitting diode has high reflection capability, and meanwhile, the photoetching line width precision and the photoetching process stability can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially relates to a light emitting diode. BACKGROUND

[0002] The performance improvement of light emitting diodes has been a common concern of academia and industry, and the mainstream light emitting diode in the market is currently using DBR (Distributed Bragg Reflection) and other mirrors. The advantage of DBR structure scheme is that it can significantly improve the reflection ability of the central wavelength of the light emitting diode in the axial direction, and there is no problem of reduced reflectivity caused by electromigration and easy physical and chemical changes of metal-based mirrors.

[0003] However, the use of DBR structure will adversely affect the manufacturing process of light emitting diodes, which involves photolithography & patterning, mainly including the following aspects: on the one hand, the tens of pairs of high and low refractive index dielectric layer structures with relatively thick layers pose a challenge to the etching process, and it is difficult to obtain a good etching sidewall morphology; on the other hand, with the improvement of the performance of light emitting diodes, the requirement for process line width precision is getting higher and higher. This requires the use of high-precision stepper photolithography equipment for micron-level photolithography. However, due to the use of heteroepitaxy technology in light emitting diodes, the wafer warpage is large, which in turn affects the line width precision and uniformity during high-precision photolithography. The greater challenge lies in the instability of the reflectivity of the near-ultraviolet light (365nm line ~ 436nm G-line) of the photolithography machine at different angles, which makes it impossible to guarantee the photolithography line width precision and photolithography process stability. This has been a technical difficulty that has plagued the industry.

[0004] Therefore, how to make the light emitting diode have high reflectivity while improving the photolithography line width precision and photolithography process stability is a technical problem that needs to be solved. UTILITY MODEL CONTENTS

[0005] The utility model aims at providing a light emitting diode, which has high reflectivity while improving the photolithography line width precision and photolithography process stability.

[0006] To achieve the above-mentioned purpose, the utility model provides a light emitting diode, which comprises:

[0007] An epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence, the doping type of the first semiconductor layer and the second semiconductor layer being opposite, a first through hole being formed in the epitaxial layer, the first through hole penetrating through the second semiconductor layer and the active layer and exposing the first semiconductor layer;

[0008] a first DBR layer located on an inner wall of the first via and extending to a surface of the second semiconductor layer at a periphery of the first via, the first DBR layer at the periphery of the first via having a second via formed therein, the second via penetrating the first DBR layer and exposing the second semiconductor layer;

[0009] a first bottom anti-reflective layer located on at least a portion of a surface of the first DBR layer at the first via opening away from the epitaxial layer, the first bottom anti-reflective layer absorbing near-ultraviolet light and transmitting visible light;

[0010] a first metal reflective layer located on at least one side of the first bottom anti-reflective layer at the first via opening away from the epitaxial layer, the first metal reflective layer further extending into the second via, the first metal reflective layer being electrically connected to the second semiconductor layer.

[0011] Optionally, the first bottom anti-reflective layer further extends to a surface of the first DBR layer in the first via, and the first bottom anti-reflective layer further extends to a surface of the first DBR layer away from the first via, the second via further penetrating the first bottom anti-reflective layer.

[0012] Optionally, the first metal reflective layer is located on an inner wall of the second via, or the first metal reflective layer fills the second via.

[0013] Optionally, the first metal reflective layer does not cover an edge of the first bottom anti-reflective layer near a center of the first via.

[0014] Optionally, the light-emitting diode further comprises:

[0015] an ohmic contact layer located between the second semiconductor layer and the first DBR layer at a periphery of the first via, the second via exposing the ohmic contact layer, the first metal reflective layer being electrically connected to the ohmic contact layer.

[0016] Optionally, the ohmic contact layer does not cover an edge of the second semiconductor layer near the first via.

[0017] Optionally, the first DBR layer has an opening exposing a bottom wall of the first via, the light-emitting diode further comprising:

[0018] a first current spreading layer located on a side of the first metal reflective layer away from the epitaxial layer;

[0019] a first isolation dielectric layer located in the first via and the opening and extending to a side of the first current spreading layer away from the epitaxial layer;

[0020] A second current spreading layer is located in the first isolation medium layer in the first via and the opening and extends to a surface of the first isolation medium layer away from the epitaxial layer at a periphery of the first via.

[0021] Optionally, the light emitting diode further comprises a substrate; when the first semiconductor layer is of N type and the second semiconductor layer is of P type, the substrate is located at a surface of the second current spreading layer away from the epitaxial layer.

[0022] Optionally, the second current spreading layer extends to the entire surface of the first isolation medium layer away from the epitaxial layer at the periphery of the first via, and the light emitting diode further comprises:

[0023] A second isolation medium layer is located at a surface of the first isolation medium layer away from the epitaxial layer and at a surface of the second current spreading layer away from the epitaxial layer.

[0024] A first electrode penetrates the second isolation medium layer and the first isolation medium layer to connect with the first current spreading layer, and the first electrode further extends to a surface of the second isolation medium layer away from the epitaxial layer.

[0025] A second electrode penetrates the second isolation medium layer to connect with the second current spreading layer, and the second electrode further extends to a surface of the second isolation medium layer away from the epitaxial layer.

[0026] Optionally, the light emitting diode further comprises:

[0027] A second DBR layer, a second bottom anti-reflection layer and a second metal reflection layer are stacked in the light emitting diode from inside to outside in sequence.

[0028] Optionally, the light emitting diode further comprises a substrate; when the first semiconductor layer is of N type and the second semiconductor layer is of P type, the substrate is located at a surface of the second current spreading layer away from the epitaxial layer.

[0029] Optionally, the second current spreading layer extends to the entire surface of the first isolation medium layer away from the epitaxial layer at the periphery of the first via, and the light emitting diode further comprises:

[0030] A bonding structure is located between the second current spreading layer and the substrate.

[0031] Optionally, an edge of the light emitting diode is formed with a step, a sidewall of the step comprises at least the epitaxial layer, the first DBR layer and the first metal reflection layer, and a bottom wall of the step comprises at least the first current spreading layer and the first isolation medium layer; the light emitting diode further comprises:

[0032] a first electrode on a bottom wall of the step, the first electrode extending from a surface of the first current spreading layer to a surface of the first isolation medium layer;

[0033] a second electrode on a side of the substrate away from the epitaxial layer.

[0034] Optionally, the light emitting diode further comprises:

[0035] a passivation layer on a side of the first semiconductor layer away from the second semiconductor layer and on the surface of the first isolation medium layer outside the first electrode.

[0036] Optionally, the light emitting diode further comprises:

[0037] a second DBR layer, a second bottom anti-reflection layer and a second metal reflection layer stacked in turn on a sidewall of the step, the first electrode being on a side of the second metal reflection layer away from the second DBR layer.

[0038] Optionally, a side of the first semiconductor layer away from the second semiconductor layer has a roughened surface.

[0039] Optionally, an area of the second DBR layer, the second bottom anti-reflection layer and the second metal reflection layer is 50% to 100% of an area of an optical window of the light emitting diode.

[0040] Optionally, the first DBR layer and the second DBR layer each comprise a first transparent medium layer and a second transparent medium layer alternately stacked in period, the first transparent medium layer having a refractive index lower than that of the second transparent medium layer, a thickness of a single layer of the first transparent medium layer and a thickness of a single layer of the second transparent medium layer being λ / (4*n1) and λ / (4*n2) respectively, where λ is a light emitting wavelength of the light emitting diode, and n1 and n2 are refractive indexes of the first transparent medium layer and the second transparent medium layer respectively corresponding to the light emitting wavelength.

[0041] Optionally, the first bottom anti-reflection layer and the second bottom anti-reflection layer are an insulating medium layer, a metal layer or a transparent conductive layer.

[0042] Compared with the prior art, the light emitting diode has the advantages that: the light emitting diode comprises an epitaxial layer, a first DBR layer, a first bottom anti-reflection layer and a first metal reflection layer, the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, the doping type of the first semiconductor layer is opposite to that of the second semiconductor layer, a first through hole is formed in the epitaxial layer, the first through hole penetrates the second semiconductor layer and the active layer and exposes the first semiconductor layer, the first DBR layer is located on the inner wall of the first through hole and extends to the surface of the second semiconductor layer at the periphery of the first through hole, a second through hole is formed in the first DBR layer at the periphery of the first through hole, the second through hole penetrates the first DBR layer and exposes the second semiconductor layer, the first bottom anti-reflection layer is located on at least the part of the surface of the first DBR layer away from the epitaxial layer at the opening of the first through hole, the first bottom anti-reflection layer absorbs near-ultraviolet light and transmits visible light, the first metal reflection layer is located on at least one side of the first bottom anti-reflection layer away from the epitaxial layer at the opening of the first through hole, the first metal reflection layer further extends into the second through hole, and the first metal reflection layer is electrically connected with the second semiconductor layer, so that the light emitting diode has high reflection capacity, and the photolithography line width precision and photolithography process stability are improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a structure schematic view of the light emitting diode of an embodiment of the utility model;

[0044] Figure 2 is a device structure schematic view in the process of manufacturing Figure 1 the light emitting diode shown.

[0045] Figure 3 is a structure schematic view of the light emitting diode of an embodiment of the utility model;

[0046] Figure 4 is a device structure schematic view in the process of manufacturing Figure 3 the light emitting diode shown.

[0047] Among them, the accompanying Figures 1-4 drawings are explained as follows:

[0048] 10-substrate; 111-first semiconductor layer; 112-active layer; 113-second semiconductor layer; 121-first DBR layer; 122-first bottom anti-reflection layer; 123-first metal reflection layer; 131-first via hole; 132-second via hole; 133-opening; 14-ohmic contact layer; 151-first current spreading layer; 152-second current spreading layer; 161-first isolation dielectric layer; 162-second isolation dielectric layer; 171-first electrode; 172-second electrode; 181-first bonding layer; 182-second bonding layer; 19-passivation layer; 21-second DBR layer; 22-second bottom anti-reflection layer; 23-second metal reflection layer; 24-substrate. DETAILED DESCRIPTION

[0049] To make the objects, advantages and features of the present application clearer, the following further describes the light emitting diode provided by the present application. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0050] The present application provides a light emitting diode, comprising: an epitaxial layer, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence, the doping type of the first semiconductor layer is opposite to that of the second semiconductor layer, a first via hole is formed in the epitaxial layer, the first via hole penetrates the second semiconductor layer and the active layer and exposes the first semiconductor layer; a first DBR layer, located on the inner wall of the first via hole and extending to the surface of the second semiconductor layer at the periphery of the first via hole, a second via hole is formed in the first DBR layer at the periphery of the first via hole, the second via hole penetrates the first DBR layer and exposes the second semiconductor layer; a first bottom anti-reflection layer, located on at least a part of the surface of the first DBR layer away from the epitaxial layer at the opening of the first via hole, the first bottom anti-reflection layer absorbs near-ultraviolet light and transmits visible light; a first metal reflection layer, located on at least one side of the first bottom anti-reflection layer away from the epitaxial layer at the opening of the first via hole, the first metal reflection layer also extends into the second via hole, and the first metal reflection layer is electrically connected with the second semiconductor layer.

[0051] The following refers to Figures 1-4 The light emitting diode provided by the present application is described in more detail.

[0052] The epitaxial layer comprises a first semiconductor layer 111, an active layer 112 and a second semiconductor layer 113 stacked in sequence, the first semiconductor layer 111 and the second semiconductor layer 113 are opposite in doping type, a first through hole 131 is formed in the epitaxial layer, the first through hole 131 penetrates the second semiconductor layer 113 and the active layer 112 and exposes the first semiconductor layer 111.

[0053] The active layer 112 is a light-emitting layer.

[0054] In an embodiment, the light-emitting wavelength range is 440nm-540nm.

[0055] The first through hole 131 can just penetrate the second semiconductor layer 113 and the active layer 112, and the first through hole 131 does not enter the first semiconductor layer 111; or the first through hole 131 penetrates the second semiconductor layer 113 and the active layer 112 and enters the first semiconductor layer 111.

[0056] In an embodiment, the thickness of the epitaxial layer is 5μm-10μm.

[0057] The epitaxial layer can be a single crystal structure or a polycrystalline structure.

[0058] In an embodiment, the epitaxial layer can be a periodic stacking structure composed of AlGaN layers with different Al components, and / or a periodic stacking structure composed of InGaN layers with different In components, and / or a periodic stacking structure composed of GaN layers with different Ga components. The epitaxial layer is preferably a periodic stacking structure composed of InGaN layers with different In components.

[0059] A plurality of first through holes 131 arranged in an array can be formed in the epitaxial layer; in an embodiment, the distance between the centers of adjacent first through holes 131 is 100μm-200μm.

[0060] The first DBR (Distributed Bragg Reflection) layer 121 is located on the inner wall of the first through hole 131 and extends to the surface of the second semiconductor layer 113 outside the first through hole 131.

[0061] The first DBR layer 121 can improve the reflection capability of the light-emitting diode.

[0062] In an embodiment, the first DBR layer 121 comprises a periodic alternately stacked first transparent dielectric layer (not shown) and a second transparent dielectric layer (not shown), the first transparent dielectric layer has a lower refractive index than the second transparent dielectric layer, the thickness of a single layer of the first transparent dielectric layer and a single layer of the second transparent dielectric layer are λ / (4*n1) and λ / (4*n2) respectively, where λ is the light emitting wavelength of the light emitting diode, n1 and n2 are the refractive indexes of the first transparent dielectric layer and the second transparent dielectric layer respectively corresponding to the light emitting wavelength.

[0063] The first transparent dielectric layer can be a SiO2layer, and the second transparent dielectric layer can be a TiO2layer, but not limited thereto.

[0064] The first bottom anti-reflection layer 122 is located at least on the surface of the first DBR layer 121 away from the epitaxial layer at the opening of the first via hole 131; the first bottom anti-reflection layer 122 absorbs near-ultraviolet light and transmits visible light.

[0065] In an embodiment, the first bottom anti-reflection layer 122 can be located only on the surface of the first DBR layer 121 away from the epitaxial layer at the opening of the first via hole 131, as shown in Figure 3 and Figure 4 In another embodiment, the first bottom anti-reflection layer 122 is not only located on the surface of the first DBR layer 121 away from the epitaxial layer at the opening of the first via hole 131, but also extends to the surface of the first DBR layer 121 in the first via hole 131, and the first bottom anti-reflection layer 122 also extends to the surface of the first DBR layer 121 away from the first via hole 131, as shown in Figure 1 and Figure 2 .

[0066] The first bottom anti-reflection layer 122 can be an insulating dielectric layer, a metal layer or a transparent conductive layer. The insulating dielectric layer can be a SiON layer or a SiN x layer, but not limited thereto; the transparent conductive layer can be a ZnO layer and its doped compound layer (such as a GZO layer, i.e. a gallium zinc oxide layer) or an In2O3layer and its doped compound layer (such as an ITO layer, i.e. an indium tin oxide layer), but not limited thereto; the metal layer can be an ultra-thin Ni layer, a Ti layer or a Cr layer, but not limited thereto.

[0067] In an embodiment, the thickness of the first bottom anti-reflection layer 122 can range from 1 nm to 100 nm.

[0068]

[0069] The first metal reflection layer 123 is located at least on the side of the first bottom anti-reflection layer 122 away from the epitaxial layer at the opening of the first via hole 131.

[0070] The first metal reflection layer 123 can include a stacked Ag layer, a Pt layer and a Ti layer, or the first metal reflection layer 123 can include a stacked Ag layer, a TiW layer and a Ti layer, but is not limited thereto.

[0071] The first bottom anti-reflection layer 122 can be used as a bonding layer between the first metal reflection layer 123 and the first DBR layer 121.

[0072] The first DBR layer 121, the first bottom anti-reflection layer 122 and the first metal reflection layer 123 can collectively constitute a first ODR composite mirror (i.e. omnidirectional mirror).

[0073] The first DBR layer 121 surrounding the first via hole 131 has a second via hole 132 formed therein, the second via hole 132 penetrates the first DBR layer 121 and exposes the second semiconductor layer 113, the first metal reflection layer 123 also extends into the second via hole 132, and the first metal reflection layer 123 is electrically connected to the second semiconductor layer 113.

[0074] When the first bottom anti-reflection layer 122 also extends to the surface of the first DBR layer 121 away from the first via hole 131, the second via hole 132 also penetrates the first bottom anti-reflection layer 122.

[0075] As shown in Figure 1 and Figure 2 , the first metal reflection layer 123 is located on the inner wall of the second via hole 132; or, as shown in Figure 3 or Figure 4 , the first metal reflection layer 123 fills the second via hole 132.

[0076] Preferably, the first metal reflection layer 123 does not cover the edge of the first bottom anti-reflection layer 122 close to the center of the first via hole 131.

[0077] In an embodiment, the light emitting diode further comprises an ohmic contact layer 14 located between the second semiconductor layer 113 and the first DBR layer 121 surrounding the first via hole 131, the second via hole 132 exposes the ohmic contact layer 14, and the first metal reflection layer 123 is electrically connected to the ohmic contact layer 14.

[0078] Preferably, the ohmic contact layer 14 does not cover the edge of the second semiconductor layer 113 close to the first via hole 131, so as to prevent the ohmic contact layer 14 from being formed on the sidewall of the first via hole 131 during etching of the ohmic contact layer 14, which may cause the first semiconductor layer 111 to be in conduction with the second semiconductor layer 113, thereby preventing short circuit.

[0079] The ohmic contact layer 14 can be an ITO (indium tin oxide) layer, but is not limited thereto.

[0080] As shown in FIG. 1, the first DBR layer 121 has an opening 133 exposing the bottom wall of the first via hole 131, i.e., the opening 133 penetrates the first DBR layer 121 of the bottom wall of the first via hole 131. Figure 4 As shown in FIG. 1, when the first bottom anti-reflection layer 122 also extends to the surface of the first DBR layer 121 in the first via hole 131, the opening 133 also penetrates the first bottom anti-reflection layer 122 on the bottom wall of the first via hole 131. Figure 2

[0081] The light emitting diode further comprises:

[0082] A first current spreading layer 151 located on the side of the first metal reflection layer 123 away from the epitaxial layer;

[0083] A first isolation dielectric layer 161 located in the first via hole 131 and the opening 133 and extending to the side of the first current spreading layer 151 away from the epitaxial layer;

[0084] A second current spreading layer 152 located in the first isolation dielectric layer 161 in the first via hole 131 and the opening 133 and extending to the side of the first isolation dielectric layer 161 away from the epitaxial layer at the periphery of the first via hole 131.

[0085] The first current spreading layer 151 can be a stack of Cr layer, Al layer, Ti layer, Pt layer and Ti layer, or the first current spreading layer 151 can be a stack of Ti layer, Au layer, Pt layer and Ti layer, but is not limited thereto; the first isolation dielectric layer 161 can be a stack of SiO2 layer, SiON layer and SiO2 layer, but is not limited thereto; and the second current spreading layer 152 can be a stack of Ti layer, Pt layer and Ti layer, but is not limited thereto.

[0086] In an embodiment, the thickness of the first isolation dielectric layer 161 is 600 nm to 1000 nm.

[0087] ​The light emitting diode further comprises a substrate 10; the first semiconductor layer 111 is of N type, and the second semiconductor layer 113 is of P type, as shown in FIG. 1, the substrate 10 is located on the side of the first semiconductor layer 111 away from the second semiconductor layer 113, at this time, the light emitting diode is of flip chip structure; or the first semiconductor layer 111 is of N type, and the second semiconductor layer 113 is of P type, as shown in FIG. 2, the substrate 10 is located on the side of the second current spreading layer 152 away from the epitaxial layer, at this time, the light emitting diode is of vertical structure. Figure 1 Figure 3

[0088] When the light emitting diode is of flip chip structure, the substrate 10 is a transparent substrate, and the material of the substrate 10 can be at least one of sapphire, aluminum nitride, gallium nitride, gallium oxide, zinc oxide, silicon carbide, magnesium aluminate, lithium gallate and lithium aluminate with micron / nanometer patterned features, but is not limited thereto; the substrate 10 is preferably a mirror sapphire substrate.

[0089] When the light emitting diode is of vertical structure, the substrate 10 can be a transparent or non-transparent substrate, and the material of the substrate 10 can be at least one of semiconductor materials such as silicon, germanium, aluminum nitride and silicon carbide, but is not limited thereto; the substrate 10 is preferably a silicon substrate.

[0090] It should be noted that in other embodiments, the first semiconductor layer 111 can be of P type, and the second semiconductor layer 113 can be of N type.

[0091] In an embodiment, the thickness of the substrate 10 is 50 μm to 150 μm.

[0092] The light emitting diode further comprises a first electrode 171 and a second electrode 172.

[0093] Preferably, the light emitting diode further comprises a second DBR layer 21, a second bottom anti-reflection layer 22 and a second metal reflection layer 23.

[0094] When the light emitting diode is of flip chip structure, the light emitting diode further comprises a second isolation dielectric layer 162; when the light emitting diode is of vertical structure, the light emitting diode further comprises a bonding structure and a passivation layer 19.

[0095] ​​When the light emitting diode is a flip structure, the second current spreading layer 152 extends to the surface of the first isolation dielectric layer 161 away from the epitaxial layer at the periphery of the first via hole 131, the second isolation dielectric layer 162 is located between the second current spreading layer 152 and the surface of the first isolation dielectric layer 161 away from the epitaxial layer; the first electrode 171 penetrates the second isolation dielectric layer 162 and the first isolation dielectric layer 161 to connect with the first current spreading layer 151, and the first electrode 171 also extends to the surface of the second isolation dielectric layer 162 away from the epitaxial layer; the second electrode 172 penetrates the second isolation dielectric layer 162 to connect with the second current spreading layer 152, and the second electrode 172 also extends to the surface of the second isolation dielectric layer 162 away from the epitaxial layer.

[0096] In an embodiment, the thickness of the second isolation dielectric layer 162 is 600 nm to 1000 nm.

[0097] When the light emitting diode is a flip structure, the second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 are sequentially stacked from inside to outside on the sidewall of the light emitting diode.

[0098] When the light emitting diode is a vertical structure, the second current spreading layer 152 extends to the entire surface of the first isolation dielectric layer 161 away from the epitaxial layer at the periphery of the first via hole 131, and the bonding structure is located between the second current spreading layer 152 and the substrate 10. The bonding structure includes a first bonding layer 181 and a second bonding layer 182, and the second bonding layer 182 is closer to the substrate 10 than the first bonding layer 181.

[0099] When the light emitting diode is a vertical structure, the edge of the light emitting diode forms a step, the sidewall of the step includes at least the epitaxial layer, the first DBR layer 121 and the first metal reflection layer 123, and the bottom wall of the step includes at least the first current spreading layer 151 and the first isolation dielectric layer 161; the first electrode 171 is located on the bottom wall of the step, and the first electrode 171 extends from the surface of the first current spreading layer 151 to the surface of the first isolation dielectric layer 161; the second electrode 172 is located on the surface of the substrate 10 away from the epitaxial layer.

[0100] The passivation layer 19 is located on the surface of the first isolation dielectric layer 161 away from the second semiconductor layer 113 and outside the first electrode 171. The outside of the first electrode 171 is the side of the first electrode 171 away from the epitaxial layer.

[0101] When the light emitting diode is a vertical structure, the second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 are stacked in sequence from inside to outside on the sidewall of the step, and the first electrode 171 is located on the side of the second metal reflection layer 23 away from the second DBR layer 21.

[0102] When the light emitting diode is a vertical structure, preferably, one side of the first semiconductor layer 111 away from the second semiconductor layer 113 has a roughened surface to reduce total reflection of light and improve light extraction efficiency.

[0103] Preferably, the area of the second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 is 50% to 100% of the area of the light extraction optical window of the light emitting diode.

[0104] In an embodiment, the second DBR layer 21 comprises periodically and alternately stacked first transparent dielectric layers (not shown) and second transparent dielectric layers (not shown), the refractive index of the first transparent dielectric layers is lower than that of the second transparent dielectric layers, and the thickness of a single first transparent dielectric layer and a single second transparent dielectric layer is λ / (4*n1) and λ / (4*n2) respectively, where λ is the light emitting wavelength of the light emitting diode, and n1 and n2 are the refractive indexes of the first transparent dielectric layers and the second transparent dielectric layers respectively corresponding to the light emitting wavelength.

[0105] The first transparent dielectric layer can be a SiO2 layer, and the second transparent dielectric layer can be a TiO2 layer, but is not limited thereto.

[0106] In an embodiment, the second bottom anti-reflection layer 22 can be an insulating dielectric layer, a metal layer or a transparent conductive layer. The insulating dielectric layer can be a SiON layer or a SiN layer, but is not limited thereto; the transparent conductive layer can be a ZnO layer and a doped compound layer thereof (such as a GZO layer, i.e. a gallium zinc oxide layer) or an In2O3 layer and a doped compound layer thereof (such as an ITO layer, i.e. an indium tin oxide layer), but is not limited thereto; and the metal layer can be an ultra-thin Ni layer, a Ti layer or a Cr layer, but is not limited thereto. x

[0107] The second bottom anti-reflection layer 22 can be used as a bonding layer between the second metal reflection layer 23 and the second DBR layer 21.

[0108] The second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 can collectively constitute a second ODR composite mirror (i.e. an omnidirectional mirror).

[0109] ​When the light emitting diode is a flip chip structure, the first ODR compound mirror is formed on the side of the active layer 112 away from the substrate 10, so that the light emitted by the active layer 112 cannot be emitted from the front side of the light emitting diode (i.e. the side on which the first electrode 171 and the second electrode 172 are formed); and the second ODR compound mirror is formed on the sidewall of the light emitting diode, so that the light emitted by the active layer 112 cannot be emitted from the sidewall of the light emitting diode; thus, the light emitted by the active layer 112 can only be emitted from the back side of the light emitting diode (i.e. the side of the substrate 10 away from the epitaxial layer), so the back side of the light emitting diode is the light emitting optical window of the light emitting diode.

[0110] When the light emitting diode is a vertical structure, the first ODR compound mirror is formed on the side of the active layer 112 close to the substrate 10, so that the light emitted by the active layer 112 cannot be emitted from the back side of the light emitting diode (i.e. the side on which the second electrode 172 is formed) or the sidewall of the structure between the bottom wall of the step and the second electrode 172; and the second ODR compound mirror is formed on the sidewall of the step, so that the light emitted by the active layer 112 cannot be emitted from the sidewall of the step; thus, the light emitted by the active layer 112 can only be emitted from the front side of the light emitting diode (i.e. the side of the passivation layer 19 on the surface of the first semiconductor layer 111 away from the epitaxial layer), so the front side of the light emitting diode is the light emitting optical window of the light emitting diode.

[0111] Therefore, by providing the first ODR compound mirror and the second ODR compound mirror, the light emitting angle is more concentrated, and the light emitting direction has high orientation.

[0112] When a flip chip structure light emitting diode is made, as shown in Figure 1 and Figure 2 the steps of making the light emitting diode include:

[0113] First, a substrate 10 is provided, and a first semiconductor layer 111, an active layer 112 and a second semiconductor layer 113 are sequentially stacked on the substrate 10. The forming process can be a MOCVD (Metal-organic Chemical Vapor Deposition) process, a molecular beam epitaxy process, an HVPE (Hydride Vapor Phase Epitaxy) process or laser sputtering, etc.

[0114] Then, a photoetching and etching process is performed to form a first via hole 131 penetrating through the second semiconductor layer 113 and the active layer 112 and exposing the first semiconductor layer 111;

[0115] Then, an ohmic contact material layer is formed on the surface of the second semiconductor layer 113 and the inner wall of the first via hole 131 by a rapid plasma deposition process, and an annealing process is performed. Then, a photoetching and etching process is performed on the ohmic contact material layer to remove the ohmic contact material layer on the inner wall of the first via hole 131, the ohmic contact material layer on the surface of the second semiconductor layer 113 near the first via hole 131, and the ohmic contact material layer on the edge of the second semiconductor layer 113, and the remaining ohmic contact material layer serves as an ohmic contact layer 14;

[0116] Then, a first DBR layer 121 is deposited on the inner wall of the first via hole 131, and the first DBR layer 121 extends to the surface of the second semiconductor layer 113 at the periphery of the first via hole 131, and the first DBR layer 121 covers the ohmic contact layer 14;

[0117] Then, a first bottom anti-reflective layer 122 is deposited on the entire surface of the first DBR layer 121;

[0118] Then, a photoetching and etching process is performed to form an opening 133 penetrating through the first bottom anti-reflective layer 122 and the first DBR layer 121 on the bottom wall of the first via hole 131, and to form a second via hole 132 penetrating through the first bottom anti-reflective layer 122 and the first DBR layer 121 on the ohmic contact layer 14;

[0119] Then, a photoetching, deposition, and stripping process is performed to form a first metal reflective layer 123 on the side of the first bottom anti-reflective layer 122 at the opening of the first via hole 131 away from the epitaxial layer, and the first metal reflective layer 123 also extends into the second via hole 132;

[0120] Then, a photoetching, deposition, and stripping process is performed to form a first current spreading layer 151 on the side of the first metal reflective layer 123 away from the epitaxial layer, and the first current spreading layer 151 can also extend to the surface of the first bottom anti-reflective layer 122 away from the epitaxial layer;

[0121] Then, a first isolation medium layer 161 is formed in the first via hole 131 and the opening 133 by a plasma-enhanced chemical vapor deposition (PECVD) process, and the first isolation medium layer 161 also extends to the side of the first current spreading layer 151 away from the epitaxial layer;

[0122] Then, a photolithography and etching process is performed to form a third via (not shown) in the first isolation medium layer 161, the third via penetrating the first isolation medium layer 161 in the first via 131 and the opening 133 and exposing the first semiconductor layer 111; then, a photolithography, electron beam evaporation and stripping process is performed to form a second current spreading layer 152 in the third via, the second current spreading layer 152 also extending to the surface of the first isolation medium layer 161 away from the epitaxial layer outside the third via;

[0123] Then, a second isolation medium layer 162 is formed on the second current spreading layer 152 and the surface of the first isolation medium layer 161 away from the epitaxial layer by a plasma enhanced chemical vapor deposition (PECVD) process;

[0124] Then, a photolithography and etching process is performed to form a fourth via (not shown) penetrating the second isolation medium layer 162 and the first isolation medium layer 161 and exposing the first current spreading layer 151, and to form a fifth via (not shown) penetrating the second isolation medium layer 162 and exposing the second current spreading layer 152; then, a photolithography, physical vapor deposition and stripping process is performed to form a first electrode 171 in the fourth via and a second electrode 172 in the fifth via, the first electrode 171 and the second electrode 172 also extending to the surface of the second isolation medium layer 162 away from the epitaxial layer;

[0125] Then, the substrate 10 is thinned to a desired thickness, and a cutting process is performed to separate a plurality of flip-chip structure light emitting diodes;

[0126] Then, the surface of the substrate 10 away from the epitaxial layer is bonded to a temporary substrate (not shown) by an adhesive, and a second DBR layer 21, a second bottom anti-reflection layer 22 and a second metal reflection layer 23 are sequentially stacked on the sidewall of the light emitting diode;

[0127] Then, the light emitting diode is peeled off from the temporary substrate to expose the surface of the substrate 10 away from the epitaxial layer.

[0128] When a flip-chip structure light emitting diode is made, as shown in FIGS. 1A to 1C, the steps of making the light emitting diode include: Figure 3 and Figure 4 The steps of making the flip-chip structure light emitting diode include:

[0129] First, a substrate 24 is provided, and a first semiconductor layer 111, an active layer 112, and a second semiconductor layer 113 are sequentially stacked on the substrate 24. The forming process can be a MOCVD (Metal-organic Chemical Vapor Deposition) process, a molecular beam epitaxy process, an HVPE (Hydride Vapor Phase Epitaxy) process, or a laser sputtering process, etc.

[0130] Then, a photolithography and etching process is performed to form a first via hole 131 penetrating through the second semiconductor layer 113 and the active layer 112 and exposing the first semiconductor layer 111;

[0131] Then, an ohmic contact material layer is formed on the surface of the second semiconductor layer 113 and the inner wall of the first via hole 131 by a rapid plasma deposition process, and an annealing process is performed. Then, a photolithography and etching process is performed on the ohmic contact material layer to remove the ohmic contact material layer on the inner wall of the first via hole 131, the ohmic contact material layer on the surface of the second semiconductor layer 113 close to the first via hole 131, and the ohmic contact material layer on the edge of the second semiconductor layer 113, and the remaining ohmic contact material layer serves as an ohmic contact layer 14;

[0132] Then, a first DBR layer 121 is deposited on the inner wall of the first via hole 131, and the first DBR layer 121 extends to the surface of the second semiconductor layer 113 at the periphery of the first via hole 131, and the first DBR layer 121 covers the ohmic contact layer 14;

[0133] Then, a first bottom anti-reflective material layer is deposited on the entire surface of the first DBR layer 121. Then, a photolithography and etching process is performed to remove the first bottom anti-reflective material layer in the first via hole 131 and the first bottom anti-reflective material layer on part of the surface of the first DBR layer 121 at the periphery of the first via hole 131, and the first bottom anti-reflective material layer on the surface of the first DBR layer 121 away from the epitaxial layer at the opening of the first via hole 131 and the first bottom anti-reflective material layer on the edge of the first DBR layer 121 are retained as a first bottom anti-reflective layer 122;

[0134] Then, a photolithography and etching process is performed to form an opening 133 penetrating through the first DBR layer 121 on the bottom wall of the first via hole 131, and to form a second via hole 132 penetrating through the first DBR layer 121 on the ohmic contact layer 14;

[0135] Then, lithography, deposition and stripping processes are performed to form a first metal reflective layer 123 on the side of the first bottom anti-reflective layer 122 away from the epitaxial layer at the opening of the first via hole 131, the first metal reflective layer 123 also extends into the second via hole 132 and the partial surface of the first bottom anti-reflective layer 122 on the edge of the first DBR layer 121;

[0136] Then, lithography, deposition and stripping processes are performed to form a first current spreading layer 151 on the side of the first metal reflective layer 123 away from the epitaxial layer;

[0137] Then, a first isolation medium layer 161 is formed in the first via hole 131 and the opening 133 by using a plasma enhanced chemical vapor deposition (PECVD) process, and the first isolation medium layer 161 also extends to the side of the first current spreading layer 151 away from the epitaxial layer;

[0138] Then, a third via hole (not shown) is formed in the first isolation medium layer 161 by using lithography and etching processes, the third via hole penetrates through the first isolation medium layer 161 in the first via hole 131 and the opening 133 and exposes the first semiconductor layer 111; then, a second current spreading layer 152 is formed in the third via hole by using lithography, electron beam evaporation and stripping processes, the second current spreading layer 152 also extends to the entire surface of the first isolation medium layer 161 around the third via hole away from the epitaxial layer;

[0139] Then, a first bonding layer 181 is formed on the side of the second current spreading layer 152 away from the epitaxial layer;

[0140] Then, a substrate 10 is provided, and a second bonding layer 182 is formed on the surface of the substrate 10; the side of the first bonding layer 181 away from the epitaxial layer is bonded to the side of the second bonding layer 182 away from the substrate 10 by using a bonding process;

[0141] Then, the substrate 24 is removed by using chemical mechanical polishing and wet etching processes; then, the first semiconductor layer 111 is partially removed in thickness by using a dry etching process to reduce the influence of high defects on the surface of the first semiconductor layer 111 on light absorption and device electrical characteristics;

[0142] Then, lithography and etching processes are performed to remove the edges (located outside the light emitting area) of the epitaxial layer and other structures, so as to form a step at the edge of the light emitting diode;

[0143] Then, the side of the first semiconductor layer 111 away from the second semiconductor layer 113 is subjected to a roughening treatment; wherein the roughening treatment operation can be performed by using a KOH hot solution;

[0144] Then, a passivation material layer is formed on the side wall and bottom wall of the step and the surface of the first semiconductor layer 111 away from the second semiconductor layer 113 by a plasma enhanced chemical vapor deposition (PECVD) process. Then, a photolithography and etching process is performed to remove part of the passivation material layer, and only the passivation material layer on the surface of the first semiconductor layer 111 away from the second semiconductor layer 113 and the part of the surface of the first isolation medium layer 161 on the bottom wall of the step is reserved as a passivation layer 19. The passivation layer 19 on the surface of the first isolation medium layer 161 on the bottom wall of the step has a gap with the side wall of the step.

[0145] Then, a first electrode 171 is formed in the gap.

[0146] Then, a second DBR layer 21, a second bottom anti-reflection layer 22 and a second metal reflection layer 23 are sequentially stacked on the surface of the passivation layer 19, the side wall and bottom wall of the step, and the second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 on the surface of the passivation layer 19 and the surface of the first electrode 171 are removed, and the second DBR layer 21, the second bottom anti-reflection layer 22 and the second metal reflection layer 23 on the side wall of the step are reserved. The first electrode 171 is located on the side of the reserved second metal reflection layer 23 away from the second DBR layer 21.

[0147] Then, the substrate 10 is thinned to a desired thickness, and a second electrode 172 is formed on the surface of the substrate 10 away from the epitaxial layer.

[0148] Then, a cutting process is performed to separate a plurality of vertical structure light emitting diodes.

[0149] Due to the first DBR layer 121 has different reflectivity to different wavelengths of light at different angles, when the near ultraviolet light emitted by the light source of the photoetching machine is incident on the first DBR layer 121, the reflectivity of the first DBR layer 121 to the near ultraviolet light at different angles is different, which causes that in the process of forming the first metal reflection layer 123 on the first DBR layer 121, the accuracy of the photoetching line width and the stability of the photoetching process cannot be guaranteed when the photoetching process is performed. In the utility model, since at least one side of the first DBR layer 121 away from the epitaxial layer at the opening of the first through hole 131 is formed with the first bottom anti-reflection layer 122, and the first bottom anti-reflection layer 122 can absorb the near ultraviolet light, so that in the process of forming the first metal reflection layer 123 on the side of the first bottom anti-reflection layer 122 away from the epitaxial layer at the opening of the first through hole 131, when the photoetching process is performed, the near ultraviolet light emitted by the light source of the photoetching machine to the opening of the first through hole 131 is basically absorbed by the first bottom anti-reflection layer 122, which reduces the reflection of the first DBR layer 121 to the near ultraviolet light, and further reduces the influence on the photoetching process corresponding to the formation of the first metal reflection layer 123, so that the photoetching line width accuracy and the photoetching process stability can be improved.

[0150] And since the light emitting wavelength of the light emitting diode is mainly in the visible light band, the first bottom anti-reflection layer 122 can transmit visible light, so that the absorption of visible light can be reduced.

[0151] Since the first bottom anti-reflection layer 122 (such as SiN x layer or metal layer) of part of the material still has a certain absorption rate to visible light, when the first bottom anti-reflection layer 122 is only located on the side of the first DBR layer 121 away from the epitaxial layer at the opening of the first through hole 131, the absorption of visible light can be further reduced while ensuring the photoetching line width accuracy and the photoetching process stability.

[0152] When the first metal reflection layer 123 does not cover the edge of the first bottom anti-reflection layer 122 close to the center side of the first through hole 131, it can ensure that the photoetching position of the photoetching process corresponding to the formation of the first metal reflection layer 123 is formed with the first bottom anti-reflection layer 122, so that the influence of the first DBR layer 121 on the photoetching process corresponding to the formation of the first metal reflection layer 123 can be further ensured.

[0153] From the above, the utility model discloses the light emitting diode includes: epitaxial layer, including the first semiconductor layer, active layer and second semiconductor layer who stack in proper order, the first semiconductor layer with the second semiconductor layer's doping type is opposite, the first through -hole is formed in the epitaxial layer, the first through -hole exposes the first semiconductor layer and passes through the second semiconductor layer and active layer, first DBR layer, is located the inner wall of the first through -hole and extends to the second semiconductor layer surface of the first through -hole periphery, the first DBR layer in the first through -hole periphery forms the second through -hole, the second through -hole exposes the second semiconductor layer and passes through the first DBR layer, first bottom anti -reflective layer, at least the first DBR layer of the first through -hole opening portion surface away from the epitaxial layer, the first bottom anti -reflective layer absorbs near ultraviolet light and transmits visible light, first metal reflection layer, at least the first bottom anti -reflective layer of the first through -hole opening portion one side away from the epitaxial layer, the first metal reflection layer also extends to the second through -hole, the first metal reflection layer with the second semiconductor layer electric connection. The utility model makes light emitting diode have high reflection ability, can also improve the photoetching line width precision and photoetching process stability.

[0154] The above description is only the description of the preferred embodiment of the utility model, and does not limit the scope of the utility model, and any change and modification of the ordinary skill in the art according to the above disclosure are within the protection scope of the claims.

Claims

1. A light-emitting diode, characterized in that, include: An epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The first semiconductor layer and the second semiconductor layer have opposite doping types. A first via is formed in the epitaxial layer. The first via penetrates the second semiconductor layer and the active layer and exposes the first semiconductor layer. A first DBR layer is located on the inner wall of the first via and extends to the surface of the second semiconductor layer surrounding the first via. A second via is formed in the first DBR layer surrounding the first via, and the second via penetrates the first DBR layer and exposes the second semiconductor layer. A first bottom anti-reflective layer, at least located on the portion of the surface of the first DBR layer away from the epitaxial layer at the opening of the first via, wherein the first bottom anti-reflective layer absorbs near-ultraviolet light and transmits visible light; A first metal reflective layer, at least located on the side of the first bottom anti-reflective layer away from the epitaxial layer at the opening of the first via, the first metal reflective layer also extending into the second via, and the first metal reflective layer being electrically connected to the second semiconductor layer.

2. The light-emitting diode as described in claim 1, characterized in that, The first bottom anti-reflective layer extends to the surface of the first DBR layer in the first through hole, and the first bottom anti-reflective layer also extends to the surface of the first DBR layer away from the first through hole, and the second through hole also penetrates the first bottom anti-reflective layer.

3. The light-emitting diode as described in claim 1 or 2, characterized in that, The first metal reflective layer is located on the inner wall of the second through hole, or the first metal reflective layer fills the second through hole.

4. The light-emitting diode as described in claim 1, characterized in that, The first metal reflective layer does not cover the edge of the first bottom anti-reflective layer near the center of the first through-hole.

5. The light-emitting diode as described in claim 1, characterized in that, The light-emitting diode also includes: An ohmic contact layer is located between the second semiconductor layer and the first DBR layer around the first via. The second via exposes the ohmic contact layer, and the first metal reflective layer is electrically connected to the ohmic contact layer.

6. The light-emitting diode as described in claim 5, characterized in that, The ohmic contact layer does not cover the edge of the second semiconductor layer near the first via.

7. The light-emitting diode as described in claim 1, characterized in that, The first DBR layer has an opening exposing the bottom wall of the first via, and the light-emitting diode further includes: The first current spreading layer is located on the side of the first metal reflective layer away from the epitaxial layer; A first isolation dielectric layer is located in the first via and the opening, and extends to the side of the first current spreading layer away from the epitaxial layer; The second current extension layer is located within the first isolation dielectric layer in the first via and the opening, and extends to the side of the first isolation dielectric layer surrounding the first via that is away from the epitaxial layer.

8. The light-emitting diode as described in claim 7, characterized in that, The light-emitting diode further includes a substrate; when the first semiconductor layer is N-type doped and the second semiconductor layer is P-type doped, the substrate is located on the side of the first semiconductor layer away from the second semiconductor layer.

9. The light-emitting diode as described in claim 8, characterized in that, The second current spreading layer extends to a portion of the surface of the first isolation dielectric layer surrounding the first via, away from the epitaxial layer, and the light-emitting diode further includes: The second isolation dielectric layer is located on the side of the second current spreading layer and the first isolation dielectric layer away from the epitaxial layer; A first electrode extends through the second isolation dielectric layer and the first isolation dielectric layer to be connected to the first current spreading layer, and the first electrode also extends to a portion of the surface of the second isolation dielectric layer away from the epitaxial layer; The second electrode extends through the second isolation dielectric layer to connect with the second current spreading layer, and the second electrode also extends to a portion of the surface of the second isolation dielectric layer away from the epitaxial layer.

10. The light-emitting diode as described in claim 8, characterized in that, The light-emitting diode also includes: The second DBR layer, the second bottom anti-reflective layer, and the second metal reflective layer are stacked sequentially from the inside to the outside on the sidewall of the light-emitting diode.

11. The light-emitting diode as claimed in claim 7, characterized in that, The light-emitting diode further includes a substrate; when the first semiconductor layer is doped with N-type and the second semiconductor layer is doped with P-type, the substrate is located on the side of the second current spreading layer away from the epitaxial layer.

12. The light-emitting diode as claimed in claim 11, characterized in that, The second current spreading layer extends to the entire surface of the first isolation dielectric layer surrounding the first via, away from the epitaxial layer, and the light-emitting diode further includes: A bonding structure is located between the second current spreading layer and the substrate.

13. The light-emitting diode as described in claim 11, characterized in that, The edge of the light-emitting diode is formed with a step, the sidewall of the step includes at least the epitaxial layer, the first DBR layer and the first metal reflective layer, and the bottom wall of the step includes at least the first current spreading layer and the first isolation dielectric layer. The light-emitting diode also includes: The first electrode is located on the bottom wall of the step and extends from the surface of the first current spreading layer to the surface of the first insulating dielectric layer. The second electrode is located on the side of the substrate away from the epitaxial layer.

14. The light-emitting diode as described in claim 13, characterized in that, The light-emitting diode also includes: A passivation layer is located on the side of the first semiconductor layer away from the second semiconductor layer and on the surface of the first isolation dielectric layer outside the first electrode.

15. The light-emitting diode as described in claim 13, characterized in that, The light-emitting diode also includes: The second DBR layer, the second bottom anti-reflective layer, and the second metal reflective layer are stacked sequentially from the inside to the outside on the sidewall of the step, and the first electrode is located on the side of the second metal reflective layer away from the second DBR layer.

16. The light-emitting diode as claimed in claim 11, characterized in that, The side of the first semiconductor layer away from the second semiconductor layer has a roughened surface.

17. The light-emitting diode as described in claim 10 or 15, characterized in that, The area of ​​the second DBR layer, the second bottom anti-reflective layer, and the second metal reflective layer is 50% to 100% of the area of ​​the light-emitting optical window of the light-emitting diode.

18. The light-emitting diode as described in claim 10 or 15, characterized in that, Both the first DBR layer and the second DBR layer include a first transparent dielectric layer and a second transparent dielectric layer that are periodically stacked alternately. The refractive index of the first transparent dielectric layer is lower than that of the second transparent dielectric layer. The thicknesses of a single first transparent dielectric layer and a single second transparent dielectric layer are λ / (4*n1) and λ / (4*n2), respectively, where λ is the emission wavelength of the light-emitting diode, and n1 and n2 are the refractive indices of the first transparent dielectric layer and the second transparent dielectric layer corresponding to the emission wavelength, respectively.

19. The light-emitting diode as described in claim 10 or 15, characterized in that, The first bottom anti-reflective layer and the second bottom anti-reflective layer are insulating dielectric layers, metal layers or transparent conductive layers.

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