Semiconductor photonic device

Abstract

The utility model provides a semiconductor photonic device, which can comprise a photonic integrated circuit and can be coupled with an output optical fiber at the top surface of the semiconductor photonic device. To facilitate coupling a modulated optical signal to an output fiber of a top surface of a semiconductor photonic device, the semiconductor photonic device may include a mirror structure supported by a semiconductor support structure included in the semiconductor photonic device. The mirror structure may be positioned at an angle relative to a surface of a semiconductor substrate of the semiconductor photonic device, which enables the mirror structure to transmit a modulated optical signal propagating in a first direction to a second direction towards the output fiber. According to the utility model, the output optical fiber can be coupled to the side surface of the semiconductor photonic device, and the propagation distance of modulated optical signals in the semiconductor photonic device can be reduced by coupling the output optical fiber to the top surface of the semiconductor photonic device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to a semiconductor photonic device. BACKGROUND

[0002] Semiconductor devices can be configured to use optical signals for high-speed and secure data transmission. The optical signals can be transmitted through waveguides in the semiconductor devices. The waveguides are capable of confining the optical signals, which can reduce optical loss and improve the propagation efficiency of the optical signals. By modulating light into optical pulses through an optical modulator, data can be encoded into the optical signals. The optical pulses are then transmitted to the waveguides to propagate to other areas of the semiconductor devices. SUMMARY

[0003] Embodiments of the present utility model provide a semiconductor photonic device, comprising: a semiconductor substrate; a dielectric region located above the semiconductor substrate; an optical modulator located in the dielectric region; one or more waveguides located in the dielectric region, wherein the one or more waveguides are optically coupled with the optical modulator; a mirror structure located in the dielectric region, configured to receive a modulated optical signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated optical signal from a first direction substantially parallel to a top surface of the semiconductor substrate to a second direction substantially perpendicular to the first direction; and a grating coupler configured to direct an input optical signal from the second direction to the first direction.

[0004] Embodiments of the present utility model provide a semiconductor photonic device, comprising: a semiconductor substrate; a dielectric region located above the semiconductor substrate; an optical modulator located in the dielectric region; one or more waveguides located in the dielectric region, wherein the one or more waveguides are optically coupled with the optical modulator; a semiconductor support structure located on the semiconductor substrate and in the dielectric region; a mirror structure located above the semiconductor support structure in the dielectric region, configured to receive a modulated optical signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated optical signal from a first direction substantially parallel to a top surface of the semiconductor substrate to a second direction substantially perpendicular to the first direction; and a grating coupler configured to direct an input optical signal from the second direction to the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0005] The nature of the utility model content will be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale according to the standard convention in the industry. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clear discussion.

[0006] Figure 1is a diagram of an example environment in which systems and / or methods described herein can be implemented.

[0007] Figure 2 is a diagram of an example semiconductor photonic device described herein.

[0008] Figure 3A and Figure 3B is a diagram of an example implementation of a mirror structure described herein.

[0009] Figures 4A-4Q is a diagram of an example implementation of forming a semiconductor photonic device described herein.

[0010] Figure 5 is a diagram of example components of a device described herein.

[0011] Figure 6 is a flow diagram of an example process associated with forming a semiconductor photonic device described herein. DETAILED DESCRIPTION

[0012] The following detailed description is provided to provide a more complete understanding of the various embodiments described herein. The detailed description includes specific details to assist in that understanding but these are intended to be illustrative only and not limiting of the various embodiments described herein. For example, one or more embodiments described herein can be implemented in different embodiments and environments. The present inventive concept provides many different embodiments or instances, only a few of which are described herein. The specific details of the one or more embodiments of the present inventive concept described herein are provided for the purpose of illustration. Therefore, the inventive concept is not intended to be limited to the specific embodiments described herein, but the scope of the inventive concept is to be determined solely by the appended claims and their equivalents. The various embodiments described herein can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the present inventive concept, or any combination of these, e.g., data server and client computer implement a portion of the present inventive concept. The front end component can be delivered to a user on a transitory signal or a non-transitory computer readable storage medium, e.g., via the Internet or through a commercial distribution medium. The various embodiments described herein can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the present inventive concept, or any combination of these, e.g., data server and client computer implement a portion of the present inventive concept. The front end component can be delivered to a user on a transitory signal or a non-transitory computer readable storage medium, e.g., via the Internet or through a commercial distribution medium.

[0013] In addition, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] A light modulator of a photonic integrated circuit can be configured to receive an input optical signal and an input electrical signal, and can be configured to encode data from the input electrical signal onto the input optical signal by modulating the input optical signal to produce a modulated optical signal. A waveguide of the photonic integrated circuit can be configured to receive the modulated optical signal and provide the modulated optical signal to an output optical fiber on which the modulated optical signal is transmitted to another device. In this way, the photonic integrated circuit can facilitate high-speed and / or high-bandwidth optical communication for applications such as telecommunications, data centers, and / or high-performance computing (HPC), among others.

[0015] In some embodiments described herein, a semiconductor photonic device can include a photonic integrated circuit and can be coupled with an output optical fiber at a top surface of the semiconductor photonic device. To facilitate coupling of a modulated optical signal to the output optical fiber at the top surface of the semiconductor photonic device, the semiconductor photonic device can include a mirror structure supported by a semiconductor support structure included in the semiconductor photonic device. The mirror structure can be positioned at an angle relative to a surface of a semiconductor substrate of the semiconductor photonic device, which enables the mirror structure to transmit the modulated optical signal propagating in a first direction to a second direction toward the output optical fiber.

[0016] In contrast to coupling the output optical fiber to a side surface of the semiconductor photonic device, coupling the output optical fiber to the top surface of the semiconductor photonic device enables wafer-level testing of the semiconductor photonic device. In other words, the semiconductor photonic device can be operated and tested as part of a semiconductor wafer before the semiconductor wafer is diced into individual semiconductor photonic devices. This enables enhanced checking and verification of the performance of the semiconductor photonic device, and can enable an increase in yield of the semiconductor photonic devices on the semiconductor wafer. Moreover, in contrast to coupling the output optical fiber to a side surface of the semiconductor photonic device, the propagation distance of the modulated optical signal in the semiconductor photonic device can be reduced by coupling the output optical fiber to the top surface of the semiconductor photonic device. As a result, coupling the output optical fiber to the top surface of the semiconductor photonic device can reduce optical loss in the semiconductor photonic device and / or can increase operational efficiency of the semiconductor photonic device, among others.

[0017] Figure 1 is a diagram of an example environment 100 in which systems and / or methods described herein can be implemented. As shown, environment 100 includes a semiconductor photonic device 102, an output optical fiber 104, and a semiconductor support structure 106. Figure 1As shown, the example environment 100 can include a plurality of semiconductor process tools 102-114 and wafer / die transport tools 116. The plurality of semiconductor process tools 102-114 can include a deposition tool 102, an exposure tool 104, a development tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor process tool. The tools included in the example environment 100 can be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor process facility, and / or a manufacturing facility, among other examples.

[0018] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin-on tool capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool such as a sputtering tool or another type of PVD tool. In some embodiments, the example environment 100 includes a plurality of different types of deposition tools 102. As used herein, a “deposition tool 102” can refer to one or more deposition tools 102, one or more deposition tools 102 of the same type. Among other examples, and / or one or more deposition tools 102 of different types.

[0019] The exposure tool 104 is a semiconductor process tool capable of exposing a photoresist layer to a radiation source such as an ultraviolet (UV) source (e.g., a deep UV (EUV) source, an extreme UV (EUV) source, and a UV source, and / or the like), an X-ray source, an e-beam source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various portions of a semiconductor device, and / or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0020] The developing tool 106 is a semiconductor process tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some implementations, the developing tool 106 develops the photoresist layer. The pattern is formed by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0021] The etching tool 108 is a semiconductor process tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber that is filled with an etchant and places the substrate in the chamber for a particular period of time to remove a particular amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which can involve using an ionized gas to isotropically or directionally etch the one or more portions.

[0022] The planarization tool 110 is a semiconductor processing tool that is capable of polishing or planarizing layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes layers or surfaces of deposited or plated materials. The planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize surfaces of a semiconductor device. The planarization tool 110 can use an abrasive and corrosive chemical slurry in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can be rotated at different axes of rotation to remove material and level any irregular topography of the semiconductor device, thereby planarizing or flattening the semiconductor device.

[0023] The plating tool 112 is a semiconductor processing tool that is capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the plating tool 112 can include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin silver, tin lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0024] The ion implantation tool 114 is a semiconductor process tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material, such as a gas or a solid, in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage discharges between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward a substrate such that the ions are implanted below a surface of the substrate.

[0025] The wafer / die transport tool 116 can be included in a cluster tool or another type of tool including multiple processing chambers, and can be configured to transport substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as a device front end module (EFEM), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transport tool 116 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or deposits), a deposition processing chamber (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations), and / or the like.

[0026] In some implementations, one or more of the semiconductor process tools 102-114 can perform one or more of the semiconductor process operations described herein. For example, one or more of the semiconductor processing tools 102-114 can form a light modulator and a first waveguide of a semiconductor photonic device in a semiconductor layer over a first portion of a dielectric region; can form a second waveguide of the semiconductor photonic device over the first waveguide in a second portion of the dielectric region; can form a recess in the dielectric region adjacent to the second waveguide, where a portion of a semiconductor substrate below the dielectric region is exposed by the recess; can form a semiconductor support structure on the portion of the semiconductor substrate in the recess; can form a mirror structure over a beveled sidewall of the semiconductor support structure; and / or can fill the recess above the semiconductor support structure and above the mirror structure with a dielectric material, among other examples. One or more of the semiconductor process tools 102-114 can perform other semiconductor process operations described herein, such as forming a semiconductor photonic device including a light modulator and a first waveguide of the semiconductor photonic device in a semiconductor layer over a first portion of a dielectric region, forming a second waveguide of the semiconductor photonic device over the first waveguide in a second portion of the dielectric region, forming a recess in the dielectric region adjacent to the second waveguide, where a portion of a semiconductor substrate below the dielectric region is exposed by the recess, forming a semiconductor support structure on the portion of the semiconductor substrate in the recess, forming a mirror structure over a beveled sidewall of the semiconductor support structure, and / or filling the recess above the semiconductor support structure and above the mirror structure with a dielectric material, among other examples. Figures 4A-4Q and / or Figure 6 and / or

[0027] Figure 1 The number and arrangement of devices shown is provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown in other examples. Figure 1additional apparatuses, fewer apparatuses, different apparatuses, or differently arranged apparatuses than those depicted in FIG. 1. Furthermore, Figure 1 Two or more of the apparatuses depicted in FIG. 1 can be in a single apparatus, or a single apparatus within Figure 1 The apparatuses depicted in FIG. 1 can be implemented as a plurality of dispersed apparatuses. Additionally or alternatively, a group of apparatuses (e.g., one or more apparatuses) of the example environment 100 can perform one or more functions described as being performed by another group of apparatuses of the example environment 100.

[0028] Figure 2 is a diagram of an example semiconductor photonic apparatus 200 described herein. The semiconductor photonic apparatus 200 can include a photonic integrated circuit (PIC) configured to transmit and / or receive modulated optical signals (e.g., optical signals modulated to encode data in the optical signals). Generally, the semiconductor photonic apparatus 200 can be configured to convert between electrical signals and optical signals for high bandwidth optical communications.

[0029] Figure 2 A cross-sectional view of the semiconductor photonic apparatus 200 is shown. As Figure 2 shown, the semiconductor photonic apparatus 200 can include a semiconductor substrate 202, an apparatus region 204 above the semiconductor substrate 202, and an interconnect region 206 above the apparatus region 204. The semiconductor substrate 202 can include a silicon (Si) substrate and / or another type of semiconductor substrate. The apparatus region 204 can include a dielectric region 208. The dielectric region 208 can include one or more layers of dielectric material. The dielectric material can include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, and / or another dielectric material.

[0030] The device region 204 can also include a grating coupler 210 in a dielectric region 208. The grating coupler 210 can include a semiconductor structure (e.g., a silicon (Si) structure and / or another type of semiconductor structure) configured to receive an input optical signal 212 from an input optical fiber 214 that extends through one or more dielectric layers 216 in the interconnect region 206 of the semiconductor photonic device 200. The grating coupler 210 can direct the input optical signal 212 to an optical modulator 220 contained in the dielectric region 208 of the device region 204 in the semiconductor photonic device 200. The grating coupler 210 can be configured to diffract the input optical signal 212 from an off-plane direction (e.g., a z-direction) in the semiconductor photonic device 200 to an in-plane direction (e.g., an x-direction) that lies in the plane of the optical modulator 220. The grating coupler 210 can include a plurality of periodic gratings. The periodicity of the periodic gratings can be selected to implement diffraction of one or more wavelengths of the input optical signal 212. In some implementations, the periodicity of the periodic gratings can be selected based on the wavelengths of the input optical signal 212.

[0031] The one or more dielectric layers 216 of the interconnect region 206 can include one or more layers of a dielectric material. The dielectric material can include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, and / or another dielectric material. The passivation layer 218 can be included on and / or over the one or more dielectric layers 216, and the passivation layer 218 can include one or more dielectric materials, one or more polymeric materials, and / or one or more other types of materials.

[0032] The optical modulator 220 can include a micro-ring modulator (MRM), a Mach Zender modulator (MZM), and / or another type of optical modulator configured to modulate the input optical signal 212 based on an input electrical signal 222 to produce a modulated optical signal 224. The input electrical signal 222 can be or can correspond to a digital data stream (e.g., 1 values and 0 values). The optical modulator 220 can modulate an amplitude of the input optical signal 212, a phase of the input optical signal 212, a frequency of the input optical signal 212, and / or another property of the input optical signal 212 based on the digital data stream of the input electrical signal 222.

[0033] The input electrical signal 222 can be provided to the contact 226 and / or the contact 228 of the optical modulator 220. The contact 226 and / or the contact 228 can include one or more types of doped semiconductor material. For example, the contact 226 can be a p-doped contact (e.g., can include a semiconductor material doped with one or more p-type dopants), and the contact 228 can be an n-doped contact (e.g., can include a semiconductor material doped with one or more n-type dopants). Thus, the optical modulator 220 can include a PN junction. The semiconductor material can include silicon (Si), germanium (Ge), silicon germanium (SiGe), and / or another semiconductor material. The p-type dopants can include p-type ions of a p-type material (e.g., boron (B) or germanium (Ge), among others). The n-type dopants can include n-type ions of an n-type material (e.g., phosphorus (P) or arsenic (As), among others).

[0034] When the input electrical signal 222 is applied to the PN junction of the optical modulator 220, the junction depletion width of the PN junction is modified. This causes a change in the electron and hole concentrations within the optical modulator 220. The change in the electron and hole concentrations can cause a change in the effective refractive index of the optical modulator 220, which can modulate the light intensity of the input optical signal 212 within the optical modulator 220, thereby enabling the input electrical signal 222 to be converted into the modulated optical signal 224.

[0035] The capping layer 230 can be included on and / or over the contact 226 and the contact 228. The capping layer 230 can include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0036] The device region 204 can include a plurality of interconnect structures (interconnect structure 232 and interconnect structure 234) that are included in the dielectric region 208 and coupled with the optical modulator 220. For example, the interconnect structure 232 can be electrically and / or physically coupled with the contact 226. The interconnect structure 234 can be electrically and / or physically coupled with the contact 228. The interconnect structures 232 and 234 can each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other examples of conductive materials. The interconnect structures 232 and 234 can each include a via, a trench, a contact plug, and / or another type of conductive structure.

[0037] Interconnect structures 232 and 234 can be electrically and / or physically coupled with one or more metallization layers 236 in one or more dielectric layers 216 of interconnect region 206 of semiconductor photonic device 200. Input electrical signals 222 can be provided through metallization layers 236 and through interconnect structures 232 and 234 to optical modulator 220. Metallization layers 236 correspond to electrical circuitry capable of providing signals and / or power to and / or from optical modulator 220 and / or other devices in device region 204. Metallization layers 236 can each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), or other examples of electrically conductive materials. Metallization layers 236 can each include vias, trenches, contact plugs, electrically conductive pads, electrically conductive pillars, and / or another type of metallization layer.

[0038] Optical modulator 220 can be configured to provide modulated optical signals 224 to a semiconductor waveguide 238 contained in dielectric region 208 of device region 204. Semiconductor waveguide 238 can include a silicon (Si) waveguide and / or another type of semiconductor waveguide. Semiconductor waveguide 238 can be configured to receive modulated optical signals 224 and transmit modulated optical signals 224 to a dielectric waveguide 240 located above semiconductor waveguide 238 in dielectric region 208 of device region 204. Semiconductor waveguide 238 can be fabricated from the same semiconductor layer as optical modulator 220 and / or grating coupler 210, as described. Figures 4A-4Q

[0039] Dielectric waveguide 240 can include a slab waveguide that includes a plurality of dielectric layers. Dielectric waveguide 240 can include a high-k core layer sandwiched between low-k cladding layers. This enables modulated optical signals 224 to be loosely confined within the high-k core layer and achieve total internal reflection of modulated optical signals 224 in the high-k dielectric core layer, which can enable low optical loss and / or increased speed of propagation of the signal relative to semiconductor waveguide 238. Low-k dielectric cladding layers can each include a low-k dielectric material, such as silicon oxide (SiO x， ​For example, SiO2, which has a dielectric constant ranging from about 3.9 to about 4.2. The high-k dielectric core layer may include a high-k dielectric material having a dielectric constant greater than 4.2 and ranging from about 7 to about 1500. However, other values ​​of the dielectric constant range for the low-k dielectric overlay and the high-k dielectric core layer are within the scope of this disclosure. Exemplary high-k dielectric materials that can be used for the high-k dielectric core layer include strontium titanate (SrTiOx, such as SrTiO3) and barium titanate (BaTiO2). x For example, BaTiO3), barium strontium titanate (BaSrTiO3), etc. x For example, BaSrTiO3), lead zirconate titanate (PbZrTiO3), etc. x For example, PbZrTiO3), silicon nitride (Si3N4, for example, Si x N y Titanium dioxide (TiO2) x For example, TiO2), zirconium oxide (ZrO2) x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), hafnium oxide (HfO) x For example, HfO2), hafnium silicate (HfSiO2), etc. x For example, HfSiO4), zirconium titanate (ZrTiO4) x For example, ZrTiO4), tantalum oxide (Ta x O y For example, Ta₂O₅) and / or yttrium oxide (Y) x O y Examples include Y2O3.

[0040] The dielectric waveguide 240 can guide the modulated optical signal 224 to a mirror structure 242 included in a dielectric region 208 of a device region 204 above a semiconductor substrate 202. The mirror structure 242 can be configured to redirect the modulated optical signal 224 from an x-direction (e.g., a first direction generally parallel to the semiconductor substrate 202) in the semiconductor photonic device 200 to a z-direction (e.g., a second direction generally perpendicular to the first direction) in the semiconductor photonic device. This allows the mirror structure to guide the modulated optical signal 224 to an output fiber 244, which is coupled to the semiconductor photonic device 200 at the top (e.g., opposite to the side of the semiconductor photonic device 200).

[0041] The mirror structure 242 is configured to direct the modulated light signal 224 toward a top surface of the semiconductor photonic device 200 (rather than a side surface of the semiconductor photonic device 200) so that the semiconductor photonic device 200 can be subjected to wafer-level testing before being singulated or diced from a semiconductor wafer on which the semiconductor photonic device 200 is fabricated. The side surface of the semiconductor photonic device 200 is contiguous with other semiconductor dies on the semiconductor wafer before the semiconductor photonic device 200 is singulated or diced from the semiconductor wafer. Thus, the output of the photonic integrated circuit from the semiconductor photonic device 200 (e.g., including the light modulator 220 and the waveguides 238 and 240) cannot be obtained through the side surface of the semiconductor photonic device 200 before the semiconductor photonic device 200 is singulated or diced from the semiconductor wafer. The mirror structure 242 is configured to direct the modulated light signal 224 toward the top surface of the semiconductor photonic device 200 so that the semiconductor photonic device 200 can be subjected to wafer-level testing through the top surface of the semiconductor photonic device 200 before the semiconductor photonic device 200 is singulated or diced from the semiconductor wafer. For example, the semiconductor photonic device 200 can be subjected to wafer-level testing to verify the operation of the light modulator 220 and / or the waveguides 238 and 240. Example include verifying the light intensity of the modulated light signal 224 produced by the light modulator 220, verifying the operating frequency of the modulated light signal 224 produced by the light modulator 220, and / or verifying the error rate of data encoded in the modulated light signal 224 produced by the light modulator 220, etc.

[0042] Additionally and / or alternatively, the propagation distance of the modulated light signal 224 from the dielectric waveguide 240 to the top surface of the semiconductor photonic device 200 can be less than the propagation distance of the modulated light signal 224 from the dielectric waveguide 240 to the side surface. Thus, the mirror structure 242 being configured to direct the modulated light signal 224 toward the top surface of the semiconductor photonic device 200 can reduce optical loss of the modulated light signal 224 in the semiconductor photonic device 200 (which can reduce the operating power consumption of the semiconductor photonic device 200) and / or can enable the semiconductor photonic device 200 to operate at a higher data rate, etc.

[0043] The mirror structure 242 can be included above and can be supported by a semiconductor support structure 246. The semiconductor support structure 246 can be included on and can extend above the semiconductor substrate 202. In some implementations, the semiconductor support structure 246 semiconductor substrate 202 can include the same semiconductor material, e.g., silicon (Si). In some embodiments, the semiconductor support structure 246 and the semiconductor substrate 202 can include different semiconductor materials.

[0044] The semiconductor support structure 246 can include a beveled sidewall 248 that is angled with respect to the top surface 250 of the semiconductor substrate 202. The mirror structure 242 can be positioned above the beveled sidewall 248 of the semiconductor support structure 246, which enables the mirror structure 242 to be angled positioned (e.g., with respect to the top surface 250 and with respect to the direction of propagation of the modulated light signal 224) that enables the mirror structure 242 to redirect the modulated light signal 224 so that it does not propagate in the x-direction in the semiconductor photonic device 200, but instead propagates in the z-direction in the semiconductor photonic device 200 toward the top surface of the semiconductor photonic device 200 where the output fiber 244 is located.

[0045] The dimension Dl of the semiconductor support structure 246 can correspond to the angle of the beveled sidewall 248 with respect to the top surface 250 of the semiconductor substrate 202. The dimension D2 of the mirror structure 242 can correspond to the angle of the mirror structure 242 with respect to the top surface 250 of the semiconductor substrate 202. In some embodiments, the dimension Dl and the dimension D2 are approximately the same (e.g., within 5% different, within 1% different). In other words, the angle of the mirror structure 242 can correspond to the angle of the beveled sidewall 248 of the semiconductor support structure 246. In some embodiments, the dimension Dl and the dimension D2 are included in a range of about 40 degrees to about 50 degrees. If the dimension Dl and the dimension D2 are less than about 40 degrees or greater than about 50 degrees, the propagation distance of the modulated light signal 224 can increase because the modulated light signal 224 will propagate at an angle rather than directly in the z-direction toward the top surface of the semiconductor photonic device 200. This can introduce additional optical loss for the modulated light signal 224. However, other values for the dimension Dl and the dimension D2 and ranges other than about 40 degrees to about 50 degrees are within the scope of the present disclosure.

[0046] Further as Figure 2As shown, the length of the mirror structure 242 can be selected such that the mirror structure 242 completely covers the thickness of the dielectric waveguide 240. In other words, the length of the mirror structure 242 can be selected such that the top surface (or topmost point) of the mirror structure 242 is located at a higher z-direction position in the semiconductor photonic device 200 than the top surface 252 of the dielectric waveguide 240 and such that the bottom surface (or bottommost point) is located at a lower z-direction position in the semiconductor photonic device 200 than the bottom surface 254 of the dielectric waveguide 240. If the mirror structure 242 does not completely extend between the top surface 252 of the dielectric waveguide 240 and the bottom surface 254 of the dielectric waveguide 240, the modulated light signal 224 can experience optical loss, and thus, the semiconductor photonic device 200 can experience reduced operational efficiency. The mirror structure 242 completely extending between the top surface 252 of the dielectric waveguide 240 and the bottom surface 254 of the dielectric waveguide 240 can increase the likelihood that the mirror structure 242 completely captures the modulated light signal 224 received from the dielectric waveguide 240, thereby minimizing optical loss of the modulated light signal 224.

[0047] In this way, the semiconductor photonic device 200 can include a semiconductor substrate 202, a dielectric region 208 above the semiconductor substrate 202, and an optical modulator 220 in the dielectric region 208. The semiconductor photonic device 200 can include a semiconductor waveguide 238 adjacent to the optical modulator 220, a dielectric waveguide 240 above and optically coupled to the semiconductor waveguide 238, and a mirror structure 242 adjacent to and optically coupled to the dielectric waveguide 240. The mirror structure 242 can be supported on a semiconductor support structure 246 that extends above a top surface 250 of the semiconductor substrate 202. The mirror structure 242 can be configured to receive a modulated light signal 224 from the dielectric waveguide 240 and direct the modulated light signal 224 toward an output fiber 244 that is coupled to the semiconductor photonic device 200 at a top of the semiconductor photonic device 200.

[0048] As described above, there is provided Figure 2 by way of example. Other examples can differ Figure 2 from the described examples.

[0049] Figure 3A and Figure 3B are diagrams of example implementations of the mirror structure 242 described herein. Figure 3AAn example implementation 300 is shown in which the mirror structure 242 includes a single layer structure. In the example implementation 300, the mirror structure 242 can include a high-reflectivity material, such as aluminum copper (AlCu) and / or tungsten (W), among others. In some embodiments, a dimension D3 corresponding to a thickness of the mirror structure 242 can be included in a range from about 5 Angstroms to about 1 micron. If the dimension D3 is less than about 5 Angstroms, the mirror structure 242 can not provide sufficient reflectivity, which can result in increased optical loss of the modulated light signal 224. If the dimension D3 is greater than about 1 micron, the mirror structure 242 can increase surface roughness, which can also increase optical loss of the modulated light signal 224. If the dimension D3 is included in a range from about 5 Angstroms to about 1 micron, the mirror structure 242 can implement high reflectivity and low surface roughness, resulting in reduced or minimized optical loss of the modulated light signal 224. However, other values of the dimension D3 and ranges other than about 5 Angstroms to about 1 micron are within the scope of the present disclosure.

[0050] Figure 3B An example implementation 302 is shown in which the mirror structure 242 includes a multi-layer structure. For example, the mirror structure 242 can include a plurality of first layers 304 arranged vertically in an alternating fashion with a plurality of second layers 306. In other words, the first layers 304 alternate with the second layers 306 in a direction that is approximately perpendicular to a direction in which the mirror structure 242 extends. In some implementations, one or more properties of the plurality of first layers 304 and / or one or more properties of the plurality of second layers 306 can be selected to optimize reflectivity of the mirror structure 242 for the modulated light signal 224. For example, a refractive index of the first layers 304 and / or a refractive index of the second layers 306 can be different and can be selected to optimize reflectivity of the mirror structure 242 for the modulated light signal 224. In other words, each first layer 304 can have a first refractive index, each second layer 306 can have a second refractive index, and the first refractive index and the second refractive index can be different refractive indices and can be selected to optimize reflectivity of the mirror structure 242 for the modulated light signal 224.

[0051] As another example, a thickness of the first layers 304 and / or a thickness of the second layers 306 can be different and can be selected to optimize reflectivity of the mirror structure 242 for the modulated light signal 224. In other words, each first layer 304 can have a first thickness (e.g., an individual thickness of each first layer 304), each second layer 306 can have a second thickness (e.g., an individual thickness of each second layer 306), and the first thickness and the second thickness can be different thicknesses and can be selected to optimize reflectivity of the mirror structure 242 for the modulated light signal 224.

[0052] As another example, the first layers 304 can each include a first material, and the second layers 306 can each include a second material, where the first and second materials are selected to optimize the reflectivity of the mirror structure 242 for the modulated light signal 224. As an example, the first material can include silicon (Si) and the second material can include molybdenum (Mo).

[0053] As described above, Figure 3A and Figure 3B are provided by way of example. Other examples can differ from those described with respect to Figure 3A and Figure 3B described with respect to

[0054] Figures 4A-4Q is a diagram of an example implementation 400 of the semiconductor photonic device 200 described herein. In some embodiments, one or more of the semiconductor process operations described in connection with the example implementation 400 can be performed using one or more of the semiconductor process tools 102-114 and / or by the wafer / die transport tool 116. In some embodiments, one or more of the semiconductor process operations described in connection with the example implementation 400 can be performed using another semiconductor process tool.

[0055] As shown in Figure 4A , a substrate 402 can be provided. The substrate 402 can include a silicon-on-insulator (SOI) substrate (or SOI wafer) that includes a semiconductor substrate 202 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a portion of a dielectric region 208 (e.g., a buried oxide or bottom oxide (BOX) layer and / or another type of insulator layer) on and / or over the semiconductor substrate 202, and a semiconductor layer 404 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) on and / or over the portion of the dielectric region 208.

[0056] Alternatively, the semiconductor substrate 202 can be provided as a semiconductor wafer, and the deposition tool 102 can be used to form the portion of the dielectric region 208 on and / or over the semiconductor substrate 202, and the semiconductor layer 404 can be formed on and / or over the portion of the dielectric region 208. The deposition tool 102 can be used to form the portion of the dielectric region 208 using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. The deposition tool 102 can be used to form the semiconductor layer 404 using a CVD technique, a PVD technique, an epitaxy technique, and / or another type of deposition technique.

[0057] As shown in Figures 4B-4F , a device region 204 of the semiconductor device 200 is formed. As shown in Figure 4BAs shown, grating coupler 210, optical modulator 220, and semiconductor waveguide 238 can be formed on semiconductor layer 404. In some embodiments, a pattern in the hard mask layer is used to etch semiconductor layer 404 to form grating coupler 210, optical modulator 220, and / or semiconductor waveguide 238. For example, a hard mask layer can be formed on semiconductor layer 404 using deposition tool 102 (e.g., using CVD, PVD, and / or another type of deposition technique), and can be used to form a photoresist layer on the hard mask layer (e.g., using spin coating and / or another type of deposition technique). Exposure tool 104 can be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch the hard mask layer to transfer the pattern from the photoresist layer to the hard mask layer.

[0058] Etching tool 108 can be used to etch semiconductor layer 404 based on a pattern in the hard mask layer to remove portions of semiconductor layer 404 to form grating coupler 210, optical modulator 220, and / or semiconductor waveguide 238. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using chemical stripping agents, plasma ashing, and / or another technique). In some embodiments, planarization tool 110 is used to remove the remaining portion of the hard mask layer using CMP technology and / or another type of planarization technique.

[0059] like Figure 4C As shown, additional material can be deposited for dielectric region 208 to encapsulate grating coupler 210, optical modulator 220, and semiconductor waveguide 238 within dielectric region 208. Deposition tool 102 can be used to deposit dielectric region 208. CVD, PVD, oxidation (e.g., thermal oxidation), and / or another type of deposition technique are used to form the additional material for dielectric region 208. In some embodiments, planarization tool 110 is used to planarize dielectric region 208 after depositing additional material.

[0060] like Figure 4CAs further shown, one or more portions of the optical modulator 220 may be doped with one or more types of dopants to form one or more doped regions in the optical modulator 220, including contacts 226 and 228. For example, an ion implantation tool 114 may be used to p-type ion implantate a portion of the semiconductor material of the optical modulator 220 to form contact 226. As another example, the ion implantation tool 114 may be used to n-type ion implantate another portion of the semiconductor material of the optical modulator 220 to form contact 228. P-type ions and / or n-type ions may be implanted using ion implantation technology and / or another type of doping technology.

[0061] like Figure 4C As further shown, the capping layer 230 may be formed on and / or over the top surfaces of contacts 226 and 228. The deposition tool 102 may be used to deposit the capping layer 230 using CVD, PVD, ALD, oxidation, and / or another deposition technique. In some embodiments, the planarization tool 110 is used to planarize the capping layer 230 such that the top surface of the dielectric region 208 and the top surface of the capping layer 230 are coplanar.

[0062] like Figure 4D As shown, additional material for dielectric region 208 can be formed on and / or over grating coupler 210, optical modulator 220, and / or semiconductor waveguide 238. Deposition tool 102 can be used to deposit dielectric region 208. CVD, PVD, oxidation (e.g., thermal oxidation), and / or another type of deposition technique are used to form the additional material for dielectric region 208. In some embodiments, planarization tool 110 is used to planarize dielectric region 208 after depositing additional material.

[0063] like Figure 4D As further shown, a dielectric waveguide 240 can be formed in a dielectric region 208 above the semiconductor waveguide 238. The dielectric waveguide 240 can be formed in a groove in the dielectric region 208.

[0064] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric region 208 to form grooves in the dielectric region 208. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric region 208. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch the dielectric region 208 based on the pattern to form grooves in the dielectric region 208. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other etching operations. Type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the dielectric region 208.

[0065] The deposition tool 102 can be used to deposit dielectric waveguide 240 in a groove in dielectric region 208 using CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique. In some embodiments, a planarization tool 110 is used to planarize dielectric waveguide 240 after deposition.

[0066] like Figure 4E As shown, additional material for dielectric region 208 can be formed on and / or over grating coupler 210, optical modulator 220, semiconductor waveguide 238, and / or dielectric waveguide 240. Deposition tool 102 can use CVD, PVD, oxidation (e.g., thermal oxidation), and / or another type of deposition technique to deposit the additional material for dielectric region 208. In some embodiments, planarization tool 110 is used to planarize dielectric region 208 after depositing the additional material.

[0067] like Figure 4F As further shown, interconnect structures 232 and 234 can be formed on the dielectric region 208 above the optical modulator 220. Interconnect structure 232 can be formed on and / or above the contact 226, such that interconnect structure 232 is electrically coupled and / or physically coupled to contact 226. Interconnect structure 234 can be formed on and / or above the contact 228, such that interconnect structure 234 is electrically coupled and / or physically coupled to contact 228. Interconnect structures 232 and 234 can be formed in a groove in the dielectric region 208.

[0068] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric region 208 and the cap layer 230 to form a recess in the dielectric region 208. In these implementations, the deposition tool 102 can be used to form a photoresist layer on the dielectric region 208. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etch tool 108 can be used to etch the dielectric region 208 and the cap layer 230 based on the pattern to form a recess in the dielectric region 208. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch the dielectric region 208 based on the pattern.

[0069] The deposition tool 102 and / or the plating tool 112 can be used to deposit the interconnect structures 232 and 234 in the recess using a CVD technique, a PVD technique, an ALD technique, a plating technique, and / or another suitable deposition technique in combination with the Figure 1 In some embodiments, a seed layer is first deposited, and the interconnect structure 232 and / or the interconnect structure 234 is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the interconnect structure 232 and / or the interconnect structure 234 after the interconnect structure 232 and / or the interconnect structure 234 is deposited.

[0070] The interconnect structure 232 can be deposited such that the interconnect structure 232 lands on the contact 226. The interconnect structure 234 can be deposited such that the interconnect structure 234 lands on the contact 228. In some implementations, a silicide layer is formed on the contact 226, and the interconnect structure 232 is formed on the silicide layer. In some embodiments, a silicide layer is formed on the contact 228, and the interconnect structure 234 is formed on the silicide layer.

[0071] As Figure 4GAs shown, an interconnect region 206 can be formed over the device region 204. The interconnect region 206 can be formed in a series of operations in which one or more dielectric layers 216 are formed, and one or more metallization layers 236 are formed in the one or more dielectric layers 216. For example, a first dielectric layer of the dielectric layers 216 can be deposited, patterned, and etched. A first metallization layer of the metallization layers 236 can then be deposited in the first dielectric layer. A second dielectric layer in the dielectric layers 216 over the first dielectric layer can be deposited, patterned, and etched. A second metallization layer of the metallization layers 236 can then be deposited in the second dielectric layer. Additional dielectric layers 216 and additional metallization layers 236 can be formed in the interconnect region 206 in a similar manner. A passivation layer 218 can be formed over a topmost dielectric layer of the dielectric layers 216.

[0072] The deposition tool 102 can be used to deposit the dielectric layers 216 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations thereof, and / or another suitable deposition technique. Figure 1 Another type of deposition technique described and / or another suitable deposition technique can be used to deposit the dielectric layers 216. In some embodiments, the planarization tool 110 can be used to planarize the dielectric layers 216 after the dielectric layers 216 are deposited.

[0073] The deposition tool 102 and / or the plating tool 112 can be used to deposit the metallization layers 236 using CVD techniques, PVD techniques, ALD techniques, plating techniques, combinations thereof, and / or another suitable deposition technique. Figure 1 Another type of deposition technique described and / or another suitable deposition technique can be used to deposit the metallization layers 236. In some embodiments, a seed layer is first deposited, and the metallization layers 236 are deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the metallization layers 236 after the metallization layers 236 are deposited.

[0074] The deposition tool 102 can be used to deposit the passivation layer 218 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations thereof, and / or another suitable deposition technique. Figure 1 Another type of deposition technique described and / or another suitable deposition technique can be used to deposit the passivation layer 218. In some embodiments, the planarization tool 110 can be used to planarize the passivation layer 218 after the passivation layer 218 is deposited.

[0075] As shown in FIG. 4A, a via 406 can be formed through the passivation layer 218, through one or more dielectric layers 216 of the interconnect region 206, and through the dielectric region 208 of the device region 204. The via 406 can be formed adjacent to the dielectric waveguide 240. Portions of the semiconductor substrate 202 can be exposed by the via 406. Figure 4H Figure 4I As shown in FIG. 4A, a via 406 can be formed through the passivation layer 218, through one or more dielectric layers 216 of the interconnect region 206, and through the dielectric region 208 of the device region 204. The via 406 can be formed adjacent to the dielectric waveguide 240. Portions of the semiconductor substrate 202 can be exposed by the via 406.

[0076] ​In some embodiments, the pattern in the photoresist layer is used to etch the passivation layer 218, the one or more dielectric layers 216, the dielectric region 208 to form the recess 406. In these implementations, the deposition tool 102 can be used to form the photoresist layer on the passivation layer 218. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etch tool 108 can be used to etch the passivation layer 218, the one or more dielectric layers 216, the dielectric region 208 based on the pattern to form the recess 406 in the passivation layer 218, the one or more dielectric layers 216, the dielectric region 208. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch the passivation layer 218, the one or more dielectric layers 216, the dielectric region 208 based on the pattern.

[0077] As shown in FIG. 4A, the semiconductor support structure 246 can be formed in the recess 406. The semiconductor support structure 246 can be formed on portions of the semiconductor substrate 202 that are exposed by the recess 406. Thus, the semiconductor support structure 246 can extend above the semiconductor substrate 202. Figure 4J

[0078] The deposition tool 102 can be used to epitaxially grow the semiconductor support structure 246 on the semiconductor substrate 202 in the recess 406. Epitaxially growing the semiconductor support structure 246 enables the semiconductor support structure 246 to be formed such that the semiconductor support structure 246 has a particular die orientation. Specifically, epitaxially growing the semiconductor support structure 246 enables the semiconductor support structure 246 to be formed such that the semiconductor support structure 246 has a (011) die orientation. As shown in FIG. 4B, epitaxially growing the semiconductor support structure 246 enables the semiconductor support structure 246 to have the (011) die orientation facilitates the formation of the beveled sidewalls 248 of the semiconductor support structure 246. Thus, the semiconductor support structure 246 is formed to have a trapezoidal cross-sectional profile (e.g., in the x-z plane) as a result of the epitaxial growth of the (011) die of the semiconductor support structure 246. In this manner, the epitaxial growth of the (011) die of the semiconductor support structure 246 enables the beveled sidewalls 248 of the semiconductor support structure 246 to be formed to include an angle (dimension Dl) that is in a range from about 40 degrees to about 50 degrees. Figure 4J

[0079] As shown in FIG. 4B, the semiconductor support structure 246 can be formed in the recess 406. The semiconductor support structure 246 can be formed on portions of the semiconductor substrate 202 that are exposed by the recess 406. Thus, the semiconductor support structure 246 can extend above the semiconductor substrate 202. Figure 4K ​​As shown, an oxide barrier layer 408 can be formed in the groove 406. The oxide barrier layer 408 can be conformally deposited on the semiconductor support structure 246, such that the oxide barrier layer 408 conforms to the contour and / or shape of the semiconductor support structure 246. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding... Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the oxide barrier layer 408. In some embodiments, the oxide barrier layer 408 comprises an oxide-containing dielectric material, such as silicon oxide (SiO2). x Or silicon oxynitride (SiON), etc. Additionally and / or alternatively, the oxide barrier layer 408 may include a nitride-containing dielectric material, such as silicon nitride (SiON). x N y )wait.

[0080] like Figure 4L As shown, a mirror layer 410 can be formed in the recess 406. The mirror layer 410 can be conformally deposited on the oxide barrier layer 408 above the semiconductor support structure 246, such that the mirror layer 410 conforms to the contour and / or the contour of the semiconductor support structure 246. The mirror layer 410 can also be formed on the sidewall of the recess 406.

[0081] The mirror layer 410 may include one or more highly reflective materials, such as aluminum copper (AlCu) and / or tungsten (W). In some embodiments, the mirror layer 410 comprises a single layer of highly reflective material. In some implementations, the mirror layer 410 includes a plurality of first layers 304 arranged perpendicularly to a plurality of second layers 306 in an alternating manner. The first layers 304 may include a first material (e.g., silicon (Si)) and the second layers 306 may include a second material (e.g., molybdenum (Mo)).

[0082] Deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, epitaxial technology, and bonding technology. Figure 1 Another deposition operation and / or other suitable deposition operation are described to deposit the mirror layer 410.

[0083] like Figure 4MAs shown, the mirror structure 242 can be formed over the oxide barrier layer 408 on the beveled sidewall 248 of the semiconductor support structure 246. Therefore, the oxide barrier layer 408 can be included between the mirror structure 242 and the support structure 246, such that the mirror structure 242 is spaced apart from the semiconductor support structure 246 by the oxide barrier layer 408. The mirror structure 242 can be formed over the oxide barrier layer 408 on the beveled sidewall 248 facing the dielectric waveguide 240. The mirror structure 242 can be formed of one or more conductive materials. The oxide barrier layer 408 can be included over the semiconductor support structure 246 to electrically isolate the mirror structure 242 and the semiconductor support structure 246, thereby preventing the mirror structure 242 from generating an electric field in the semiconductor support structure 246 (or reducing its likelihood), which could otherwise lead to current leakage through the semiconductor support structure 246.

[0084] Mirror structure 242 can be formed by removing a portion of mirror layer 410, wherein the remaining portion of mirror layer 410 corresponds to mirror structure 242. In some embodiments, a pattern in the photoresist layer is used to etch mirror layer 410 to form mirror structure 242. In these embodiments, deposition tool 102 can be used to form photoresist layer on mirror layer 410. Exposure tool 104 can be used to expose photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 can be used to develop and remove a portion of photoresist layer to expose the pattern. Etching tool 108 can be used to etch mirror layer 410 based on the pattern to form mirror structure 242 from mirror layer 410. In some embodiments, etching operations include plasma etching operations, wet chemical etching operations, and / or another type of etching operation. In some embodiments, photoresist removal tool can be used to remove the remaining portion of photoresist layer (e.g., using chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of mirror layer 410.

[0085] like Figure 4N and Figure 4O As shown, the groove 406 can be filled with dielectric material over the semiconductor support structure 246 and the mirror structure 242. The dielectric material may correspond to additional portions of the dielectric region 208 of the device region 204 and / or additional portions of one or more dielectric layers 216 of the interconnect region 206. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, Figure 1 Another type of deposition technique and / or another suitable deposition technique is used to deposit the dielectric material. In some embodiments, the planarization tool 110 can be used to planarize the dielectric material after deposition.

[0086] like Figure 4PAs shown, recesses 412 and 414 may be formed in and / or through one or more dielectric layers 216 of the interconnect region 206 of the semiconductor photonic device 200. Recess 412 may be formed over the grating coupler 210, and recess 414 may be formed over the mirror structure 242. In some embodiments, recesses 412 and 414 are formed completely through one or more dielectric layers 216, such that the dielectric region 208 is exposed through recesses 412 and 414. In some embodiments, one or more dielectric layers 216 remain in recesses 412 and / or recess 414.

[0087] In some embodiments, the pattern in the photoresist layer is used to etch one or more dielectric layers 216 to form recesses 412 and 414. In these embodiments, a deposition tool 102 can be used to form the photoresist layer on the passivation layer 218. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the passivation layer 218 and one or more dielectric layers 216 based on the pattern to form recesses 412 and 414 in the interconnect region 206. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the passivation layer 218 and one or more dielectric layers 216.

[0088] like Figure 4Q As shown, the input optical fiber 214 can be inserted into the recess 412, such that the input optical fiber 214 is coupled to the top surface of the semiconductor photonic device 200. The input optical fiber 214 extends into the interconnect region 206 of the semiconductor photonic device 200 and is located above the grating coupler 210. This allows the input optical signal 212 to be provided from the input optical fiber 214 to the grating coupler 210. In some embodiments, the input optical fiber 214 is fixed in the recess 412 with an adhesive such as epoxy resin.

[0089] like Figure 4QAs further shown, the output fiber 244 can be inserted into the recess 414, such that the output fiber 244 is coupled to the top surface of the semiconductor photonic device 200. The output fiber 244 extends to the interconnect region 206 of the semiconductor photonic device 200 and is located above the mirror structure 242. This allows the modulated optical signal 224 to be redirected from the dielectric waveguide 240 to the output fiber 244 through the mirror structure 242. In some embodiments, the output fiber 244 is fixed in the recess 414 with an adhesive such as epoxy resin.

[0090] As mentioned above, Figures 4A-4Q Provided as an example. Other examples may be provided in relation to... Figures 4A-4Q The descriptions are different.

[0091] Figure 5 This is a diagram of exemplary components of the apparatus 500 described herein. In some embodiments, one or more of the semiconductor process tools 102 to 114 and / or the wafer / die transfer tool 116 may include one or more apparatuses 500 and / or one or more components of apparatus 500. Figure 5 As shown, the device 500 may include a bus 510, a processor 520, a memory 530, an input component 540, an output component 550, and / or a communication component 560.

[0092] Bus 510 may include one or more components for wired and / or wireless communication between components of implementing device 500. Bus 510 can... Figure 5 Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 510 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 520 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing unit. Processor 520 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 520 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0093] The memory 530 can include volatile and / or nonvolatile memory. For example, the memory 530 can include random access memory (RAM), read-only memory (ROM), hard disk, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 530 can include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 530 can be a non-transitory computer-readable medium. The memory 530 can store information, one or more instructions, and / or software (e.g., one or more software applications) related to operation of the device 500. In some implementations, the memory 530 can include one or more memories coupled with one or more processors (e.g., the processor 520). The communicative coupling between the processor 520 and the memory 530 can enable the processor 520 to read and / or process information stored in the memory 530 and / or store information in the memory 530.

[0094] The input component 540 can enable the device 500 to receive input, such as user input and / or sensed input. For example, the input component 540 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 550 can enable the device 500 to provide output, such as via a display, a speaker, and / or a light-emitting diode. The communication component 560 can enable the device 500 to communicate with other devices via wired and / or wireless connections. For example, the communication component 560 can include a receiver, a transmitter, a transceiver, a data modem, a network interface card, and / or an antenna.

[0095] The device 500 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., the memory 530) can store a set of instructions (e.g., one or more instructions or program code) for execution by the processor 520. The processor 520 can perform the set of instructions to perform one or more operations or processes described herein. In some implementations, performance of the set of instructions by one or more processors 520 causes the one or more processors 520 and / or the device 500 to perform one or more operations or processes described herein. In some implementations, one or more operations or processes described herein can be performed using hardwired circuitry in place of, or in combination with, instructions. Additionally or alternatively, the processor 520 can be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

[0096] Figure 5 The number and arrangement of components shown in FIG. 5 are provided as an example. Substantial Figure 5 FIG. 5 shows an example of a device 500 that can include additional components not shown in FIG. 5 for the sake of brevity. Additionally or alternatively, some of the components shown in FIG. 5 can be integrated or distributed.

[0097] Figure 6 is a flow diagram of an example process 600 associated with forming a semiconductor photonic device described herein. In some implementations, one or more process blocks of Figure 6 FIG. 6 can be performed using one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102-114). Additionally or alternatively, Figure 6 one or more process blocks of FIG. 6 can be performed using one or more components of the device 500, such as the processor 520, the memory 530, the input component 540, the output component 550, and / or the communication component 560.

[0098] As shown in Figure 6 FIG. 6, the process 600 can include forming an optical modulator and a first waveguide of a semiconductor photonic device in a semiconductor layer over a first portion of a dielectric region (block 610). For example, one or more of the semiconductor processing tools 102-114 can be used to form an optical modulator 220 and a first waveguide (e.g., a semiconductor waveguide 238) of a semiconductor photonic device 200 in a semiconductor layer 404 over a first portion of a dielectric region 208. In some implementations, a grating coupler 210 is also formed in the semiconductor layer 404.

[0099] As shown in Figure 6Further shown, process 600 can include forming a second waveguide of the semiconductor photonic device in a second portion of the dielectric region over the first waveguide (block 620). For example, one or more of semiconductor processing tools 102-114 can be used to form a second waveguide (e.g., dielectric waveguide 240) of semiconductor photonic device 200 over the first waveguide in a second portion of dielectric region 208.

[0100] As Figure 6 Further shown, process 600 can include forming a recess in the dielectric region adjacent to the second waveguide (block 630). For example, one or more of semiconductor processing tools 102-114 can be used to form recess 406 in dielectric region 208 adjacent to the second waveguide. In some embodiments, a portion of semiconductor substrate 202 below dielectric region 208 is exposed by recess 406.

[0101] As Figure 6 Further shown, process 600 can include forming a semiconductor support structure on the portion of the semiconductor substrate in the recess (block 640). For example, one or more of semiconductor processing tools 102-114 can be used to form semiconductor support structure 246 on the portion of semiconductor substrate 202 in recess 406.

[0102] As Figure 6 Further shown, process 600 can include forming a mirror structure over the beveled sidewall of the semiconductor support structure (block 650). For example, one or more of semiconductor processing tools 102-114 can be used to form mirror structure 242 over beveled sidewall 248 of semiconductor support structure 246.

[0103] As Figure 6 Further shown, process 600 can include filling the recess above the semiconductor support structure and above the mirror structure with a dielectric material (block 660). For example, one or more of semiconductor processing tools 102-114 can be used to fill recess 406 above semiconductor support structure 246 and above mirror structure 242 with a dielectric material.

[0104] Process 600 can include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0105] In a first implementation, process 600 includes forming an oxide barrier layer 408 on beveled sidewall 248 of the semiconductor support structure.

[0106] In a second embodiment, alone or in combination with the first embodiment, forming the mirror structure 242 includes forming the mirror structure 242 on the oxide barrier layer 408 over the beveled sidewall 248 of the semiconductor support structure 246.

[0107] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the semiconductor support structure 246 includes epitaxially growing the semiconductor support structure 246 on a portion of the semiconductor substrate 202 exposed by the recess 406.

[0108] In a fourth embodiment, alone or in combination with one or more of the first through third embodiments, forming the semiconductor support structure 246 includes forming the semiconductor support structure 246 such that the semiconductor support structure 246 has a trapezoidal cross-sectional profile.

[0109] In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, forming the semiconductor support structure 246 includes forming the semiconductor support structure 246 such that the semiconductor support structure 246 has a (011) die orientation.

[0110] In a sixth embodiment, alone or in combination with one or more of the first through fifth embodiments, forming the semiconductor support structure 246 includes forming the semiconductor support structure 246 such that the angle of the beveled sidewall 248 relative to the top surface 250 of the semiconductor substrate 202 includes an angle (dimension Dl) in a range of about 40 degrees to about 50 degrees.

[0111] Although Figure 6 An exemplary block of the process 600 is shown, but in some embodiments, fewer blocks, different blocks, or differently arranged blocks can be used compared to Figure 6 As shown, the process 600 can include additional blocks, fewer blocks, different blocks, or differently arranged blocks. Additionally or alternatively, two or more blocks of the process 600 can be performed in parallel.

[0112] In this way, the semiconductor photonic device can include a photonic integrated circuit and can be coupled with an output fiber at a top surface of the semiconductor photonic device. To facilitate coupling of the modulated light signal to the output fiber at the top surface of the semiconductor photonic device, the semiconductor photonic device can include a mirror structure supported by a semiconductor support structure included in the semiconductor photonic device. The mirror structure can be positioned at an angle relative to a surface of a semiconductor substrate of the semiconductor photonic device that enables the mirror structure to transmit the modulated light signal propagating in a first direction to a second direction toward the output fiber. Coupling the output fiber to the top surface of the semiconductor photonic device, as opposed to a side surface of the semiconductor photonic device, enables wafer-level testing of the semiconductor photonic device. Further, coupling the output fiber to the top surface of the semiconductor photonic device can reduce a propagation distance of the modulated light signal in the semiconductor photonic device.

[0113] In some embodiments, a semiconductor photonic device includes a semiconductor substrate; a dielectric region above the semiconductor substrate; a light modulator in the dielectric region; one or more waveguides in the dielectric region, wherein the one or more waveguides are optically coupled with the light modulator; a mirror structure in the dielectric region configured to receive a modulated light signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated light signal from a first direction generally parallel to a top surface of the semiconductor substrate to a second direction generally perpendicular to the first direction; and a grating coupler configured to direct an input light signal from the second direction to the first direction.

[0114] In some embodiments, wherein the mirror structure is configured to direct the modulated light signal to an output fiber coupled with the semiconductor photonic device. In some embodiments, wherein the one or more waveguides include a semiconductor waveguide adjacent to the light modulator and a dielectric waveguide adjacent to the mirror structure. In some embodiments, wherein a top surface of the mirror structure is at a second direction position in the dielectric region higher than a top surface of the dielectric waveguide, and wherein a bottom surface of the mirror structure is at a second direction position in the dielectric region lower than a bottom surface of the dielectric waveguide. In some embodiments, wherein an angle of the mirror structure relative to the top surface of the semiconductor substrate is included in a range of about 40 degrees to about 50 degrees. In some embodiments, wherein the mirror structure includes an aluminum copper (AlCu) mirror structure. In some embodiments, wherein the mirror structure includes a plurality of first layers having a first refractive index and a plurality of second layers alternating with the plurality of first layers and having a second refractive index. In some embodiments, wherein a thickness of the mirror structure is in a range of about 5 angstroms to about 1 micrometer.

[0115] In some embodiments, a semiconductor photonic device, comprising: a semiconductor substrate; a dielectric region located above the semiconductor substrate; an optical modulator located in the dielectric region; one or more waveguides located in the dielectric region, wherein the one or more waveguides are optically coupled with the optical modulator; a semiconductor support structure located on the semiconductor substrate and located in the dielectric region; a mirror structure located above the semiconductor support structure in the dielectric region, configured to receive a modulated optical signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated optical signal from a first direction that is substantially parallel to a top surface of the semiconductor substrate, to a second direction that is substantially perpendicular to the first direction; and a grating coupler configured to direct an input optical signal from the second direction to the first direction.

[0116] In some embodiments, wherein the semiconductor support structure has a (011) die orientation. In some embodiments, wherein the mirror structure is located above the semiconductor support structure. In some embodiments, wherein the mirror structure is positioned at an angle relative to a top surface of the semiconductor substrate; and wherein the angle of the mirror structure corresponds to an angle of the beveled sidewall of the semiconductor support structure. In some embodiments, further comprising: an oxide barrier layer located between the semiconductor support structure and mirror structure.

[0117] In some embodiments, a method, comprising: forming an optical modulator and a first waveguide of a semiconductor photonic device in a semiconductor layer above a first portion of a dielectric region; forming a second waveguide of the semiconductor photonic device above the first waveguide in a second portion of the dielectric region; forming a recess in the dielectric region adjacent to the second waveguide, wherein a portion of a semiconductor substrate below the dielectric region is exposed through the recess; forming a semiconductor support structure on the portion of the semiconductor substrate located in the recess; forming a mirror structure above a beveled sidewall of the semiconductor support structure; and filling the recess above the semiconductor support structure and above the mirror structure with a dielectric material.

[0118] In some embodiments, further comprising forming an oxide barrier layer on the beveled sidewall of the semiconductor support structure. In some embodiments, wherein forming the mirror structure comprises forming the mirror structure on the oxide barrier layer over the beveled sidewall of the semiconductor support structure. In some embodiments, wherein forming the semiconductor support structure comprises epitaxially growing the semiconductor support structure on a portion of the semiconductor substrate exposed by the recess. In some embodiments, wherein forming the semiconductor support structure comprises forming the semiconductor support structure such that the semiconductor support structure has a trapezoidal cross-sectional profile. In some embodiments, wherein forming the semiconductor support structure comprises forming the semiconductor support structure such that the semiconductor support structure has a (011) die orientation. In some embodiments, wherein forming the semiconductor support structure comprises forming the semiconductor support structure such that an angle of the beveled sidewall relative to a top surface of the semiconductor substrate is in a range from about 40 degrees to about 50 degrees.

[0119] As used herein, a value that "meets a threshold" can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, or equal to the threshold, depending on the context.

[0120] The foregoing outlines features of several embodiments so that a thorough comprehension of the present disclosure can be attained. Those of ordinary skill in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor photonic device, characterized by, Comprising: a semiconductor substrate; a dielectric region over the semiconductor substrate; a light modulator in the dielectric region; one or more waveguides in the dielectric region, wherein the one or more waveguides are optically coupled with the light modulator; a mirror structure in the dielectric region configured to receive a modulated light signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated light signal from a first direction generally parallel to a top surface of the semiconductor substrate to a second direction generally perpendicular to the first direction; and a grating coupler configured to direct an input light signal from the second direction to the first direction.

2. The semiconductor photonic device of claim 1, wherein The mirror structure is configured to direct the modulated light signal to an output optical fiber coupled with the semiconductor photonic device.

3. The semiconductor photonic device of claim 1, wherein The one or more waveguides comprise: a semiconductor waveguide adjacent to the light modulator; and a dielectric waveguide adjacent to the mirror structure.

4. The semiconductor photonic device of claim 3, wherein A top surface of the mirror structure is located at a second direction position in the dielectric region higher than a top surface of the dielectric waveguide, and wherein a bottom surface of the mirror structure is located at a second direction position in the dielectric region lower than a bottom surface of the dielectric waveguide.

5. The semiconductor photonic device of claim 1, wherein An angle of the mirror structure relative to a top surface of the semiconductor substrate is comprised in a range of about 40 degrees to about 50 degrees.

6. The semiconductor photonic device of claim 1, wherein, The mirror structure comprises: a plurality of first layers having a first refractive index; and a plurality of second layers alternating with the plurality of first layers and having a second refractive index.

7. A semiconductor photonic device, characterized in that, Comprising: a semiconductor substrate; a dielectric region over the semiconductor substrate; a light modulator in the dielectric region; one or more waveguides in the dielectric region, wherein the one or more waveguides are optically coupled with the light modulator; a semiconductor support structure on the semiconductor substrate and in the dielectric region; a mirror structure over the semiconductor support structure in the dielectric region configured to receive a modulated light signal from the one or more waveguides, wherein the mirror structure is configured to redirect the modulated light signal from a first direction generally parallel to a top surface of the semiconductor substrate to a second direction generally perpendicular to the first direction; and a grating coupler configured to direct an input light signal from the second direction to the first direction.

8. The semiconductor photonic device of claim 7, wherein, The mirror structure is over a beveled angled sidewall of the semiconductor support structure.

9. The semiconductor photonic device of claim 8, wherein, The mirror structure is positioned at an angle relative to a top surface of the semiconductor substrate; and wherein the angle of the mirror structure corresponds to an angle of the beveled angled sidewall of the semiconductor support structure.

10. The semiconductor photonic device of claim 7, wherein, Further comprising: an oxide barrier layer between the semiconductor support structure and mirror structure.

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