I2C bus deadlock self-recovery circuit, hard disk backboard and server
By designing an I2C bus deadlock self-recovery circuit, the I2C bus state is detected and reset using hardware circuitry, which solves the problems of resource consumption and debugging costs when the I2C bus is dead and realizes the self-recovery function without software intervention.
Patent Information
- Application Number
- CN202423310817.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In existing technologies, when the I2C bus is hung, software programs are required to control the power-on/off of slave devices and coordinate bus access, which consumes processor resources and increases software development and debugging costs.
An I2C bus deadlock self-recovery circuit was designed, including a reset signal generation sub-circuit and a slave device reset sub-circuit. The hardware circuit detects and generates a reset signal to reset the I2C bus state, avoiding software intervention.
It achieves self-recovery of the I2C bus in deadlock conditions without software intervention, improving system stability and reducing debugging difficulty and resource consumption.
Smart Images
Figure CN223728215U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to server technical field, concretely relates to I2C bus deadlock self -recovery circuit, hard disk backplate and server. BACKGROUND
[0002] I2C bus (I2C full name is Inter-Integrated Circuit, also called IIC, indicates integrated circuit bus) is a kind of standard widely used in communication between electronic equipment, it uses two lines, namely serial data line (SDA, its full name is Serial Data) and serial clock line (SCL, its full name is Serial Clock) to carry out two-way transmission, effectively reduces the connection complexity.Equation wherein, SDA line is used to transmit data, can be controlled by master device or slave device.SCL line is used to transmit clock signal, is controlled by master device.SCL line level change determines the synchronism of data transmission, i.e.transmit one bit data in each clock cycle.
[0003] I2C bus protocol stipulates that SCL is at high level, SDA changes from high level to low level to indicate start signal;When SCL is low, the state of SDA can switch;When SCL is at high level, the state of SDA can be sampled;After transmitting 8 bits of data, the receiving party needs to pull down SDA to indicate response;When SCL is high, SDA changes from low to high to indicate communication end signal.
[0004] I2C bus supports multiple master devices, but only one master device can control bus communication at the same time.When multiple master devices try to communicate at the same time, bus arbitration mechanism is needed to determine which master device controls the bus, and other devices can only communicate when the bus is idle.But when some abnormal conditions occur, the bus is continuously pulled down by a certain device, and the communication on the whole bus is suspended, i.e.I2C bus is dead, which may affect the performance and stability of the system, and may even cause the whole system to malfunction or damage the device.
[0005] The existing way to solve the problem that I2C bus is dead usually needs software program to control the power-on and power-off of slave device and bus access coordination, which consumes processor resources and increases the cost of software development and debugging. UTILITY MODEL CONTENTS
[0006] The utility model provides I2C bus deadlock self -recovery circuit, hard disk backplate and server, aims at solving the problem that software program is needed to control the power-on and power-off of slave device and bus access coordination when I2C bus is dead in the recovery of prior art, which not only consumes processor resources, but also increases the cost of software development and debugging.
[0007] The utility model provides a kind of I2C bus deadlock self-recovery circuit, applied to the I2C bus of master device, it includes: reset signal generation subcircuit and slave device reset subcircuit, the input of the reset signal generation subcircuit is connected with the I2C bus of the master device, and the output of the reset signal generation subcircuit is connected with the slave device reset subcircuit;The reset signal generation subcircuit is used to generate reset signal and input to the slave device reset subcircuit when I2C bus deadlock;The slave device reset subcircuit is used to reset I2C bus state according to reset signal to self-recovery.
[0008] Further, the reset signal generation subcircuit includes signal sampling unit, signal shaping isolation unit, RC delay and fast discharge unit and logic operation unit;The input of the signal sampling unit is connected with the I2C bus, and the output of the signal sampling unit is connected with the input of the signal shaping isolation unit;The output of the signal shaping isolation unit is connected with the input of the RC delay and fast discharge unit;The output of the RC delay and fast discharge unit is connected with the input of the logic operation unit;The output of the logic operation unit is connected with the slave device reset subcircuit;
[0009] The signal sampling unit is used to carry out signal sampling processing to the input signal of the I2C bus of the master device, and obtain first processing signal;
[0010] The signal shaping isolation unit is used to carry out flip, shaping and noise filtering processing to the first processing signal, and obtain second processing signal;
[0011] The RC delay and fast discharge unit is used to carry out RC delay and fast discharge processing to the second processing signal, and obtain third processing signal;
[0012] The logic operation unit is used to carry out logic operation to the third processing signal, and obtain the reset signal.
[0013] Further, the signal sampling unit includes first signal sampling subunit and second signal sampling subunit;
[0014] The first signal sampling subunit includes first resistance, and the first end of the first resistance is connected with serial clock line in the I2C bus, and the second end of the first resistance is connected with the input of the signal shaping isolation unit;
[0015] The second signal sampling subunit includes second resistance, and the first end of the second resistance is connected with serial data line in the I2C bus, and the second end of the second resistance is connected with the input of the signal shaping isolation unit.
[0016] Further, the signal shaping and isolating unit comprises a first inverting Schmitt trigger, a second inverting Schmitt trigger and a first capacitor; the input end of the first inverting Schmitt trigger is connected with the second end of the first resistor, the output end of the first inverting Schmitt trigger is connected with the RC delay and fast discharge unit, and the grounding end of the first inverting Schmitt trigger is used for grounding; the first end of the first capacitor is connected with the power supply end of the first inverting Schmitt trigger, the first end of the first capacitor is also connected with a power supply, and the second end of the first capacitor is grounded; the input end of the second inverting Schmitt trigger is connected with the second end of the second resistor, and the output end of the second inverting Schmitt trigger is connected with the RC delay and fast discharge unit.
[0017] Further, the RC delay and fast discharge unit comprises a first RC delay and fast discharge subunit and a second RC delay and fast discharge subunit.
[0018] The first RC delay and fast discharge subunit comprises a third resistor, a fourth resistor, a second capacitor and a first diode; the first end of the third resistor is connected with the output end of the first inverting Schmitt trigger, and the second end of the third resistor is connected with the first end of the fourth resistor; the second end of the fourth resistor is connected with the first end of the second capacitor; the second end of the second capacitor is grounded; the positive electrode of the first diode is connected with the second end of the fourth resistor, and the negative electrode of the first diode is connected with the first end of the fourth resistor.
[0019] The second RC delay and fast discharge subunit comprises a fifth resistor, a sixth resistor, a third capacitor and a second diode; the first end of the fifth resistor is connected with the output end of the second inverting Schmitt trigger, and the second end of the fifth resistor is connected with the first end of the sixth resistor; the second end of the sixth resistor is connected with the first end of the third capacitor; the second end of the third capacitor is grounded; the positive electrode of the second diode is connected with the second end of the sixth resistor, and the negative electrode of the second diode is connected with the first end of the sixth resistor.
[0020] Further, the logic operation unit comprises a first logic operation subunit and a second logic operation subunit.
[0021] The first logic operation subunit comprises a third inverting Schmitt trigger, a fourth capacitor, a third diode and a seventh resistor; the input end of the third inverting Schmitt trigger is connected with the second end of the fourth resistor, the output end of the third inverting Schmitt trigger is grounded through the fourth capacitor, and the output end of the third inverting Schmitt trigger is also connected with the negative electrode of the third diode; the positive electrode of the third diode is connected with the pull-up power supply through the seventh resistor.
[0022] The second logic operator unit comprises a fourth inverting Schmitt trigger, a fifth capacitor and a fourth diode, the input end of the fourth inverting Schmitt trigger is connected with the second end of the sixth resistor, the output end of the fourth inverting Schmitt trigger is grounded through the fifth capacitor, and the output end of the fourth inverting Schmitt trigger is also connected with the negative electrode of the fourth diode; the positive electrode of the fourth diode is connected with the pull-up power supply through the seventh resistor.
[0023] Further, the slave device reset sub-circuit adopts an I2C bus switch, and a RESET# pin of the I2C bus switch is connected with the reset signal generation sub-circuit.
[0024] Further, a plurality of slave devices can be connected on the I2C bus switch.
[0025] In a second aspect, the utility model also provides a hard disk backboard which comprises the I2C bus deadlock self-recovery circuit of the first aspect.
[0026] In a third aspect, the utility model also provides a server which comprises the I2C bus deadlock self-recovery circuit of the first aspect.
[0027] Compared with the prior art, the utility model provides I2C bus deadlock self-recovery circuit, hard disk backboard and server, including reset signal generation sub-circuit and slave device reset sub-circuit, the input end of reset signal generation sub-circuit is connected with the I2C bus of host device, and the output end of reset signal generation sub-circuit is connected with slave device reset sub-circuit;Reset signal generation sub-circuit is used for generating reset signal and inputting to slave device reset sub-circuit when I2C bus deadlock;Slave device reset sub-circuit is used for resetting I2C bus state according to reset signal to self-recovery.In the embodiment of the utility model, I2C bus state can be detected without software participation, when bus deadlock problem appears, the circuit sends reset signal, so that slave device reset releases the bus, to guarantee the normal operation of system. BRIEF DESCRIPTION OF DRAWINGS
[0028] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the drawings needed to be used in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are some embodiments of the utility model, and for ordinary skilled in the art, other drawings can also be obtained according to these drawings without creating labor.
[0029] Figure 1 It is a schematic block diagram of the I2C bus deadlock self-recovery circuit provided by the utility model;
[0030] Figure 2Another schematic block diagram of the I2C bus deadlock self-recovery circuit is provided in the utility model
[0031] Figure 3 The circuit principle schematic diagram of the reset signal generation sub-circuit in the I2C bus deadlock self-recovery circuit is provided in the utility model
[0032] Figure 4 The circuit principle schematic diagram of the slave device reset sub-circuit in the I2C bus deadlock self-recovery circuit is provided in the utility model. DETAILED DESCRIPTION
[0033] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0034] The direction terms mentioned in the utility model, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side" and the like, are only the directions of the attached drawings. Therefore, the direction terms used are used to explain and understand the utility model, rather than to limit the utility model. In addition, in the drawings, structures similar or identical in structure are denoted by the same reference numerals.
[0035] It should be understood that when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0036] It should also be understood that the terms used in the utility model specification are only for the purpose of describing specific embodiments and are not intended to limit the utility model. As used in the utility model specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.
[0037] It should be further understood that the term "and / or" used in the utility model specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.
[0038] Please refer to Figure 1 , which is a schematic block diagram of the I2C bus deadlock self-recovery circuit provided by the utility model. As Figure 1As shown, the I2C bus deadlock self-recovery circuit 10 provided by the embodiment of the utility model is applied to the I2C bus of the host device, which comprises: a reset signal generation subcircuit 11 and a slave device reset subcircuit 12, the input end of the reset signal generation subcircuit is connected with the I2C bus of the host device, and the output end of the reset signal generation subcircuit is connected with the slave device reset subcircuit; the reset signal generation subcircuit is used for generating a reset signal and inputting to the slave device reset subcircuit when the I2C bus is deadlocked; and the slave device reset subcircuit is used for resetting the I2C bus state according to the reset signal to self-recover.
[0039] In the embodiment, during the idle period of the I2C bus of the host device, the serial data line signal and the serial clock line signal are maintained in the high level state, and once entering the data interaction link, the I2C bus transmits information by generating a low level pulse.If the I2C bus is maintained in the low level state for a long time without recovery, it means that the system is in a deadlock state. At this time, the reset signal generation subcircuit can detect whether the I2C bus enters the deadlock state. If the I2C bus is continuously pulled low, the reset signal generation subcircuit generates a reset signal to reset the I2C state machine corresponding to the I2C bus and cancel the selected state of all slave devices, so as to realize bus reset and cancel the selected state of all channels (i.e. the multiple channels of the slave device reset subcircuit are connected with multiple slave devices respectively), so that the system can work normally. It can be seen that by the above-mentioned mode, the situation that the I2C bus cannot be recovered when the deadlock occurs is solved only by the hardware circuit design. Moreover, only the hardware circuit design is relied on without the participation of software, the stability of the whole system is improved, and the difficulty of system debugging is reduced.
[0040] In an embodiment, as shown in Figure 1 and Figure 2 the reset signal generation subcircuit 11 comprises a signal sampling unit 111, a signal shaping and isolation unit 112, an RC delay and fast discharge unit 113 and a logic operation unit 114; the input end of the signal sampling unit 111 is connected with the I2C bus, the output end of the signal sampling unit 111 is connected with the input end of the signal shaping and isolation unit 112; the output end of the signal shaping and isolation unit 112 is connected with the input end of the RC delay and fast discharge unit 113; the output end of the RC delay and fast discharge unit 113 is connected with the input end of the logic operation unit 114; and the output end of the logic operation unit 114 is connected with the slave device reset subcircuit 12;
[0041] the signal sampling unit 111 is used for signal sampling processing the input signal of the I2C bus of the host device to obtain a first processing signal;
[0042] The signal shaping and isolating unit 112 is configured to perform inversion, shaping and noise filtering on the first processing signal to obtain a second processing signal.
[0043] The RC delay and fast discharge unit 113 is configured to perform RC delay and fast discharge on the second processing signal to obtain a third processing signal.
[0044] The logic operation unit 114 is configured to perform logic operation on the third processing signal to obtain the reset signal.
[0045] In the embodiment, after detecting the input signal of the I2C bus of the host device, the signal sampling unit 111 performs signal sampling on the input signal to obtain a first processing signal for the protection of subsequent circuit components, so as to avoid the input end of the signal sampling unit 111 from being impacted by excessive current. Then, the signal shaping and isolating unit 112 performs inversion, shaping and noise filtering on the first processing signal to output a clear second processing signal. Then, the RC delay and fast discharge unit 113 performs RC delay and fast discharge on the second processing signal to obtain a third processing signal. Finally, the logic operation unit 114 performs logic operation on the third processing signal output by the RC delay and fast discharge unit 113 to determine whether to generate a reset signal. Through the above process, the serial data line signal and the clock line signal of the I2C bus are shaped and delayed, and finally a reset signal is generated.
[0046] In an embodiment, as shown in Figures 1-3 The signal sampling unit 111 includes a first signal sampling subunit (not shown) and a second signal sampling subunit (not shown).
[0047] The first signal sampling subunit includes a first resistor R1, a first end of the first resistor R1 is connected with the serial clock line in the I2C bus, and a second end of the first resistor R1 is connected with the input end of the signal shaping and isolating unit 112.
[0048] The second signal sampling subunit includes a second resistor R2, a first end of the second resistor R2 is connected with the serial data line in the I2C bus, and a second end of the second resistor R2 is connected with the input end of the signal shaping and isolating unit 112.
[0049] In the embodiment, the first resistor R1 and the second resistor R2 connected with the input end of the signal shaping and isolating unit 112 can effectively protect the signal shaping and isolating unit 112 from being impacted by excessive current, and effectively protect subsequent circuit components.
[0050] In an embodiment, as shown in Figures 1-3As shown, the signal shaping and isolating unit 112 includes a first inverting Schmitt trigger U1, a second inverting Schmitt trigger U2 and a first capacitor C1; an input end of the first inverting Schmitt trigger U1 is connected with a second end of the first resistor R1, an output end of the first inverting Schmitt trigger U1 is connected with the RC delay and fast discharge unit 113, and a grounding end of the first inverting Schmitt trigger U1 is grounded; a first end of the first capacitor C1 is connected with a power supply end of the first inverting Schmitt trigger U1, the first end of the first capacitor C1 is also connected with a power supply VCC, and a second end of the first capacitor C1 is grounded; an input end of the second inverting Schmitt trigger U2 is connected with a second end of the second resistor R2, and an output end of the second inverting Schmitt trigger U2 is connected with the RC delay and fast discharge unit 113.
[0051] In the embodiment, the first inverting Schmitt trigger U1 and the second inverting Schmitt trigger U2 are core devices of the signal shaping and isolating unit 112, which can flip, shape and filter noise of signals output by the first signal sampling subunit and the second signal sampling subunit, and output clear second processing signals. The first capacitor C1 is a bypass capacitor of the first inverting Schmitt trigger U1.
[0052] In an embodiment, as shown in Figures 1-3 The RC delay and fast discharge unit 113 includes a first RC delay and fast discharge subunit (not shown) and a second RC delay and fast discharge subunit (not shown);
[0053] The first RC delay and fast discharge subunit includes a third resistor R3, a fourth resistor R4, a second capacitor C2 and a first diode D1; a first end of the third resistor R3 is connected with an output end of the first inverting Schmitt trigger U1, and a second end of the third resistor R3 is connected with a first end of the fourth resistor R4; a second end of the fourth resistor R4 is connected with a first end of the second capacitor C2; a second end of the second capacitor C2 is grounded; a positive electrode of the first diode D1 is connected with the second end of the fourth resistor R4, and a negative electrode of the first diode D2 is connected with the first end of the fourth resistor R4;
[0054] The second RC delay and fast discharge unit comprises a fifth resistor R5, a sixth resistor R6, a third capacitor C3 and a second diode D2, a first end of the fifth resistor R5 is connected with an output end of the second inverting Schmitt trigger U2, a second end of the fifth resistor R5 is connected with a first end of the sixth resistor R6; a second end of the sixth resistor R6 is connected with a first end of the third capacitor C3; a second end of the third capacitor C3 is grounded; a positive electrode of the second diode D2 is connected with the second end of the sixth resistor R6, and a negative electrode of the second diode D2 is connected with the first end of the sixth resistor R6.
[0055] In the embodiment, the output end of the first inverting Schmitt trigger U1 is connected to the ground through the third resistor R3 (for example, 100Ω) in series with the fourth resistor R4 (for example, 1000kΩ), and then through the second capacitor C2 (for example, 1uF) in parallel to the ground, forming a first RC delay circuit. A first diode D1 is connected in parallel across the fourth resistor R4, and the first diode D1 functions to ensure that the second capacitor C2 can be quickly discharged so as to respond quickly at the beginning of the next signal period. The signal processed by the RC delay and fast discharge of the first RC delay and fast discharge unit is input to the input end of the logic operation unit 114. Moreover, when the output end of the first inverting Schmitt trigger U1 generates a high pulse, current will charge the second capacitor C2 through the third resistor R3 and the fourth resistor R4, and with the passage of time, the voltage on the second capacitor C2 gradually rises, and when the voltage reaches the threshold voltage of the logic operation unit 114 and is determined to be a high level, the output of the logic operation unit 114 will become a low level. If the voltage of the second capacitor C2 rises to the threshold voltage before the high pulse of the output end of the first inverting Schmitt trigger U1 disappears, the second capacitor C2 is quickly discharged through the path of the first diode D1, the third resistor R3 and the output end of the first inverting Schmitt trigger U1, so as to ensure that the circuit returns to the initial state in time and is ready for the next signal period.
[0056] Similarly, the output of the second inverting Schmitt trigger U2 is connected through a fifth resistor R5 (e.g., 100 Ω) in series with a sixth resistor R6 (e.g., 1000 kΩ), and then through a third capacitor C3 (e.g., 1 uF) to ground, forming a second RC delay circuit. A second diode D2 is connected in parallel across the sixth resistor R6, and the second diode D2 functions to ensure that the third capacitor C3 can be quickly discharged so as to respond quickly at the start of the next signal period. The signal after the RC delay and quick discharge processing of the second RC delay and quick discharge unit is input to the input of the logic operation unit 114. Moreover, when a high pulse is generated at the output of the second inverting Schmitt trigger U2, current charges the third capacitor C3 through the fifth resistor R5 and the sixth resistor R6, and over time the voltage on the third capacitor C3 gradually rises. When the voltage reaches the threshold voltage that is determined to be a high level at the logic operation unit 114, the output of the logic operation unit 114 becomes a low level. If the voltage on the third capacitor C3 rises to the threshold voltage before the high pulse at the output of the second inverting Schmitt trigger U2 disappears, the third capacitor C3 is quickly discharged through the second diode D2, the fifth resistor R5, and the output of the second inverting Schmitt trigger U2, so as to ensure that the circuit returns to the initial state in time and is ready for the next signal period.
[0057] In one embodiment, as shown in FIG. 1, the logic operation unit 114 includes a first logic operation subunit (not shown) and a second logic operation subunit (not shown). Figures 1-3
[0058] The first logic operation subunit includes a third inverting Schmitt trigger U3, a fourth capacitor C4, a third diode D3, and a seventh resistor R7. The input of the third inverting Schmitt trigger U3 is connected to the second end of the fourth resistor R4. The output of the third inverting Schmitt trigger U3 is connected to ground through the fourth capacitor C4, and is also connected to the negative electrode of the third diode D3. The positive electrode of the third diode D3 is connected to the pull-up power supply VCC through the seventh resistor R7.
[0059] The second logic operation subunit includes a fourth inverting Schmitt trigger U4, a fifth capacitor C5, and a fourth diode D4. The input of the fourth inverting Schmitt trigger U4 is connected to the second end of the sixth resistor R6. The output of the fourth inverting Schmitt trigger U4 is connected to ground through the fifth capacitor C5, and is also connected to the negative electrode of the fourth diode D4. The positive electrode of the fourth diode D4 is connected to the pull-up power supply VCC through the seventh resistor R7.
[0060] In the embodiment, the output terminal of the third inverting Schmitt trigger U3 is connected with the fourth capacitor C4 (1nF) for filtering to further stabilize the signal. The output signals of the third inverting Schmitt trigger U3 and the fourth inverting Schmitt trigger U4 are subjected to logical AND operation after the processing of the serial data line signal and the serial clock line signal, that is, the negative poles of the third diode D3 and the fourth diode D4 are connected respectively, and the anodes of the third diode D3 and the fourth diode D4 are connected together and connected with the 3.3V pull-up power supply VCC. In this way, when the output signals of the third inverting Schmitt trigger U3 and the fourth inverting Schmitt trigger U4 are both high level, the positive poles of the third diode D3 and the fourth diode D4 remain high level, and the RESET- reset signal is not triggered. When any one of the output signals of the third inverting Schmitt trigger U3 and the fourth inverting Schmitt trigger U4 is low level, the positive poles of the third diode D3 and the fourth diode D4 are pulled down to low level, thereby generating the RESET- reset signal. Through the above-mentioned manner, the serial data line signal and the serial clock line signal of the I2C bus are shaped and delayed, and finally a RESET- reset signal is generated. The first inverting Schmitt trigger U1 to the fourth inverting Schmitt trigger U4 can be integrated on the same chip, and each has an input terminal, an output terminal, a power supply terminal and a ground terminal.
[0061] In an embodiment, as shown in Figure 1 、 Figure 2 and Figure 4 , the slave device reset sub-circuit 12 adopts the I2C bus switch U5, and the RESET# pin of the I2C bus switch U5 is connected with the reset signal generation sub-circuit 11.
[0062] The I2C bus switch U5 can be connected with multiple slave devices.
[0063] In the embodiment, the slave device reset sub-circuit 12 can adopt the I2C bus switch of the PCA9548APW (in specific implementation, it can also be other models of I2C bus switch) to reset the I2C bus, which provides low-level effective reset input and allows the slave device to recover from the situation of being stalled in low level state from the downstream I2C bus. The slave device reset sub-circuit 12 has three address pins, allowing up to eight devices to be connected to the I2C bus.
[0064] When the I2C bus of the master device is in a deadlock situation, the reset signal generation sub-circuit 11 outputs a low-level reset signal to the RESET# pin of the slave device reset sub-circuit 12, resets the state of the I2C bus, and cancels the selected state of all channels, so that the system can work normally.
[0065] It can be seen that when the I2C bus needs to mount more slave devices, the circuit complexity grows slowly in the embodiment of the utility model, and the overall circuit complexity is low, the components are few, and the wiring is simple, so as to realize low cost.
[0066] The utility model also provides a kind of hard disk backboard, including the I2C bus deadlock self-recovery circuit described in preceding embodiment.
[0067] In the embodiment, the hard disk backboard in the embodiment of the utility model includes I2C bus deadlock self-recovery circuit, wherein, the I2C bus deadlock self-recovery circuit can refer to the above embodiment, and since the hard disk backboard includes all the technical solutions of the I2C bus deadlock self-recovery circuit embodiment, the hard disk backboard at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here.
[0068] The utility model also provides a kind of server, including the I2C bus deadlock self-recovery circuit described in preceding embodiment, or including the hard disk backboard described in preceding embodiment.
[0069] In the embodiment, the server in the embodiment of the utility model includes I2C bus deadlock self-recovery circuit, wherein, the I2C bus deadlock self-recovery circuit can refer to the above embodiment. And since the server (specific implementation can be edge server) includes all the technical solutions of the I2C bus deadlock self-recovery circuit embodiment, the server at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here.
[0070] The utility model provides I2C bus deadlock self-recovery circuit, hard disk backplate and server, including reset signal generation subcircuit and slave device reset subcircuit, the input of reset signal generation subcircuit is connected with the I2C bus of master device, and the output of reset signal generation subcircuit is connected with slave device reset subcircuit;Reset signal generation subcircuit is used to generate reset signal and input to slave device reset subcircuit when I2C bus deadlock;Slave device reset subcircuit is used to reset I2C bus state according to reset signal to self-recovery.In the embodiment of the utility model, I2C bus state can be detected without software participation, when bus deadlock problem appears, circuit sends reset signal, so that slave device reset releases bus, to guarantee the normal operation of system.
[0071] The above is only the specific embodiment of the utility model, but the protection scope of the utility model is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the utility model, and these modifications or replacements should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of claims.
Claims
1. An I2C bus deadlock self-recovery circuit applied to an I2C bus of a master device, characterized in that, The application relates to an I2C bus reset device and a reset signal generation subcircuit and a slave device reset subcircuit, an input end of the reset signal generation subcircuit is connected with an I2C bus of a master device, and an output end of the reset signal generation subcircuit is connected with the slave device reset subcircuit; the reset signal generation subcircuit is used for generating a reset signal and inputting the reset signal to the slave device reset subcircuit when the I2C bus is in a deadlock state; and the slave device reset subcircuit is used for resetting the I2C bus state according to the reset signal to recover automatically. The reset signal generation subcircuit comprises a signal sampling unit, a signal shaping and isolating unit, an RC delay and fast discharge unit and a logic operation unit; an input end of the signal sampling unit is connected with the I2C bus, an output end of the signal sampling unit is connected with an input end of the signal shaping and isolating unit, an output end of the signal shaping and isolating unit is connected with an input end of the RC delay and fast discharge unit, an output end of the RC delay and fast discharge unit is connected with an input end of the logic operation unit, and an output end of the logic operation unit is connected with the slave device reset subcircuit.
2. The I2C bus deadlock recovery circuit of claim 1, wherein, The signal sampling unit is used for performing signal sampling processing on an input signal of the I2C bus of the master device to obtain a first processing signal. The signal shaping and isolating unit is used for performing inversion, shaping and noise filtering processing on the first processing signal to obtain a second processing signal. The RC delay and fast discharge unit is used for performing RC delay and fast discharge processing on the second processing signal to obtain a third processing signal. The logic operation unit is used for performing logic operation on the third processing signal to obtain the reset signal. The signal sampling unit comprises a first signal sampling subunit and a second signal sampling subunit.
3. The I2C bus deadlock self-recovery circuit according to claim 2, characterized in that, The first signal sampling subunit comprises a first resistor, a first end of the first resistor is connected with a serial clock line in the I2C bus, and a second end of the first resistor is connected with an input end of the signal shaping and isolating unit. The second signal sampling subunit comprises a second resistor, a first end of the second resistor is connected with a serial data line in the I2C bus, and a second end of the second resistor is connected with an input end of the signal shaping and isolating unit. The signal shaping and isolating unit comprises a first inverting Schmitt trigger, a second inverting Schmitt trigger and a first capacitor, an input end of the first inverting Schmitt trigger is connected with the second end of the first resistor, an output end of the first inverting Schmitt trigger is connected with the RC delay and fast discharge unit, and a grounding end of the first inverting Schmitt trigger is used for grounding, a first end of the first capacitor is connected with a power supply end of the first inverting Schmitt trigger, the first end of the first capacitor is also connected with a power supply, and a second end of the first capacitor is grounded, an input end of the second inverting Schmitt trigger is connected with the second end of the second resistor, and an output end of the second inverting Schmitt trigger is connected with the RC delay and fast discharge unit.
4. The I2C bus deadlock recovery circuit of claim 3, wherein, The RC delay and fast discharge unit comprises a first RC delay and fast discharge subunit and a second RC delay and fast discharge subunit.
5. The I2C bus deadlock self-recovery circuit according to claim 4, characterized in that, The first RC delay and fast discharge unit comprises a third resistor, a fourth resistor, a second capacitor and a first diode, a first end of the third resistor is connected with an output end of the first inverting Schmitt trigger, a second end of the third resistor is connected with a first end of the fourth resistor; a second end of the fourth resistor is connected with a first end of the second capacitor; a second end of the second capacitor is grounded; a positive electrode of the first diode is connected with the second end of the fourth resistor, and a negative electrode of the first diode is connected with the first end of the fourth resistor; The second RC delay and fast discharge unit comprises a fifth resistor, a sixth resistor, a third capacitor and a second diode, a first end of the fifth resistor is connected with an output end of the second inverting Schmitt trigger, a second end of the fifth resistor is connected with a first end of the sixth resistor; a second end of the sixth resistor is connected with a first end of the third capacitor; a second end of the third capacitor is grounded; a positive electrode of the second diode is connected with the second end of the sixth resistor, and a negative electrode of the second diode is connected with the first end of the sixth resistor.
6. The I2C bus deadlock self-recovery circuit according to claim 5, characterized in that, The logic operation unit comprises a first logic operation subunit and a second logic operation subunit; The first logic operation subunit comprises a third inverting Schmitt trigger, a fourth capacitor, a third diode and a seventh resistor, an input end of the third inverting Schmitt trigger is connected with the second end of the fourth resistor, an output end of the third inverting Schmitt trigger is grounded through the fourth capacitor, and the output end of the third inverting Schmitt trigger is also connected with a negative electrode of the third diode; a positive electrode of the third diode is connected with an upper pull power supply through the seventh resistor; The second logic operation subunit comprises a fourth inverting Schmitt trigger, a fifth capacitor and a fourth diode, an input end of the fourth inverting Schmitt trigger is connected with the second end of the sixth resistor, an output end of the fourth inverting Schmitt trigger is grounded through the fifth capacitor, and the output end of the fourth inverting Schmitt trigger is also connected with a negative electrode of the fourth diode; a positive electrode of the fourth diode is connected with the upper pull power supply through the seventh resistor.
7. The I2C bus deadlock recovery circuit of claim 1, wherein, The slave device reset subcircuit adopts an I2C bus switch, and a RESET# pin of the I2C bus switch is connected with the reset signal generation subcircuit.
8. The I2C bus deadlock self-recovery circuit according to claim 7, characterized in that, A plurality of slave devices can be connected on the I2C bus switch.
9. A hard disk backplane, characterized by An I2C bus deadlock self-recovery circuit comprising any one of claims 1-8.
10. A server, characterized by An I2C bus deadlock self-recovery circuit comprising any one of claims 1-8.