ATX power-on circuit based on hardware self-locking

Abstract

The utility model relates to an ATX power-on circuit based on hardware self-locking. The ATX power-on circuit comprises a power failure detection circuit, a self-locking switch circuit and a residual power detection circuit. The ATX power-on circuit based on hardware self-locking is ingenious in design; power source time sequence control is achieved through a pure hardware circuit, voltage-regulator tube threshold comparison, MOS self-locking logic and triode residual electricity detection serve as the core, the voltage-regulator tube threshold comparison, the MOS self-locking logic and the triode residual electricity detection form a closed loop of'detection-locking-release ', by means of the cooperation mechanism, the problem of time sequence disorder caused by rapid plugging is thoroughly avoided, delay or misjudgment of software intervention in a traditional scheme is avoided, and the reliability of the power source is improved. The time sequence strictly follows hardware logic, the problems that a traditional scheme is high in cost and slow in response, needs software cooperation and the like are solved, and the method is particularly suitable for industrial control equipment and other high-reliability scenes.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of computer power management more specifically, it relates to a kind of ATX start-up circuit based on hardware self-locking. BACKGROUND

[0002] Many ATX power supply powered mainboards currently, in BIOS, set to incoming call self-starting, ATX power supply powered mainboard has the following problems when plugging in and out quickly:

[0003] 1, timing disorder: ATX power supply plugging in and out quickly can cause power signal not to be discharged completely, and the mainboard timing logic is abnormal when powering on again, and causes crash;

[0004] 2, defects of MCU / BMC scheme: MCU / BMC detection circuit with high cost needs software cooperation, relies on large capacity capacitor to maintain power supply when power off, increases volume and cost;

[0005] 3, insufficient versatility: poor circuit adaptability caused by software dependence, which cannot realize hardware-level fast response. INVENTION CONTENTS

[0006] The utility model provides a kind of ATX start-up circuit based on hardware self-locking to solve the technical problems of the prior art.

[0007] The technical scheme adopted by the utility model to solve its technical problems is: a kind of ATX start-up circuit based on hardware self-locking, comprising:

[0008] Power-off detection circuit, for detecting main power voltage drop and output trigger signal;

[0009] Self-locking switch circuit, for receiving the trigger signal and cutting off PS_ON connection and entering locking state;

[0010] Residual power detection circuit, for detecting whether each power rail voltage of system is lower than preset threshold value, and releasing self-locking after reaching standard.

[0011] The ATX start-up circuit, wherein the power-off detection circuit includes voltage comparator, Q61 voltage stabilizing diode and at least one voltage dividing resistor;The threshold value is set through the voltage dividing resistor at the inverting input end of the voltage comparator, and the highest value of power voltage is connected to the same-phase input end.

[0012] The ATX start-up circuit, wherein the highest value of power voltage is less than the threshold value after voltage division through the voltage dividing resistor, and the voltage comparator outputs low-level pulse to the self-locking switch circuit.

[0013] The utility model discloses an ATX starting circuit, wherein, the self-locking switch circuit includes the first NMOS pipe and PMOS pipe in series, the first NMOS pipe includes Q13 / Q60 / Q65 diode, the PMOS pipe includes Q59 diode, the first NMOS pipe grid is controlled to the logic or gate by Q13 diode and Q60 diode, and the Q59 diode conduction maintains the locking signal.

[0014] The utility model discloses an ATX starting circuit, wherein, after the self-locking switch receives the trigger signal, the 3PIN of Q13 diode will pull down the G pole of Q65 diode to disconnect the PSON of mainboard and ATX, and the Q59 diode conduction will pull up the self-locking signal, force Q60 diode to conduct, so that the G pole of Q65 diode is connected to the ground, and further maintain the off state of Q65.

[0015] The utility model discloses an ATX starting circuit, wherein, the residual power detection circuit includes the AND gate, Q62 / Q63 / Q64 triode and the second NMOS pipe, the second NMOS pipe includes Q66 / Q67 diode, the base of Q62 / Q63 / Q64 triode is connected with the highest value of power voltage respectively / 5 / 3, and the collector electrode is output to the AND gate, when all power rail voltage is less than or equal to 0.7V, the AND gate output high level trigger Q66 diode conduction, and release the self-locking signal.

[0016] The utility model discloses an ATX starting circuit, wherein, after the self-locking switch circuit detects the release self-locking signal, resets and reconnects PSPS_ON, and allows normal power-on.

[0017] The utility model discloses an ATX starting circuit, wherein, the drain of Q13 diode and Q60 diode is connected to the grid of Q65 diode.

[0018] The source of Q13 diode is grounded, and the source of Q60 diode is grounded through Q67 diode.

[0019] The grid of Q13 diode is controlled by the output end of the power failure detection circuit, and the grid of Q60 diode is controlled by the self-locking signal.

[0020] The utility model discloses an ATX starting circuit, wherein, the source of Q59 diode is connected to the highest value of power voltage, the drain outputs the self-locking signal, and the grid is controlled by the drain level of Q13 diode, when Q13 diode conducts, the grid of Q59 diode is pulled down, triggers Q59 diode conduction, and pulls up the level to the highest value of power voltage.

[0021] The ATX starting circuit based on hardware self-locking has the advantages that the design is ingenious, power time sequence control is realized through a pure hardware circuit, a voltage stabilizing tube threshold comparison, MOS self-locking logic and a triode residual power detection are taken as cores, three form a closed loop of "detection, locking and release", the cooperative mechanism completely avoids time sequence confusion caused by fast plugging, avoids delay or misjudgment of software intervention in the traditional scheme, ensures that time sequence strictly follows hardware logic, solves the pain points of high cost, slow response and software cooperation of the traditional scheme, and is particularly suitable for high reliability scenes such as industrial control equipment. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the present application will be further described below with reference to the drawings and embodiments. The drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the premise of not deviating from the concept of the present application:

[0023] Figure 1 is a circuit schematic diagram of an ATX starting circuit based on hardware self-locking of a preferred embodiment of the present application;

[0024] Figure 2 is Figure 1 is a flow chart of the cooperative work of the power failure detection circuit 01, the self-locking switch circuit 02 and the residual power detection circuit 03 in the

[0025] Figure 3 is a logic truth table of the logic AND gate between the Q13 diode and the Q60 diode. DETAILED DESCRIPTION

[0026] The terms "first", "second", "third", and "fourth" and the like in the description and claims of the present application and the drawings referred to herein, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprising", "including", "containing", and "having" and their conjugates, as used herein, are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. For example, a process, method, object, or apparatus that comprises a list of steps or elements is not necessarily limited to the listed steps or elements but can include additional or other steps or elements not expressly listed or inherent to such process, method, object, or apparatus.

[0027] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiments. It is explicitly contemplated that embodiments described herein can be combined with each other.

[0028] "Multiple" refers to two or more. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents that the front and rear associated objects are in an "or" relationship.

[0029] Furthermore, the terms "up, down, front, back, left, right, upper end, lower end, longitudinal" and the like indicating the orientation are all with reference to the attitude position of the device or equipment described in the scheme in normal use. In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, not all. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present application.

[0031] The preferred embodiment of the present application is an ATX power-on circuit based on hardware self-locking, as shown in Figures 1-2 , comprising:

[0032] The power failure detection circuit 01 is used for detecting the voltage drop of the main power supply and outputting a trigger signal.

[0033] The power failure detection circuit 01 includes a voltage comparator U1, a voltage stabilizing diode Q61 and voltage dividing resistors R16 and R37. The inverting input terminal of the voltage comparator U1 is set to a threshold value through the voltage dividing resistors R16 and R37, and the non-inverting input terminal is connected to the highest value VCC12 of the power supply voltage.

[0034] Further, the voltage value of the highest value of the power supply voltage after voltage division by the voltage dividing resistor is less than the threshold value, for example, set to 10.8V threshold value, and the voltage comparator U1 outputs a low-level pulse to the self-locking switch circuit 02.

[0035] In the present embodiment, the power failure detection circuit is the "sentinel" of the system, which is responsible for real-time monitoring of the voltage drop of the main power supply (such as VCC12). The power failure detection circuit uses a voltage stabilizing diode (Q61) and a voltage comparator (U1) to form a threshold trigger mechanism. When the VCC12 voltage drops to 10.8V, the U1 outputs a low-level pulse as a trigger signal, realizing accurate undervoltage detection. The comparison threshold is set by the voltage dividing resistors (R16 / R37), replacing the traditional ADC sampling and reducing the hardware cost.

[0036] The self-locking switch circuit 02 is used for cutting off the PS_ON connection and entering the locking state after receiving the trigger signal.

[0037] Wherein, the self-locking switch circuit 02 includes a first NMOS tube and a PMOS tube in series, the first NMOS tube includes a Q13 / Q60 / Q65 diode; the PMOS tube includes a Q59 diode; the first NMOS tube gate is controlled by a logic OR gate composed of Q13 diode and Q60 diode, and the lock signal is maintained by the Q59 diode conduction;

[0038] The connection of Q13 diode and Q60 diode is as follows:

[0039] The drain (D) of Q13 diode and Q60 diode is connected to the gate (G) of Q65 diode;

[0040] The source (S) of Q13 diode is grounded, and the source (S) of Q60 diode is grounded through Q67 diode (controlled by the residual power detection circuit);

[0041] The gate (G) of Q13 diode is controlled by the output end of the power failure detection circuit 01, and the gate (G) of Q60 diode is controlled by the self-locking signal S1;

[0042] The source (S) of Q59 diode is connected to the highest value of the power supply voltage, the drain (D) outputs the self-locking signal, and the gate (G) is controlled by the drain (D) level of Q13 diode; when Q13 diode is turned on, the gate (G) of Q59 diode is pulled low, triggering Q59 diode to turn on, and pulling the level to the highest value of the power supply voltage.

[0043] As shown in Figure 3 When any one of Q13 or Q60 is turned on, the gate of Q65 is pulled low to the ground, forcing Q65 to turn off (disconnecting the PS_ON signal), that is, realizing the logic OR gate function.

[0044] Further, after the self-locking switch receives the trigger signal, the 3PIN of Q13 diode will pull down the G of Q65 diode to disconnect the PSON of the mainboard and the PSON of ATX, and at the same time, Q59 diode is turned on, pulling the self-locking signal high, forcing Q60 diode to turn on, so that the G of Q65 diode is grounded, further maintaining the off state of Q65.

[0045] Specifically, the positive feedback self-locking mechanism of PMOS tube Q59 is as follows:

[0046] The source (S) of Q59 diode is connected to the power supply voltage VCC, the drain (D) outputs the self-locking signal S1, and the gate (G) is controlled by the drain level of Q13 diode.

[0047] When Q13 diode is turned on, the gate of Q59 diode is pulled low, triggering Q59 diode to turn on, and pulling the level to the level voltage VCC.

[0048] The self-locking process of the self-locking switch circuit 02 is as follows:

[0049] 1. Initial triggering stage:

[0050] The power-off detection circuit outputs a low level (U1 trigger), Q13 is turned on, and the Q65 gate is pulled low, PS_ON is disconnected;

[0051] Q13 is turned on and the Q59 gate is pulled low, Q59 is turned on, and S1 is pulled high to VCC.

[0052] 2. Self-locking maintenance stage:

[0053] S1 high level makes Q60 conductive, and the Q65 gate remains low (even if the U1 trigger signal disappears, Q13 is turned off);

[0054] At this time, the circuit forms a positive feedback loop through Q60 and Q59, S1 is self-maintained at a high level, Q65 is continuously turned off, and PS_ON remains disconnected, preventing the mainboard from being powered on.

[0055] Release conditions of the self-locking switch circuit 02:

[0056] Only when the remaining power detection circuit outputs a low level (S1 is pulled low), Q60 is turned off, the Q65 gate returns to a high level, PS_ON is reconnected, and normal power-on is allowed.

[0057] In this embodiment, the self-locking switch circuit is the "switch gate" of the system, responsible for maintaining the locked state after power failure and preventing timing chaos: the low level pulse signal in the power-off detection circuit 01 is directly input to the self-locking switch circuit, triggering it to enter the locked state: the MOS tube (such as Q65) in the self-locking switch circuit immediately disconnects the PS_ON signal, forcing the mainboard to isolate from the ATX power supply and preventing abnormal power-on;

[0058] By constructing self-locking logic with NMOS tubes (Q13 / Q60 / Q65) and PMOS tubes (Q59), the PS_ON signal is forcibly disconnected when undervoltage is detected, and the locked state is maintained until the system's remaining power is released; using the switching characteristics of MOS tubes to achieve signal isolation without mechanical contacts, improving reliability.

[0059] The self-locking switch circuit 02 is designed in cooperation with the NMOS logic OR gate and the PMOS positive feedback, realizing the full hardware closed-loop control of "triggering → locking → releasing", and its core logic can be summarized as "power failure locks, and remaining power is released": fundamentally solving the timing chaos problem caused by fast plugging of the ATX power supply.

[0060] The remaining power detection circuit 03 is used to detect whether the voltage of each power rail of the system is lower than the preset threshold, and to release the self-locking when the threshold is met.

[0061] Wherein, the residual power detection circuit 03 includes an AND gate, Q62 / Q63 / Q64 triode and a second NMOS tube; the second NMOS tube includes Q66 / Q67 diode; the base of Q62 / Q63 / Q64 triode is connected to the highest value of power supply voltage / 5 / 3 respectively, and the collector is output to the AND gate; when all power rail voltages are less than or equal to 0.7V, the AND gate outputs high level to trigger the Q66 diode to be turned on, and the self-locking signal is released.

[0062] Further, the self-locking switch circuit 02 resets and reconnects PSPS_ON after detecting the release of the self-locking signal, allowing normal power-up.

[0063] In the embodiment, the residual power detection circuit is a "safety checker" of the system, which ensures that all power rails (VCC12 / 5 / 3) are completely discharged before allowing reset. The triode (Q62-Q64) is used to detect whether VCC12 / 5 / 3 is lower than 0.7V (using the base-emitter voltage drop threshold), and when all power rails are discharged to below 0.7V, the AND gate (U5) outputs high level to drive the NMOS tube (Q66 / Q67) to be turned on, releasing the self-locking signal (S1 becomes low level). The logic OR gate (U5) is used to control the conduction of the NMOS tube (Q66 / Q67), ensuring that all power rails are completely discharged before the self-locking is released. The triode base-emitter voltage drop (0.7V) is used as the residual power detection threshold, simplifying the circuit design.

[0064] It is worth noting that in the embodiment,

[0065] Q65 preferentially selects the NMOS with low on-resistance (Rds_on) in the prior art to reduce the voltage drop in the PS_ON path; the threshold voltage (Vth) of Q59 needs to be lower than the lowest operating voltage of the system (such as 3.3V).

[0066] When the ATX power supply is rapidly plugged in, the power supply voltage VCC12 is divided by R16 / R37 and compared with the reference voltage generated by the zener diode Q61. If VCC12<10.8V, the voltage comparator U1 outputs low level to make Q13 diode conductive, and the gate (G) of Q65 diode is pulled low to forcibly disconnect the PS_ON signal. At the same time, Q59 diode is turned on, maintaining the level as high, so that Q60 diode is continuously conductive to lock the state of Q65 diode. After entering the discharge phase, the base voltage of Q62-Q64 diode decreases with VCC12 / 5 / 3, and when all power rails are less than or equal to 0.7V, Q62-Q64 diode is cut off, the logic OR gate outputs high level to turn on Q66 diode, and the level becomes low to release Q60 diode, and the gate (G) of Q65 diode returns to the controlled state, allowing the system to be powered up again; through this cooperative mechanism, the timing confusion problem caused by rapid plugging is completely avoided.

[0067] The utility model provides a low -cost, no software dependence's based on hardware self -locking's ATX starting circuit, realizes power time sequence control through pure hardware circuit, with the threshold comparison of stabilivolt, MOS self -locking logic and triode residual power detection as the core, three form the closed loop of '' detection to locking to release'', avoid the delay or misjudgment of software intervention in traditional scheme, ensure that time sequence strictly follows hardware logic, solved the cost of traditional scheme is high, response is slow, needs software cooperation etc. Pain point, especially applicable to high reliability scene such as industrial control equipment.

[0068] It should be understood that, for those skilled in the art, improvements or changes can be made according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the utility model.

Claims

1. A hardware self-locking based ATX power-on circuit, characterized in that, The application relates to a power supply system, which comprises a power supply voltage drop detection circuit, a self-locking switch circuit and a residual power detection circuit. The power supply voltage drop detection circuit is used for detecting a power supply voltage drop and outputting a trigger signal. The self-locking switch circuit is used for cutting off a PS_ON connection and entering a locking state after receiving the trigger signal. The residual power detection circuit is used for detecting whether each power supply rail voltage of a system is lower than a preset threshold value and releasing the self-locking after reaching the threshold value.

2. The hardware self-locking based ATX power-on circuit according to claim 1, wherein, The power supply voltage drop detection circuit comprises a voltage comparator, a Q61 stabilizing diode and at least one voltage dividing resistor; the inverting input end of the voltage comparator is provided with a threshold value through the voltage dividing resistor, and the non-inverting input end is connected with the highest value of a power supply voltage.

3. The hardware self-locking based ATX power-on circuit according to claim 2, wherein, The voltage value of the highest value of the power supply voltage after being divided by the voltage dividing resistor is lower than the threshold value, and the voltage comparator outputs a low level pulse to the self-locking switch circuit.

4. The hardware self-locking based ATX power-on circuit according to claim 1, wherein, The self-locking switch circuit comprises a first NMOS tube and a PMOS tube in series; the first NMOS tube comprises Q13 / Q60 / Q65 diodes; the PMOS tube comprises a Q59 diode; the gate of the first NMOS tube is controlled by a logic OR gate composed of Q13 diodes and Q60 diodes, and the locking signal is maintained by the conduction of the Q59 diode.

5. The hardware self-locking based ATX power-on circuit according to claim 4, wherein, After the self-locking switch receives the trigger signal, the 3PIN of the Q13 diode pulls down the G electrode of the Q65 diode to disconnect the PSON of the mainboard and the PSON of the ATX, and meanwhile, the Q59 diode is turned on to pull up the self-locking signal and force the Q60 diode to be turned on so that the G electrode of the Q65 diode is connected to the ground, further maintaining the off state of the Q65.

6. The hardware self-locking based ATX power-on circuit according to claim 4, wherein, The residual power detection circuit comprises an AND gate, Q62 / Q63 / Q64 triodes and a second NMOS tube; the second NMOS tube comprises Q66 / Q67 diodes; the bases of the Q62 / Q63 / Q64 triodes are respectively connected with the highest value of the power supply voltage / 5 / 3, and the collectors are output to the AND gate; when all the power supply rail voltages are equal to or lower than 0.7V, the AND gate outputs a high level trigger to turn on the Q66 diode and release the self-locking signal.

7. The hardware self-locking based ATX power-on circuit according to claim 6, wherein, After the self-locking switch circuit detects the released self-locking signal, the self-locking switch circuit is reset and the PSPS_ON is reconnected to allow normal power-on.

8. The hardware self-locking based ATX power-on circuit according to claim 6, wherein, The drain electrodes of the Q13 diode and the Q60 diode are connected to the gate of the Q65 diode; the source electrode of the Q13 diode is grounded, and the source electrode of the Q60 diode is grounded through the Q67 diode; the gate of the Q13 diode is controlled by the output end of the power supply voltage drop detection circuit, and the gate of the Q60 diode is controlled by the self-locking signal.

9. The hardware self-locking based ATX power-on circuit according to claim 8, wherein, The source electrode of the Q59 diode is connected with the highest value of the power supply voltage, the drain electrode outputs the self-locking signal, and the gate is controlled by the level of the drain electrode of the Q13 diode; when the Q13 diode is turned on, the gate of the Q59 diode is pulled down to trigger the Q59 diode to be turned on and pull up the level to the highest value of the power supply voltage.

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