ZQ calibration circuit and semiconductor memory
By using a single comparator and calibration module in the DDR SDRAM chip for time-segmented calibration, the problem of unstable resistance performance caused by CMOS characteristic variations was solved, the accuracy of ZQ calibration was improved, and the layout area was reduced.
Patent Information
- Application Number
- CN202423147521.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-19
AI Technical Summary
In DDR SDRAM chips, the electrical performance of pull-up and pull-down resistors is unstable due to the variation of CMOS characteristics with temperature, voltage and process angle. The existing ZQ calibration process uses two comparators, which leads to inconsistent performance and affects the calibration accuracy.
A single comparator and calibration module are used to perform pull-up and pull-down calibration in time periods. The single comparator compares the connection point voltage with the reference voltage and outputs a calibration signal to adjust the resistance value, avoiding comparator deviation and mismatch, and improving calibration accuracy.
It improves the accuracy of ZQ calibration, reduces the number of comparators, and lowers the layout area.
Smart Images
Figure CN223728475U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the technical field of ZQ calibration, and particularly relate to a ZQ calibration circuit and a semiconductor memory. BACKGROUND
[0002] In a double date rate synchronous dynamic random access memory (DDR SDRAM) chip, internal pull-up resistors and pull-down resistors are composed of complementary metal oxide semiconductor field effect transistors (CMOSs). Due to the characteristics of the CMOSs, the electrical properties of the pull-up resistors and the pull-down resistors change with temperature, voltage, and process corners, thereby affecting the integrity of signals in the DRAM chip. Therefore, ZQ calibration is needed to ensure the performance of the DRAM chip under different temperatures, voltages, and process corners.
[0003] In existing DDR technology, an external resistor, for example, a 240Ω resistor, is needed to calibrate the pull-up resistors and the pull-down resistors, so as to ensure that the equivalent resistance of the pull-up resistors and the pull-down resistors is 240Ω. However, two comparators are used in the entire ZQ calibration process. Due to the bias of the comparators themselves and the mismatch between the two comparators, the performance of the two comparators is inconsistent, thereby affecting the accuracy of the ZQ calibration. UTILITY MODEL CONTENT
[0004] Embodiments of the present disclosure provide a ZQ calibration circuit and a semiconductor memory, which can improve the accuracy of ZQ calibration and reduce the layout area.
[0005] In a first aspect, the present disclosure provides a ZQ calibration circuit, comprising: a calibration module and a single comparator, a pull-up output end of the calibration module is connected to a control end of a pull-up resistor, a pull-down output end of the calibration module is connected to a control end of a pull-down resistor, an input end of the calibration module is connected to an output end of the comparator, a first connection point of the pull-up resistor and an external resistor and a second connection point of the pull-up resistor and the pull-down resistor are connected to a first input end of the comparator, and a second input end of the comparator is configured to receive a reference voltage.
[0006] The comparator is configured to compare the first connection point voltage with the reference voltage during the pull-up calibration, output a pull-up comparison signal, compare the second connection point voltage with the reference voltage during the pull-down calibration, and output a pull-down comparison signal; wherein the pull-up calibration is completed and the pull-down calibration is entered. The calibration module is configured to calibrate the pull-up resistor according to the pull-up comparison signal during the pull-up calibration, and calibrate the pull-down resistor according to the pull-down comparison signal during the pull-down calibration.
[0007] In some embodiments of the present disclosure, the calibration module includes a logic control unit, a pull-up calibration unit and a pull-down calibration unit, the pull-up output end of the logic control unit is connected to the enable end of the pull-up calibration unit, the pull-down output end of the logic control unit is connected to the enable end of the pull-down calibration unit, the output end of the pull-up calibration unit is connected to the control end of the pull-up resistor, the input end of the pull-up calibration unit is connected to the output end of the comparator, the output end of the pull-down calibration unit is connected to the control end of the pull-down resistor, and the input end of the pull-down calibration unit is connected to the output end of the comparator.
[0008] The logic control unit is configured to generate a pull-up calibration enable signal and a pull-down calibration non-enable signal in response to a ZQ calibration command, and generate a pull-up calibration non-enable signal and a pull-down calibration enable signal after the pull-up calibration is completed. The pull-up calibration unit is configured to calibrate the pull-up resistor according to the pull-up comparison signal in response to the pull-up calibration enable signal. The pull-down calibration unit is configured to calibrate the pull-down resistor according to the pull-down comparison signal in response to the pull-down calibration enable signal.
[0009] In some embodiments of the present disclosure, the ZQ calibration circuit further includes a comparison control module, the first input end of the comparison control module is connected to the first connection point, the second input end of the comparison control module is connected to the second connection point, the output end of the comparison control module is connected to the first input end of the comparator, the first control end of the comparison control module is connected to the enable end of the pull-up calibration unit, and the second control end of the comparison control module is connected to the enable end of the pull-down calibration unit.
[0010] The comparison control module is configured to turn on the first connection point and the first input end of the comparator according to the pull-up calibration enable signal, and turn on the second connection point and the first input end of the comparator according to the pull-down calibration enable signal.
[0011] In some embodiments of the present disclosure, the comparison control module comprises a first switch and a second switch, a first end of the first switch is connected to the first connection point, a second end of the first switch is connected to a first input end of the comparator, a control end of the first switch is connected to an enable end of the pull-up calibration unit, a first end of the second switch is connected to the second connection point, a second end of the second switch is connected to the first input end of the comparator, and a control end of the second switch is connected to an enable end of the pull-down calibration unit.
[0012] In some embodiments of the present disclosure, the ZQ calibration circuit further comprises an output control module, an input end of the output control module is connected to an output end of the comparator, a control end of the output control module is connected to the enable end of the pull-down calibration unit, a pull-up output end of the output control module is connected to an input end of the pull-up calibration unit, and a pull-down output end of the output control module is connected to an input end of the pull-down calibration unit.
[0013] The output control module is configured to turn on the output end of the comparator and the input end of the pull-up calibration unit according to the pull-down calibration non-enable signal, and turn on the output end of the comparator and the input end of the pull-down calibration unit according to the pull-down calibration enable signal.
[0014] In some embodiments of the present disclosure, the output control module comprises a demultiplexer, an input end of the demultiplexer is connected to an output end of the comparator, a control end of the demultiplexer is connected to the enable end of the pull-down calibration unit, a first output end of the demultiplexer is connected to an input end of the pull-up calibration unit, and a second output end of the demultiplexer is connected to an input end of the pull-down calibration unit.
[0015] In some embodiments of the present disclosure, the pull-up calibration unit comprises a pull-up calibration counter, an enable end of the pull-up calibration counter is connected to the pull-up output end of the logic control unit, an output end of the pull-up calibration counter is connected to a control end of the pull-up resistor, and an input end of the pull-up calibration counter is connected to the pull-up output end of the output control module.
[0016] In some embodiments of the present disclosure, the pull-down calibration unit comprises a pull-down calibration counter, an enable end of the pull-down calibration counter is connected to the pull-down output end of the logic control unit, an output end of the pull-down calibration counter is connected to a control end of the pull-down resistor, and an input end of the pull-down calibration counter is connected to the pull-down output end of the output control module.
[0017] In a second aspect, the present disclosure provides a semiconductor memory, comprising a pull-up resistor, a pull-down resistor, and any ZQ calibration circuit provided in the first aspect.
[0018] In some embodiments of the present disclosure, the pull-up resistor includes a first pull-up resistor and a second pull-up resistor, the first pull-up resistor and the external resistor are connected in series between a power supply and a ground, the second pull-up resistor and the pull-down resistor are connected in series between the power supply and the ground, a connection point of the first pull-up resistor and the external resistor is the first connection point, a connection point of the second pull-up resistor and the pull-down resistor is the second connection point, and control ends of the first pull-up resistor and the second pull-up resistor are connected to the pull-up output end of the calibration module.
[0019] In the technical solution of the embodiments of the present disclosure, the ZQ calibration circuit includes a calibration module and a single comparator, a pull-up output end of the calibration module is connected to a control end of a pull-up resistor, a pull-down output end of the calibration module is connected to a control end of a pull-down resistor, an input end of the calibration module is connected to an output end of the comparator, a first connection point of the pull-up resistor and an external resistor and a second connection point of the pull-up resistor and the pull-down resistor are connected to a first input end of the comparator, and a second input end of the comparator is used to receive a reference voltage. In the process of pull-up calibration, the comparator can compare a voltage at the first connection point with the reference voltage and output a pull-up comparison signal, and the calibration module calibrates the pull-up resistor according to the pull-up comparison signal. In the process of pull-down calibration, the comparator can compare a voltage at the second connection point with the reference voltage and output a pull-down comparison signal, and the calibration module calibrates the pull-down resistor according to the pull-down comparison signal. The single comparator can be used to perform pull-up calibration and pull-down calibration in different time periods, so as to realize complete ZQ calibration, avoid the influence of the deviation of the two comparators and the mismatch between the two comparators, improve the accuracy of ZQ calibration, and reduce the number of comparators, thereby reducing the layout area. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creating laborious work.
[0021] Figure 1 A partial circuit schematic diagram of a DRAM chip provided by the prior art.
[0022] Figure 2 A circuit schematic diagram of a ZQ calibration circuit provided by the prior art.
[0023] Figure 3 A circuit schematic diagram of a ZQ calibration circuit provided by the embodiments of the present disclosure. DETAILED DESCRIPTION
[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.
[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" together shall mean that the parts are joined directly or joined through one or more intermediate parts.
[0026] Reference to "an embodiment" or "the embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" or "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiments, although they can be. It is explicitly contemplated that embodiments described with respect to one embodiment can be combined with features of another embodiment.
[0027] In addition, the terms "first", "second", and the like in the description and claims of this disclosure or the above drawings are used to distinguish different objects, and are not used to describe a particular order, and can explicitly or implicitly include one or more of the features.
[0028] The term "and / or" in the present disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can mean that A exists, A and B exist, and B exists. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.
[0029] In the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" and "at least two" is two or more (including two), and similarly, "a plurality of groups" and "at least two groups" means two groups or more (including two groups).
[0030] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings.
[0031] Figure 1 A partial circuit diagram of a DRAM chip provided for the prior art, such as... Figure 1 As shown, the pull-up and pull-down resistors inside the DRAM chip are made of CMOS. The characteristics of CMOS change with temperature, voltage and process angle, which affects the electrical performance of the pull-up and pull-down resistors, and thus affects the integrity of the signal in the DRAM chip. Therefore, ZQ calibration is required to ensure the performance of the DRAM chip under different temperatures, voltages and process angles.
[0032] like Figure 1 As shown, an external resistor Rt, for example a 240Ω resistor, can be connected to the ZQ pin to calibrate the pull-up and pull-down resistors under different temperatures, voltages, and process angles, so as to ensure that the equivalent resistance of the pull-up and pull-down resistors is 240Ω.
[0033] Figure 2 A circuit diagram of a ZQ calibration circuit provided in an embodiment of this disclosure is shown below. Figure 2 As shown, the DRAM receives the ZQ calibration command sent by the Central Processing Unit (CPU), generates the internal calibration command ZQCMD and calibration clock ZQCLK based on the encoder, and generates the pull-up calibration enable signal ZQPU and the pull-down calibration enable signal ZQPD based on the logic controller. These two enable signals control the start of pull-up calibration and pull-down calibration, respectively.
[0034] Taking the pull-up calibration process as an example, the pull-up code PU[5:0] generated by the ZQ calibration circuit controls a PMOS group that needs to be calibrated. The voltage Vzq of the PMOS group and the external resistor Rt is compared with the reference voltage Vref, and the output signal DZQHITPT is generated. The signal DZQHITPT controls the pull-up code PU[5:0] to increase or decrease until the voltage Vzq of the PMOS group and the external resistor Rt is consistent with the reference voltage Vref.
[0035] During the ZQ calibration process, the pull-up resistors are calibrated first, followed by the pull-down resistors. That is, the pull-up code PU[5:0] is determined first, and then the pull-down calibration process is started. Since the code of the pull-up PMOS group in the pull-down calibration loop is the same as the determined pull-up code PU[5:0], the pull-down code PD[5:0] can be directly adjusted. The voltage division Vp of the pull-up and pull-down resistors is compared with the reference voltage Vref to obtain the output signal DZQHITNT. The signal DZQHITNT controls the pull-down code PD[5:0] to increase or decrease until the voltage division Vp of the pull-up and pull-down resistors is consistent with the reference voltage Vref.
[0036] Two comparators are used in the whole ZQ calibration process, and the two comparators are inconsistent in performance due to the self bias of the two comparators and the mismatch between the two comparators. For example, in the pull-up calibration process, when Vzq-Vref>10mv, the signal DZQHITPT output by the comparator is high, and at this time the resistance value of the pull-up resistor is less than 240Ω. At the same time, in the pull-down calibration process, when Vp-Vref<10mv, the signal DZQHITNT output by the comparator is high, and at this time the resistance value of the pull-down resistor is less than the resistance value of the pull-up resistor, so that the resistance value of the pull-down resistor is less than the resistance value of the pull-up resistor, and the resistance value of the pull-up resistor is less than 240Ω, thereby affecting the accuracy of ZQ calibration.
[0037] Therefore, the present disclosure provides a ZQ calibration circuit, which comprises a calibration module and a single comparator. The pull-up output end of the calibration module is connected to the control end of a pull-up resistor. The pull-down output end of the calibration module is connected to the control end of a pull-down resistor. The input end of the calibration module is connected to the output end of the comparator. The first connection point of the pull-up resistor and an external resistor and the second connection point of the pull-up resistor and the pull-down resistor are connected to the first input end of the comparator. The second input end of the comparator is used to receive a reference voltage. In the pull-up calibration process, the comparator can compare the voltage at the first connection point with the reference voltage and output a pull-up comparison signal. The calibration module can calibrate the pull-up resistor according to the pull-up comparison signal. In the pull-down calibration process, the comparator can compare the voltage at the second connection point with the reference voltage and output a pull-down comparison signal. The calibration module can calibrate the pull-down resistor according to the pull-down comparison signal. The single comparator can be used to perform pull-up calibration and pull-down calibration in different time periods to realize complete ZQ calibration. The influence of the self bias of the two comparators and the mismatch between the two comparators can be avoided to improve the accuracy of ZQ calibration. In addition, the number of comparators can be reduced to reduce the layout area.
[0038] The technical solutions provided by the present disclosure will be described in detail below with reference to several specific embodiments.
[0039] Figure 3 A circuit schematic diagram of a ZQ calibration circuit provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 3 As shown in FIG. 1, the ZQ calibration circuit comprises a calibration module 110 and a single comparator CMP. The pull-up output end of the calibration module 110 is connected to the control end of a pull-up resistor 210. The pull-down output end of the calibration module 110 is connected to the control end of a pull-down resistor 220. The input end of the calibration module 110 is connected to the output end of the comparator CMP. The first connection point A of the pull-up resistor 210 and an external resistor Rt and the second connection point B of the pull-up resistor 210 and the pull-down resistor 220 are connected to the first input end of the comparator CMP. The second input end of the comparator CMP is used to receive a reference voltage Vref.
[0040] The comparator CMP is configured to compare the first connection point voltage VA with the reference voltage Vref during the pull-up calibration process and output the pull-up comparison signal ZQCMPPU; and to compare the second connection point voltage VB with the reference voltage Vref during the pull-down calibration process and output the pull-down comparison signal ZQCMPPD. The pull-up calibration is completed before the pull-down calibration is performed.
[0041] The calibration module 110 is configured to calibrate the pull-up resistor 210 according to the pull-up comparison signal ZQCMPPU during the pull-up calibration process, and to calibrate the pull-down resistor 220 according to the pull-down comparison signal ZQCMPPD during the pull-down calibration process.
[0042] For example, such as Figure 3 As shown, the calibration module 110 includes a logic control unit 111, a pull-up calibration unit 112, and a pull-down calibration unit 113. The pull-up output terminal of the logic control unit 111 is connected to the enable terminal of the pull-up calibration unit 112, and the pull-down output terminal of the logic control unit 111 is connected to the enable terminal of the pull-down calibration unit 113. The output terminal of the pull-up calibration unit 112 is connected to the control terminal of the pull-up resistor 210, and the input terminal of the pull-up calibration unit 112 is connected to the output terminal of the comparator CMP. The output terminal of the pull-down calibration unit 113 is connected to the control terminal of the pull-down resistor 220, and the input terminal of the pull-down calibration unit 113 is connected to the output terminal of the comparator CMP.
[0043] See also Figure 3 The ZQ calibration circuit also includes a comparison control module 120. The first input terminal of the comparison control module 120 is connected to the first connection point A, the second input terminal of the comparison control module 120 is connected to the second connection point B, the output terminal of the comparison control module 120 is connected to the first input terminal of the comparator CMP, the first control terminal of the comparison control module 120 is connected to the enable terminal of the pull-up calibration unit 112, and the second control terminal of the comparison control module 120 is connected to the enable terminal of the pull-down calibration unit 113.
[0044] The ZQ calibration circuit also includes an output control module 130. The input terminal of the output control module 130 is connected to the output terminal of the comparator CMP. The control terminal of the output control module 130 is connected to the enable terminal of the pull-down calibration unit 113. The pull-up output terminal of the output control module 130 is connected to the input terminal of the pull-up calibration unit 112. The pull-down output terminal of the output control module 130 is connected to the input terminal of the pull-down calibration unit 113.
[0045] The logic control unit 111 can generate a pull-up control signal ZQPU and a pull-down control signal ZQPD, wherein the pull-up control signal ZQPU includes a pull-up calibration enable signal ZQPU_EN and a pull-up calibration disable signal ZQPU_DIS, and the pull-down control signal ZQPD includes a pull-down calibration enable signal ZQPD_EN and a pull-down calibration disable signal ZQPD_DIS. When the logic control unit 111 receives a ZQ calibration command, in response to the ZQ calibration command, the pull-up calibration enable signal ZQPU_EN and the pull-down calibration disable signal ZQPD_DIS are generated to start the pull-up calibration.
[0046] The comparison control module 120 turns on the first input end of the comparator CMP according to the pull-up calibration enable signal ZQPU_EN, the comparator CMP can receive the first connection point voltage VA, and compares the size of the first connection point voltage VA and the reference voltage Vref, and outputs the pull-up comparison signal ZQCMPPU.
[0047] For example, the first input end of the comparator CMP is a positive input end, and the first input end of the comparator CMP is a negative input end. When the first connection point voltage VA is greater than the reference voltage Vref, the output pull-up comparison signal ZQCMPPU is high. When the first connection point voltage VA is less than or equal to the reference voltage Vref, the output pull-up comparison signal ZQCMPPU is low.
[0048] At this time, the output control module 130 turns on the output end of the comparator CMP and the input end of the pull-up calibration unit 112 according to the pull-down calibration disable signal ZQPD_DIS, and the pull-up calibration unit 112 can receive the pull-up comparison signal ZQCMPPU. The pull-up calibration unit 112 starts the pull-up calibration in response to the pull-up calibration enable signal ZQPU_EN, and calibrates the pull-up resistor 210 according to the pull-up comparison signal ZQCMPPU.
[0049] For example, when the pull-up comparison signal ZQCMPPU is high, the pull-up calibration unit 112 increases the resistance value of the pull-up resistor 210 until the pull-up comparison signal ZQCMPPU flips to low. The pull-up calibration unit 112 reduces the resistance value of the pull-up resistor 210, and repeats the above steps until the number of pull-up comparison signal ZQCMPPU flips reaches a preset number of times, and the pull-up calibration is completed.
[0050] After the pull-up calibration is completed, the logic control unit 111 generates the pull-up calibration disable signal ZQPU_DIS and the pull-down calibration enable signal ZQPD_EN to start the pull-down calibration.
[0051] The comparison control module 120 turns on the first input terminal of the comparator CMP according to the pull-down calibration enable signal ZQPD EN, the comparator CMP can receive the second connection point voltage VB, and compare the size of the second connection point voltage VB and the reference voltage Vref, and output the pull-down comparison signal ZQCMP PD.
[0052] For example, the first input terminal of the comparator CMP is a positive input terminal, the first input terminal of the comparator CMP is a negative input terminal, when the second connection point voltage VB is greater than the reference voltage Vref, the output pull-down comparison signal ZQCMP PD is high, when the second connection point voltage VB is less than or equal to the reference voltage Vref, the output pull-down comparison signal ZQCMP PD is low.
[0053] At this time, the output control module 130 turns on the output terminal of the comparator CMP and the input terminal of the pull-down calibration unit 113 according to the pull-down calibration enable signal ZQPD EN, and the pull-down calibration unit 113 can receive the pull-down comparison signal ZQCMP PD. The pull-down calibration unit 113 starts the pull-down calibration in response to the pull-down calibration enable signal ZQPD EN, and calibrates the pull-down resistance 220 according to the pull-down comparison signal ZQCMP PD.
[0054] For example, when the pull-down comparison signal ZQCMP PD is high, the pull-down calibration unit 113 reduces the resistance value of the pull-down resistance 220 until the pull-down comparison signal ZQCMP PD flips to low, the pull-down calibration unit 113 increases the resistance value of the pull-down resistance 220, and repeats the above steps until the pull-down comparison signal ZQCMP PD flips the preset number of times, and the pull-down calibration is completed.
[0055] In this way, the pull-up calibration and the pull-down calibration can be performed in time periods by a single comparator CMP to realize complete ZQ calibration, which can avoid the influence of the deviation of the two comparators and the mismatch between the two comparators, improve the accuracy of ZQ calibration, and reduce the number of comparators CMP, thereby reducing the layout area.
[0056] In some embodiments, continuing to refer to Figure 3 The comparison control module 120 includes a first switch K1 and a second switch K2, wherein the first end of the first switch K1 is connected to the first connection point A, the second end of the first switch K1 is connected to the first input terminal of the comparator CMP, the control end of the first switch K1 is connected to the enable end of the pull-up calibration unit 112, the first end of the second switch K2 is connected to the second connection point B, the second end of the second switch K2 is connected to the first input terminal of the comparator CMP, and the control end of the second switch K2 is connected to the enable end of the pull-down calibration unit 113.
[0057] Exemplarily, during the pull-up calibration process, the logic control unit 111 outputs a pull-up calibration enable signal ZQPU_EN and a pull-down calibration disable signal ZQPD_DIS, the first switch K1 is in a conducting state under the action of the pull-up calibration enable signal ZQPU_EN, and the second switch K2 is in an off state under the action of the pull-down calibration disable signal ZQPD_DIS.
[0058] At this time, the first switch K1 can conduct the first connection point A and the first input end of the comparator CMP, and the second switch K2 can disconnect the connection between the second connection point B and the first input end of the comparator CMP, so that the comparator CMP can compare the first connection point voltage VA with the reference voltage Vref.
[0059] During the pull-down calibration process, the logic control unit 111 outputs a pull-up calibration disable signal ZQPU_DIS and a pull-down calibration enable signal ZQPD_EN, the first switch K1 is in an off state under the action of the pull-up calibration disable signal ZQPU_DIS, and the second switch K2 is in a conducting state under the action of the pull-down calibration enable signal ZQPD_EN.
[0060] At this time, the second switch K2 can conduct the second connection point B and the first input end of the comparator CMP, and the first switch K1 can disconnect the connection between the first connection point A and the first input end of the comparator CMP, so that the comparator CMP can compare the second connection point voltage VB with the reference voltage Vref.
[0061] In some embodiments, continuing to refer to Figure 3 , the output control module 130 includes a demultiplexer Demux, an input end of the demultiplexer Demux is connected to an output end of the comparator CMP, a control end of the demultiplexer Demux is connected to an enable end of the pull-down calibration unit 112, a first output end of the demultiplexer Demux is connected to an input end of the pull-up calibration unit 112, and a second output end of the demultiplexer Demux is connected to an input end of the pull-down calibration unit 113.
[0062] Exemplarily, during the pull-up calibration process, the logic control unit 111 outputs a pull-down calibration disable signal ZQPD_DIS, and the demultiplexer Demux conducts the input end of the demultiplexer Demux and the first output end of the demultiplexer Demux, i.e., conducts the output end of the comparator CMP and the input end of the pull-up calibration unit 112, under the action of the pull-down calibration disable signal ZQPD_DIS.
[0063] In the pull-down calibration process, the logic control unit 111 outputs a pull-down calibration enable signal ZQPD_EN, and the demultiplexer Demux is turned on under the action of the pull-down calibration enable signal ZQPD_EN, that is, the input end of the demultiplexer Demux and the second output end of the demultiplexer Demux are turned on, and the output end of the comparator CMP and the input end of the pull-down calibration unit 113 are turned on.
[0064] In some embodiments, continuing to refer to Figure 3 The pull-up calibration unit 112 includes a pull-up calibration counter Counter_PU, the enable end of the pull-up calibration counter Counter_PU is connected to the pull-up output end of the logic control unit 111, the output end of the pull-up calibration counter Counter_PU is connected to the control end of the pull-up resistor 210, and the input end of the pull-up calibration counter Counter_PU is connected to the pull-up output end of the output control module 130.
[0065] For example, in the pull-up calibration process, the logic control unit 111 outputs a pull-up calibration enable signal ZQPU_EN, the pull-up calibration counter Counter_PU starts to work, and outputs a pull-up code according to the pull-up comparison signal ZQCMPPU to adjust the resistance of the pull-up resistor 210, so that the first connection point voltage VA is approximately equal to the reference voltage Vref, that is, the resistance of the pull-up resistor 210 is approximately equal to the resistance of the external resistor Rt, for example, the resistance of the pull-up resistor 210 is approximately equal to 240Ω.
[0066] In some embodiments, continuing to refer to Figure 3 The pull-down calibration unit 113 includes a pull-down calibration counter Counter_PD, the enable end of the pull-down calibration counter Counter_PD is connected to the pull-down output end of the logic control unit 111, the output end of the pull-down calibration counter Counter_PD is connected to the control end of the pull-down resistor 220, and the input end of the pull-down calibration counter Counter_PD is connected to the pull-down output end of the output control module 130.
[0067] For example, in the pull-down calibration process, the logic control unit 111 outputs a pull-down calibration enable signal ZQPD_EN, the pull-down calibration counter Counter_PD starts to work, and outputs a pull-down code according to the pull-down comparison signal ZQCMPPD to adjust the resistance of the pull-down resistor 220, so that the second connection point voltage VB is approximately equal to the reference voltage Vref, that is, the resistance of the pull-down resistor 220 is approximately equal to the resistance of the pull-up resistor 210, for example, the resistance of the pull-down resistor 220 is approximately equal to 240Ω.
[0068] The embodiments of the present disclosure also provide a semiconductor memory, which includes the pull-up resistor 210, the pull-down resistor 220, and the ZQ calibration circuit provided by any of the above embodiments.
[0069] As shown in Figure 3 The pull-up resistor 210 includes a first pull-up resistor 211 and a second pull-up resistor 212. The first pull-up resistor 211 and an external resistor Rt are connected in series between the power supply VDD and the ground. The second pull-up resistor 212 and the pull-down resistor 220 are connected in series between the power supply VDD and the ground. A connection point of the first pull-up resistor 211 and the external resistor Rt is a first connection point A. A connection point of the second pull-up resistor 212 and the pull-down resistor 220 is a second connection point B. Control ends of the first pull-up resistor 211 and the second pull-up resistor 212 are connected to the pull-up output end of the calibration module 110.
[0070] In the pull-up calibration process, the comparator CMP can compare the first connection point voltage VA and the reference voltage Vref, and obtain a pull-up comparison signal ZQCMPPU. The pull-up calibration unit 112 calibrates the first pull-up resistor 211 and the second pull-up resistor 212 according to the pull-up comparison signal ZQCMPPU. The first pull-up resistor 211 is in the pull-up calibration loop, and the second pull-up resistor 212 is in the pull-down calibration loop.
[0071] When the calibration of the first pull-up resistor 211 is completed, the calibration of the second pull-up resistor 212 in the pull-down calibration loop is also completed, and the resistance value of the first pull-up resistor 211 is equal to the resistance value of the second pull-up resistor 212. Subsequently, the pull-down calibration is started. In the pull-down calibration process, the comparator CMP can compare the second connection point voltage VB and the reference voltage Vref, and obtain a pull-down comparison signal ZQCMPPD. The pull-down calibration unit 113 calibrates the pull-down resistor 220 in the pull-down calibration loop according to the pull-down comparison signal ZQCMPPD.
[0072] The semiconductor memory provided by the embodiments of the present disclosure includes the ZQ calibration circuit provided by any of the above embodiments, and has the functional modules and beneficial effects of the ZQ calibration circuit, which will not be described herein.
[0073] Unless the context clearly indicates otherwise, the use of the singular form of a word in this text and the appended claims includes the plural, and vice versa. Thus, when referring to a singular, the plural is generally included. Similarly, the words “comprise” and “include” are to be interpreted as inclusive rather than exclusive. Likewise, the terms “comprise” and “or” should be interpreted as inclusive, unless expressly forbidden herein. Where the term “example” is used in this text, especially after the term “such as”, the “example” is merely an example and is illustrative, and should not be considered as exclusive or exhaustive.
[0074] Further aspects and ranges of adaptation become apparent from the description provided herein. It should be understood that various aspects of the application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present application.
[0075] The above detailed description of several embodiments of the disclosure has been presented for the purposes of illustration and description. It is apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is defined by the appended claims.
Claims
1. A ZQ calibration circuit, characterized by, The calibration module and a single comparator are included. The pull-up output end of the calibration module is connected to the control end of a pull-up resistor, the pull-down output end of the calibration module is connected to the control end of a pull-down resistor, the input end of the calibration module is connected to the output end of the comparator, the first connection point of the pull-up resistor and an external resistor and the second connection point of the pull-up resistor and the pull-down resistor are connected to the first input end of the comparator, and the second input end of the comparator is used to receive a reference voltage. The comparator is configured to compare the first connection point voltage with the reference voltage and output a pull-up comparison signal in the process of pull-up calibration, and compare the second connection point voltage with the reference voltage and output a pull-down comparison signal in the process of pull-down calibration; and after the pull-up calibration is completed, the pull-down calibration is entered. The calibration module is configured to calibrate the pull-up resistor according to the pull-up comparison signal in the process of the pull-up calibration, and calibrate the pull-down resistor according to the pull-down comparison signal in the process of the pull-down calibration. The calibration module includes a logic control unit, a pull-up calibration unit and a pull-down calibration unit.
2. The ZQ calibration circuit of claim 1, wherein, The pull-up output end of the logic control unit is connected to the enable end of the pull-up calibration unit, the pull-down output end of the logic control unit is connected to the enable end of the pull-down calibration unit, the output end of the pull-up calibration unit is connected to the control end of the pull-up resistor, the input end of the pull-up calibration unit is connected to the output end of the comparator, the output end of the pull-down calibration unit is connected to the control end of the pull-down resistor, and the input end of the pull-down calibration unit is connected to the output end of the comparator. The logic control unit is configured to generate a pull-up calibration enable signal and a pull-down calibration non-enable signal in response to a ZQ calibration command, and generate a pull-up calibration non-enable signal and a pull-down calibration enable signal after the pull-up calibration is completed. The pull-up calibration unit is configured to calibrate the pull-up resistor according to the pull-up comparison signal in response to the pull-up calibration enable signal. The pull-down calibration unit is configured to calibrate the pull-down resistor according to the pull-down comparison signal in response to the pull-down calibration enable signal. The ZQ calibration circuit further includes a comparison control module.
3. The ZQ calibration circuit of claim 2, wherein, The first input end of the comparison control module is connected to the first connection point, the second input end of the comparison control module is connected to the second connection point, the output end of the comparison control module is connected to the first input end of the comparator, the first control end of the comparison control module is connected to the enable end of the pull-up calibration unit, and the second control end of the comparison control module is connected to the enable end of the pull-down calibration unit. The comparison control module is configured to turn on the first connection point and the first input end of the comparator according to the pull-up calibration enable signal, and turn on the second connection point and the first input end of the comparator according to the pull-down calibration enable signal. The comparison control module includes a first switch and a second switch.
4. The ZQ calibration circuit of claim 3, wherein, The first end of the first switch is connected to the first connection point, the second end of the first switch is connected to the first input end of the comparator, and the control end of the first switch is connected to the enable end of the pull-up calibration unit. The first end of the second switch is connected to the second connection point, the second end of the second switch is connected to the first input end of the comparator, and the control end of the second switch is connected to the enable end of the pull-down calibration unit.
5. The ZQ calibration circuit of claim 2, wherein, The ZQ calibration circuit further comprises an output control module; The input end of the output control module is connected to the output end of the comparator, the control end of the output control module is connected to the enable end of the pull-down calibration unit, the pull-up output end of the output control module is connected to the input end of the pull-up calibration unit, and the pull-down output end of the output control module is connected to the input end of the pull-down calibration unit. The output control module is configured to turn on the output end of the comparator and the input end of the pull-up calibration unit according to the pull-down calibration non-enable signal, and turn on the output end of the comparator and the input end of the pull-down calibration unit according to the pull-down calibration enable signal.
6. The ZQ calibration circuit of claim 5, wherein, The output control module comprises a demultiplexer. The input end of the demultiplexer is connected to the output end of the comparator, the control end of the demultiplexer is connected to the enable end of the pull-down calibration unit, the first output end of the demultiplexer is connected to the input end of the pull-up calibration unit, and the second output end of the demultiplexer is connected to the input end of the pull-down calibration unit.
7. The ZQ calibration circuit of claim 5, wherein, The pull-up calibration unit comprises a pull-up calibration counter. The enable end of the pull-up calibration counter is connected to the pull-up output end of the logic control unit, the output end of the pull-up calibration counter is connected to the control end of the pull-up resistor, and the input end of the pull-up calibration counter is connected to the pull-up output end of the output control module.
8. The ZQ calibration circuit of claim 5, wherein, The pull-down calibration unit comprises a pull-down calibration counter. The enable end of the pull-down calibration counter is connected to the pull-down output end of the logic control unit, the output end of the pull-down calibration counter is connected to the control end of the pull-down resistor, and the input end of the pull-down calibration counter is connected to the pull-down output end of the output control module.
9. A semiconductor memory, characterized by comprising: The pull-up resistor, the pull-down resistor, and the ZQ calibration circuit of any one of claims 1-8 are included.
10. The semiconductor memory according to claim 9, wherein The pull-up resistor comprises a first pull-up resistor and a second pull-up resistor. The first pull-up resistor and the external resistor are connected in series between a power supply and ground, the second pull-up resistor and the pull-down resistor are connected in series between the power supply and ground, a connection point of the first pull-up resistor and the external resistor is the first connection point, a connection point of the second pull-up resistor and the pull-down resistor is the second connection point, and the control end of the first pull-up resistor and the control end of the second pull-up resistor are connected to the pull-up output end of the calibration module.