Chip and electronic equipment
By employing an interconnect layer structure with alternating stacked metal pattern layers and dielectric layers in the chip, the problem of impedance mismatch in signal transmission paths is solved, thereby improving signal integrity.
Patent Information
- Application Number
- CN202423285753.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-30
AI Technical Summary
In existing chip packaging, the large diameter of the core layer drill hole leads to impedance mismatch in the signal transmission path, resulting in significant return loss and affecting signal integrity.
An interconnect layer structure with alternating stacked metal patterned layers and dielectric layers is adopted. The die is accommodated by a cavity on the support plate and fixed by an adhesive layer. The signal is transmitted through the interconnect layer, avoiding the transmission of signals in the core layer and improving impedance consistency.
It effectively reduces signal return loss, improves signal integrity, and enhances signal transmission quality.
Smart Images
Figure CN223728778U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit packaging technical field especially, a kind of chip and electronic equipment. BACKGROUND
[0002] With the continuous improvement of chip performance such as CPU (central processing unit) and GPU (graphics processing unit), the signal transmission rate is also getting faster and faster. Consequently, chip packaging faces great challenges, and needs to realize high-speed signal interconnection in limited space.
[0003] In related technologies, the packaging substrate of chip packaging is mostly supported by a core layer, and a stack layer is formed on both sides of the core layer for signal transmission. The signals on one side of the core layer need to be transmitted to the other side of the core layer through the drill holes in the core layer. Since the diameter of the drill holes in the core layer is relatively large, impedance mismatching may occur in the signal transmission path, resulting in a large echo loss of the signals, which seriously affects the signal integrity. SUMMARY
[0004] Therefore, the utility model embodiment provides a chip and electronic equipment, which can effectively reduce the echo loss of signals and improve signal integrity.
[0005] In a first aspect, the utility model embodiment provides a chip, which includes a die, a support plate and an interconnection layer arranged in sequence; the support plate is provided with a cavity for accommodating the die, and the opening direction of the cavity is toward the interconnection layer; the interconnection layer includes alternately stacked metal pattern layers and dielectric layers, wherein the opening of the cavity exposes the metal pattern layers, and the exposed metal pattern layers are coupled to the die; the chip further includes an adhesive layer arranged on the surface of the cavity, and the adhesive layer is used to fix the die to the surface of the cavity.
[0006] In an embodiment, the die includes a first surface and a second surface, and the first surface is opposite to the second surface; the first surface is coupled to the interconnection layer, and the second surface abuts against the bottom of the cavity.
[0007] In an embodiment, the second surface of the die is provided with a heat-conducting layer.
[0008] In an embodiment, the metal pattern layer includes a first layer of metal pattern layer, and the first layer of metal pattern layer is located on the surface of the support plate; the first layer of metal pattern layer includes a plurality of first metal contacts, and the opening of the cavity exposes the plurality of first metal contacts.
[0009] In an embodiment, the metal pattern layer of the first layer further comprises a metal pattern portion, wherein a width of the metal pattern portion is greater than a width of the first metal contact.
[0010] In an embodiment, the first metal contact comprises a metal bump.
[0011] In an embodiment, the metal pattern layer comprises a last metal pattern layer of the metal pattern layers, the last metal pattern layer being located on a surface of a dielectric layer away from the metal pattern layer of the first layer; the last metal pattern layer comprises a plurality of second metal contacts.
[0012] In an embodiment, the second metal contact comprises a solder pad.
[0013] In an embodiment, each of the dielectric layers comprises a conductive via, and different metal pattern layers are coupled through corresponding conductive vias.
[0014] In an embodiment, the number of the cavities is at least two; the chip further comprises a package substrate, and the interconnection layer serves as an interposer between the die and the package substrate, and is coupled to the die and the package substrate, respectively.
[0015] In a second aspect, an embodiment of the utility model further provides an electronic device, which is characterized by comprising a printed circuit board and any one of the chips provided by the embodiments of the utility model, wherein the chip is arranged on the printed circuit board. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the utility model or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description. Obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.
[0017] Figure 1 A structural schematic diagram of the chip provided by the embodiment of the utility model is shown in the figure.
[0018] Figure 2 Another structural schematic diagram of the chip provided by the embodiment of the utility model is shown in the figure.
[0019] Figure 3 Still another structural schematic diagram of the chip provided by the embodiment of the utility model is shown in the figure.
[0020] Figure 4 Still another structural schematic diagram of the chip provided by the embodiment of the utility model is shown in the figure.
[0021] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0022] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings.
[0023] It should be understood that the described embodiments are merely some embodiments of this utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.
[0024] This invention provides a chip that can effectively reduce signal return loss and improve signal integrity.
[0025] like Figure 1 As shown, the chip 4 provided in the embodiment of this utility model may include a die 101 and a support plate 116 and an interconnect layer 103 arranged sequentially; the support plate 116 is provided with a cavity 120 for accommodating the die 101, and the opening of the cavity 120 faces the interconnect layer 103; the interconnect layer 103 includes alternating stacked metal pattern layers 114 and dielectric layers 110, wherein the opening of the cavity 120 exposes the metal pattern layers 114, and the exposed metal pattern layers 114 couple the die 101; the chip 4 may also include an adhesive layer 122 disposed on the surface of the cavity 120, the adhesive layer 122 being used to fix the die 101 to the surface of the cavity 120.
[0026] The chip 4 provided in this embodiment of the present invention has a cavity 120 on a support plate 116 for accommodating a die 101. The die 101 is fixed to the surface of the cavity 120 by an adhesive layer 122, thereby receiving support from the support plate 116. The opening of the cavity 120 faces the interconnect layer 103. The interconnect layer 103 includes alternating stacked metal pattern layers 114 and dielectric layers 110. The opening of the cavity 120 exposes the metal pattern layers 114, which couple to the die 101. In this way, the signal in the die 101 can enter the interconnect layer 103 and be transmitted through the metal pattern layers 114 spaced apart by the dielectric layers 110 in the interconnect layer 103. The entire chip 4 has no core layer, and there is no situation where the signal is transmitted from one side of the core layer to the other side. Therefore, it can greatly improve the impedance consistency in the signal transmission line, effectively reduce the signal return loss, and improve signal integrity.
[0027] In an embodiment of the present application, the support plate 116 mainly supports the interconnection layer 103 and does not participate in signal transmission, thus, as long as the plate material with hardness and strength meeting the support requirement can be used as the support plate 116. For example, in an embodiment of the present application, the support plate 116 can include any one of the following: a resin plate, a glass plate, and a ceramic plate.
[0028] In an embodiment of the present application, the support plate 116 can be provided with a cavity 120, and the specific position of the cavity 120 on the support plate 116 is not limited, as long as the support effect of the support plate 116 on the interconnection layer 103 is not affected. For example, in one example, the cavity 120 can be located at the center of the support plate 116.
[0029] The shape and size of the cavity 120 can be adapted to the shape and size of the die 101, so as to place and accommodate the corresponding die 101. Among them, the adaptation means that after the die 101 is placed into the corresponding cavity 120, the die 101 can be coupled with the interconnection layer 103, and excessive space waste is not caused. For example, in one example, the shape of the cavity 120 can be the same as the shape of the die 101, and the size of the cavity 120 can be slightly larger than the die 101, for example, the side length of the cavity 120 can be 1-2 mm larger than the corresponding side length of the die 101.
[0030] In an embodiment of the present application, the die 101 and the inner wall of the cavity 120 can be fixed by an adhesive layer 122, so that the die 101 can be stably combined with the support plate 116. The adhesive layer 122 can be formed by curing adhesive, for example.
[0031] Further, according to the different number of dies 101 to be packaged, the number of cavities 120 in the support plate 116 can also be correspondingly different. For example, in one example, the number of cavities 120 can be one, and in another example, the number of cavities 120 can also be two or more, wherein each cavity 120 is used to place and accommodate one corresponding die 101.
[0032] In an embodiment of the present application, the die 101 can include a first surface and a second surface, and the first surface is opposite to the second surface; wherein the first surface can be coupled with the interconnection layer 103, and the second surface can be in abutment with the bottom of the cavity 120.
[0033] Further, as Figure 2As shown, in another embodiment of the present application, the second surface of the die 101 can also be provided with a heat-conducting layer 121, so that the heat generated by the die 101 during operation can be dissipated more quickly. The specific material of the heat-conducting layer 121 is not limited, as long as it can accelerate the heat conduction between the die 101 and the inner wall of the cavity 120. For example, in one example, the heat-conducting layer 121 can include graphene material or indium material, etc.
[0034] In an embodiment of the present application, the interconnection layer 103 can include alternately stacked metal pattern layers 114 and dielectric layers 110. Among them, the metal pattern layer 114 can be used for signal transmission, and the dielectric layer 110 can be used to insulate and isolate different metal pattern layers 114.
[0035] In a specific implementation, the dielectric layer 110 can include various insulating materials. For example, in one example, the material of the dielectric layer 110 can include polyimide, and in another example, the material of the dielectric layer 110 can include ABF (Ajinomoto Build-up Film). The materials of the dielectric layers 110 can be the same or different, and the embodiments of the present application do not limit this.
[0036] The number of metal pattern layers 114 can be multiple, and according to the different positions of the metal pattern layers 114 in the interconnection layer 103, the specific structures of the metal pattern layers 114 can also be different. Specifically, as shown in Figure 3 As shown, in one embodiment of the present application, the metal pattern layer 114 can include a first layer of metal pattern layer 1141, and the first layer of metal pattern layer 1141 is located on the surface of the support plate 116. The first layer of metal pattern layer 1141 includes a plurality of first metal contacts 21, and the opening of the cavity 120 exposes the plurality of first metal contacts 21. In a specific implementation, the specific form of the first metal contact 21 can be set and adjusted as needed. For example, in one example, the first metal contact 21 can include a metal bump.
[0037] In one embodiment, the first layer of metal pattern layer 1141 can also include a metal pattern portion 23, wherein the width of the metal pattern portion 23 can be greater than the width of the first metal contact 21. The metal pattern portion 23 can be electrically connected with the first metal contact 21, or can not be electrically connected with the first metal contact 21, and the embodiments of the present application do not limit this. In one embodiment, the metal pattern portion 23 can be located in the region of the first layer of metal pattern layer 1141 which is not exposed by the opening 120.
[0038] Again referring to Figure 3In another embodiment of the present application, in addition to the first metal pattern layer 1141, the metal pattern layer 114 can further include a last metal pattern layer 1142, which is located on the surface of the dielectric layer 110 away from the first metal pattern layer 1141. The last metal pattern layer 1142 can include a plurality of second metal contacts 22 for electrically connecting the chip 4 to other components or devices, such as a mainboard. For example, the second metal contacts 22 can include solder pads.
[0039] Further, in addition to the first metal pattern layer 1141 and the second metal pattern layer 1142, in an embodiment of the present application, the metal pattern layer 114 can further include at least one metal wiring layer 1143, which can be located between the first metal pattern layer 1141 and the second metal pattern layer 1142. The metal wiring layer 1143 can be used for redistributing signals in one die 101 or for interconnecting two or more dies 101, and the embodiments of the present application are not limited in this regard.
[0040] In an embodiment of the present application, the metal pattern layers 114, such as the first metal pattern layer 1141, the second metal pattern layer 1142 and the metal wiring layer 1143, can be separated by different dielectric layers 110. Each dielectric layer 110 can include a conductive via 104, and different metal pattern layers 114 can be coupled through corresponding conductive vias 104.
[0041] In the above embodiments, the chip 4 mainly performs signal redistribution or inter-die interconnection through the interconnection layer 103, but the embodiments of the present application are not limited in this regard. In other embodiments of the present application, the chip 4 can further include a package substrate, and further perform signal redistribution or inter-die interconnection through the package substrate, so as to realize 2.5D packaging of the chip 4. For example, as shown in FIG. 6, in an embodiment of the present application, the number of cavities 120 can be at least two; the chip 4 can further include a package substrate 3, and the interconnection layer 103 can be used as an interposer between the dies 101 and the package substrate 3, and coupled to the dies 101 and the package substrate 3, respectively. Figure 4
[0042] Correspondingly, as shown in FIG. 7, in an embodiment of the present application, the number of cavities 120 can be at least two; the chip 4 can further include a package substrate 3, and the interconnection layer 103 can be used as an interposer between the dies 101 and the package substrate 3, and coupled to the dies 101 and the package substrate 3, respectively. Figure 5 The embodiment of the utility model also provides an electronic equipment 5, can include printed circuit board 51 and any kind of chip 4 provided by the preceding embodiment, and the chip 4 is arranged on the printed circuit board 51.
[0043] Since the electronic equipment 5 provided by the embodiment of the utility model includes any kind of chip 4 provided by the preceding embodiment, the corresponding beneficial technical effects can also be achieved, and the foregoing has been described in detail, which will not be repeated here.
[0044] It should be noted that, in this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.
[0045] Each of the embodiments in the specification is described in a relevant manner, and the same or similar parts between each of the embodiments can be referred to each other, and each of the embodiments focuses on the difference from other embodiments.
[0046] The above is merely a specific implementation of the utility model, but the protection scope of the utility model is not limited to this, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the utility model, which should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of the claims.
Claims
1. A chip, characterized by The chip comprises a crystal grain and a support plate and an interconnection layer arranged in sequence; the support plate is provided with a cavity for accommodating the crystal grain, and the opening direction of the cavity is toward the interconnection layer; The interconnection layer comprises metal pattern layers and dielectric layers stacked alternately, wherein the opening of the cavity exposes the metal pattern layer, and the exposed metal pattern layer is coupled with the crystal grain; The chip further comprises an adhesive layer arranged on the surface of the cavity, which is used to fix the crystal grain and the surface of the cavity.
2. The chip according to claim 1, characterized in that, The crystal grain comprises a first surface and a second surface, and the first surface is opposite to the second surface; the first surface is coupled with the interconnection layer, and the second surface is in contact with the bottom of the cavity.
3. The chip of claim 2, wherein, The second surface of the crystal grain is provided with a heat-conducting layer.
4. The chip of claim 1, wherein The metal pattern layer comprises a first layer of metal pattern layer located on the surface of the support plate, and the first layer of metal pattern layer comprises a plurality of first metal contacts exposed by the opening of the cavity.
5. The chip of claim 4, wherein, The first layer of metal pattern layer further comprises a metal pattern part, wherein the width of the metal pattern part is greater than the width of the first metal contact.
6. The chip of claim 4, wherein, The first metal contact comprises a metal bump.
7. The chip of claim 4, wherein, The metal pattern layer comprises a last layer of metal pattern layer located on the surface of the dielectric layer away from the first layer of metal pattern layer; the last layer of metal pattern layer comprises a plurality of second metal contacts.
8. The chip of claim 7, wherein, The second metal contact comprises a solder pad.
9. The chip according to any one of claims 1 to 8, characterized in that, Each of the dielectric layers comprises a conductive via, and different metal pattern layers are coupled through corresponding conductive vias.
10. The chip according to any one of claims 1 to 8, characterized in that, The number of cavities is at least two; the chip further comprises a packaging substrate, and the interconnection layer serves as an interlayer between the crystal grain and the packaging substrate and is coupled with the crystal grain and the packaging substrate respectively.
11. An electronic device, comprising: The chip comprises a printed circuit board and the chip of any one of claims 1 to 10, and the chip is arranged on the printed circuit board.