BCD device
By introducing a first dielectric layer into the BCD device to raise the gate electrode layer, the surface electric field is reduced, which solves the reliability problem of the BCD device under complex operating conditions and improves the stability and lifespan of the device.
Patent Information
- Application Number
- CN202423320860.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing BCD devices lack reliability under complex operating conditions, especially the HCI effect of field-mounted MOS structures, which affects the stability and lifespan of the devices.
Introducing a first dielectric layer into a BCD device raises the edge region of the first gate electrode layer and reduces the surface electric field of the first well region, thereby reducing the hot carrier injection effect and improving device reliability.
By introducing a first dielectric layer compatible with BCD technology, the surface electric field of the BCD device is reduced, the device reliability is improved, and the cost is lower.
Smart Images
Figure CN223730191U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor technical field especially relates to a BCD device. BACKGROUND
[0002] BCD (Bipolar-CMOS-DMOS) process is a commonly used process for power integrated circuits. This process can integrate multiple different types of device structures on the same wafer through a production process, including resistors, capacitors, diodes, transistors, and various MOS devices, making power integrated circuit design more flexible, increasing integration, and significantly reducing costs.
[0003] BCD devices can include Field-MOS (Field-MOS, Field-Metal Oxide Semiconductor Transistor) structures. This structure has good compatibility with Bipolar and CMOS processes and is a very important type of device structure in BCD devices. To meet the increasingly complex working conditions and stringent verification, the reliability of the Field-MOS structure must be further optimized. SUMMARY
[0004] The utility model aims at providing a kind of BCD device, for improving the reliability of existing BCD device.
[0005] To achieve the above purpose, the utility model provides a kind of BCD device, comprising:
[0006] Substrate;
[0007] First well region, extending downward from the surface of substrate;
[0008] At least one ohmic contact region, the ohmic contact region extends downward from the surface of first well region;
[0009] First gate oxide layer, located on the top surface of the part of first well region outside ohmic contact region;
[0010] First dielectric layer, located on at least part of the top surface of first gate oxide layer;And
[0011] Second gate electrode layer, located on at least part of the top surface of second dielectric layer.
[0012] Optionally, the first dielectric layer is located on the edge region of the top surface of the first gate oxide layer, and the first gate electrode layer is located on the remaining region of the top surface of the first dielectric layer and the first gate oxide layer.
[0013] Optionally, the first dielectric layer is located on the entire top surface of the first gate oxide layer, and the first gate electrode layer is located on the entire top surface of the first dielectric layer.
[0014] Optionally, the first dielectric layer is a nitride layer; or, the first dielectric layer is a stack of a nitride layer and an oxide layer.
[0015] Optionally, the first dielectric layer has a thickness of 10-1000 nm.
[0016] Optionally, the first dielectric layer has a thickness of 10-1000 nm.
[0017] Optionally, the ohmic contact region includes a first ohmic contact region, a second ohmic contact region and a third ohmic contact region, extending from the top surface of the substrate into the first well region, the first ohmic contact region and the second ohmic contact region are located at a first side of the first gate oxide layer, the first ohmic contact region and the second ohmic contact region are adjacent, the second ohmic contact region contacts the first side of the first gate oxide layer, the third ohmic contact region is located at a second side of the first gate oxide layer, the third ohmic contact region contacts the second side of the first gate oxide layer, the first ohmic contact region has the same doping type as the first well region, the second ohmic contact region and the third ohmic contact region have the opposite doping type as the first well region.
[0018] a first insulating layer covering the first ohmic contact region, the second ohmic contact region, the first gate oxide layer, the third ohmic contact region, the edge portion of the first well region and the portion of the substrate without the edge portion, the first gate oxide layer and the first dielectric layer are below the first insulating layer, the first insulating layer has an opening, the first insulating layer has a first interconnection structure, a second interconnection structure, a third interconnection structure and a fourth interconnection structure in the opening of the first insulating layer, the first interconnection structure, the second interconnection structure and the third interconnection structure are respectively interconnected with the first ohmic contact region, the second ohmic contact region and the third ohmic contact region, the fourth interconnection structure is interconnected with the first gate electrode layer.
[0019] Optionally, the semiconductor device further includes:
[0020] a second well region extending from the top surface of the substrate into the substrate;
[0021] the ohmic contact region extends downward from the surface of the second well region;
[0022] a second gate oxide layer located at the top surface of the portion of the second well region other than the ohmic contact region;
[0023] a second dielectric layer located at the second gate oxide layer; and
[0024] a second gate electrode layer located at at least a portion of the top surface of the second dielectric layer.
[0025] Optionally, the second dielectric layer is located on the whole top surface of the second gate oxide layer, and the second gate electrode layer is located on the whole top surface of the second dielectric layer.
[0026] Optionally, the BCD device further comprises:
[0027] The first isolation structure and the second isolation structure extend from the top surface of the substrate into the second well region and are located on two sides of the second gate oxide layer, respectively.
[0028] Optionally, the top surface of the first isolation structure and the second isolation structure is flush with the top surface of the substrate, or the top surface of the first isolation structure and the second isolation structure is higher than the top surface of the substrate.
[0029] Optionally, the first isolation structure and the second isolation structure are field oxide layers or trench isolation structures.
[0030] Optionally, the second dielectric layer is a nitride layer, or the second dielectric layer is a stack of a nitride layer and an oxide layer.
[0031] Optionally, the thickness of the second dielectric layer is 10-100 nm.
[0032] Optionally, the thickness of the second dielectric layer is 10-100 nm.
[0033] Optionally, the ohmic contact region comprises a fourth ohmic contact region and a fifth ohmic contact region, which extend from the top surface of the substrate into the second well region, the fourth ohmic contact region and the fifth ohmic contact region are located on two sides of the second gate oxide layer, respectively, the fourth ohmic contact region and the fifth ohmic contact region are in contact with the two sides of the second gate oxide layer, respectively, and the fourth ohmic contact region and the fifth ohmic contact region have the same doping type as the second well region.
[0034] The second insulating layer covers the fourth ohmic contact region, the first isolation structure, the second gate electrode layer, the second isolation structure, the fifth ohmic contact region, and the second well edge and the substrate edge, the second gate oxide layer and the second dielectric layer are below the second insulating layer, the second insulating layer has an opening, the fifth interconnection structure, the sixth interconnection structure, and the seventh interconnection structure are led out from the opening of the second insulating layer, the fifth interconnection structure and the sixth interconnection structure are interconnected with the fourth ohmic contact region and the fifth ohmic contact region, respectively, and the seventh interconnection structure is interconnected with the second gate electrode layer.
[0035] Optionally, the working voltage of the BCD device is 45-120 V.
[0036] Optionally, the BCD device further comprises:
[0037] A first isolation structure and a second isolation structure extend from the top surface of the substrate into the first well region and are located on two sides of the first gate oxide layer respectively.
[0038] Optionally, the top surface of the first isolation structure and the second isolation structure is flush with the top surface of the substrate, or the top surface of the first isolation structure and the second isolation structure is higher than the top surface of the substrate.
[0039] Optionally, the first isolation structure and the second isolation structure are field oxide layers or trench isolation structures.
[0040] Optionally, the ohmic contact region includes a fourth ohmic contact region and a fifth ohmic contact region, which extend from the top surface of the substrate into the first well region, and the fourth ohmic contact region and the fifth ohmic contact region are located on two sides of the first gate oxide layer respectively, and the fourth ohmic contact region and the fifth ohmic contact region are in contact with the two sides of the first gate oxide layer respectively, and the fourth ohmic contact region and the fifth ohmic contact region are of the same doping type as the second well region.
[0041] A first insulating layer covers the fourth ohmic contact region, the first isolation structure, the first gate electrode layer, the second isolation structure, the fifth ohmic contact region, and the edge of the first well region and the edge of the substrate, and the first gate oxide layer and the first dielectric layer are below the first insulating layer, the first insulating layer has an opening, the fifth interconnection structure, the sixth interconnection structure and the seventh interconnection structure are led out from the opening of the first insulating layer, the fifth interconnection structure and the sixth interconnection structure are interconnected with the fourth ohmic contact region and the fifth ohmic contact region respectively, and the seventh interconnection structure is interconnected with the first gate electrode layer.
[0042] In the BCD device provided by the utility model, the first well region extends downward from the top surface of the substrate, the first gate oxide layer is located on the top surface of the part of the first well region other than the ohmic contact region, the first dielectric layer is located on at least part of the top surface of the first gate oxide layer, and the second gate electrode layer is located on at least part of the top surface of the second dielectric layer. BRIEF DESCRIPTION OF DRAWINGS
[0043] Figure 1 The structure schematic diagram of the BCD device provided by the first embodiment of the utility model;
[0044] Figure 2 This is a schematic diagram of the structure of the BCD device provided in Embodiment 2 of the present invention;
[0045] Figure 3 This is a schematic diagram of the structure of the BCD device provided in Embodiment 3 of the present invention;
[0046] Figure 4 This is a schematic diagram of the structure of the BCD device provided in Embodiment 4 of the present invention;
[0047] Figure 5 This is a schematic diagram of the structure of the BCD device provided in Embodiment 5 of the present invention;
[0048] The attached figures are labeled as follows:
[0049] 100 - Substrate; 101 - First well region; 111 - First ohmic contact region; 121 - Second ohmic contact region; 131 - Third ohmic contact region; 102 - Second well region; 112 - Fourth ohmic contact region; 122 - Fifth ohmic contact region; 210 - First isolation structure; 210 - First isolation structure; 301 - First gate oxide layer; 302 - Second gate oxide layer; 401 - First gate electrode layer; 402 - Second gate electrode layer; 501 - First dielectric layer; 502 - Second dielectric layer; 601 - First insulating layer; 602 - Second insulating layer; 701 - First interconnect structure; 702 - Second interconnect structure; 703 - Third interconnect structure; 704 - Fourth interconnect structure; 705 - Fifth interconnect structure; 706 - Sixth interconnect structure; 707 - Seventh interconnect structure. Detailed Implementation
[0050] The specific embodiments of this utility model will now be described in more detail with reference to the accompanying drawings. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.
[0051] Figure 1 This is a schematic diagram of the BCD device provided in this embodiment. Figure 1 As shown, the BCD device includes a substrate 100 and a field-MOS structure (Field-MOS, field-metal-oxide-semiconductor transistor). The field-MOS structure includes a first well region 101, a first gate oxide layer 301, a first gate electrode layer 401, and a first dielectric layer 501.
[0052] Specifically, the first well region 101 is located within the substrate 100 and extends downward from the top surface of the substrate 100 into the substrate 100. In this embodiment, the substrate 100 has a first doping type, and the first well regions 101 all have a second doping type.
[0053] The first well region 101 has at least one ohmic contact region extending downward from the surface of the first well region 101, the ohmic contact region including a first ohmic contact region 111, a second ohmic contact region 121 and a third ohmic contact region 131, the first ohmic contact region 111, the second ohmic contact region 121 and the third ohmic contact region 131 all extending into the first well region 101 from the top surface of the substrate 100. In this embodiment, the first ohmic contact region 111 has the same doping type as the first well region 101, and the second ohmic contact region 121 and the third ohmic contact region 131 have the opposite doping type to the first well region 101, i.e. the first ohmic contact region 111 has the second doping type, and the second ohmic contact region 121 and the third ohmic contact region 131 have the first doping type.
[0054] Optionally, the first doping type and the second doping type can be N-type and P-type respectively, or P-type and N-type respectively.
[0055] Please continue to refer to Figure 1 The first ohmic contact region 111 and the second ohmic contact region 121 are adjacent to each other, and the second ohmic contact region 121 is in contact with the first side of the first gate oxide layer 301. The first gate oxide layer 301 is located on part of the top surface of the first well region 101, specifically covering the top surface of the first well region 101 between the second ohmic contact region 121 and the third ohmic contact region 131. In this way, the first ohmic contact region 111 and the second ohmic contact region 121 are adjacent to each other and located on the first side of the first gate oxide layer 301, and the third ohmic contact region 131 is located on the second side of the first gate oxide layer 301, and the third ohmic contact region 131 is in contact with the second side of the first gate oxide layer 301.
[0056] Further, the first dielectric layer 501 is located on the first gate oxide layer 301, and the first gate electrode layer 401 is located on the first dielectric layer 501. In this embodiment, the first dielectric layer 501 only covers the edge region of the top surface of the first gate oxide layer 301, and the first gate electrode layer 401 covers the remaining region of the top surface of the first dielectric layer 501 and the first gate oxide layer 301. In the working process of the field MOS structure, one of the second ohmic contact region 121 and the third ohmic contact region 131 applies a high voltage, and the other applies a low voltage. The surface electric field of the first well region 101 is relatively high. The first dielectric layer 501 raises the edge region of the first gate electrode layer 401, thereby reducing the surface electric field of the first well region 101 (the region covered by the first dielectric layer 501, i.e., the region where electric field concentration is likely to occur), improving the reliability of the field MOS structure, and further improving the reliability of the BCD device. Moreover, the first dielectric layer 501 is compatible with the BCD process and has a relatively low manufacturing cost.
[0057] Optionally, the thickness of the first gate electrode layer 401 can be 100-200 nm.
[0058] Further, the material of the first dielectric layer 501 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric capability of the high-k material, the first dielectric layer 501 can effectively reduce the surface electric field of the first well region 101 at a relatively small thickness. The first dielectric layer 501 can be a single-layer structure or a multi-layer structure. For example, the first dielectric layer 501 can be a nitride layer (such as a silicon nitride layer), or a stack of a nitride layer (such as a silicon nitride layer) and an oxide layer (such as a silicon oxide layer, with a thickness of 10-50 nm).
[0059] Further, the thickness of the first dielectric layer 501 can be 10-50 nm. The thickness of the first dielectric layer 501 can be 10-50 nm. However, the above-mentioned ranges are not limiting.
[0060] Please continue to refer to Figure 1 The BCD device further comprises a first insulating layer 601, which completely covers the substrate 100 and the field MOS structure, i.e. covers the first ohmic contact region 111, the second ohmic contact region 121, the first gate oxide layer 301, the third ohmic contact region 131, the edge portion of the first well region 101 and the portion of the substrate 100 without the edge portion, and the first gate electrode layer 401 is below the first insulating layer 601. The first insulating layer 601 has openings, and the first interconnection structure 701, the second interconnection structure 702, the third interconnection structure 703 and the fourth interconnection structure 704 are further formed in the openings of the first insulating layer 601. The first interconnection structure 701, the second interconnection structure 702 and the third interconnection structure 703 are respectively interconnected with the first ohmic contact region 111, the second ohmic contact region 121 and the third ohmic contact region 131, and respectively serve as the body electrode, the source electrode and the drain electrode of the field MOS structure. The fourth interconnection structure 704 is interconnected with the first gate electrode layer 401, and thus serves as the gate electrode of the field MOS structure. The first interconnection structure 701, the second interconnection structure 702, the third interconnection structure 703 and the fourth interconnection structure 704 can each comprise a plug and an interconnection metal layer, the plug is located in the first insulating layer 601, and at least part of the top surface of the interconnection metal layer is exposed to the first insulating layer 601.
[0061] Optionally, the BCD device can be applied to a driving integrated circuit of a power supply and a motor, and the working voltage thereof can be 45V-120V.
[0062] Based on this, the embodiment provides a preparation method of the BCD device, comprising the following steps:
[0063] In step S100, the substrate 100 is provided, ion implantation is performed on the substrate 100 to form the first well region 101, the first well region 101 is then activated at high temperature, and high-temperature annealing is performed on the first well region 101.
[0064] In step S200, the first gate oxide layer 301 is formed on the top surface of the first well region 101.
[0065] In step S300, the first dielectric layer 501 is formed on the edge region of the top surface of the first gate oxide layer 301.
[0066] In step S400, the first gate electrode layer 401 is formed on the first gate oxide layer 301 and the remaining top surface and the first dielectric layer 501.
[0067] Step S500, ion implantation, forming the first ohmic contact region 112, the second ohmic contact region 121 and the third ohmic contact region 131; wherein the first ohmic contact region 111 has the second doping type, the second ohmic contact region 121 and the third ohmic contact region 131 have the first doping type.
[0068] Step S600, forming the first insulating layer 601, the first interconnection structure 701, the second interconnection structure 702, the third interconnection structure 703 and the fourth interconnection structure 704 on the substrate 100.
[0069] Embodiment two
[0070] Figure 2 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 2. As shown in the figure, the difference between the embodiment and the embodiment one is that, in the embodiment, the first gate oxide layer 301 is located on the top surface of the substrate 100, and the first gate electrode layer 401 is located on the first gate oxide layer 301. Figure 2 Since the first gate oxide layer 301 completely covers the first gate oxide layer 301, the gate-source voltage resistance performance can be improved without changing the working voltage of the field MOS structure, and the reliability of the BCD device is improved.
[0071] Embodiment three
[0072] Figure 3 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 3. As shown in the figure, the difference between the embodiment and the embodiment one is that, in the embodiment, the BCD device further comprises a MOS capacitor structure. Figure 3 The MOS capacitor structure comprises a second well region 102, a second gate oxide layer 302, a second gate electrode layer 402 and a second dielectric layer 502, and the ohmic contact region extends downward from the surface of the second well region 102.
[0073] Specifically, the second well region 102 is located in the substrate 100 and extends from the top surface of the substrate 100 to the substrate 100. In the embodiment, the second well region 102 has the second doping type.
[0074] The ohmic contact regions include a fourth ohmic contact region 112 and a fifth ohmic contact region 122, both of which extend from the top surface of the substrate 100 into the second well region 102, and both of which are in contact with both sides of the second gate oxide layer 302, respectively. The fourth ohmic contact region 112 and the fifth ohmic contact region 122 are spaced apart from each other. In this embodiment, the fourth ohmic contact region 112 and the fifth ohmic contact region 122 have a doping type different from that of the second well region 102, i.e., the fourth ohmic contact region 112 and the fifth ohmic contact region 122 have the first doping type.
[0075] Further, the MOS capacitor structure further includes a first isolation structure 210 and a second isolation structure 220, both of which are field oxide layers in this embodiment. The first isolation structure 210 and the second isolation structure 220 extend from the top surface of the substrate 100 into the second well region 102, and further extend upward to be higher than the top surface of the substrate 100, from Figure 3 As can be seen, the top surfaces of the first isolation structure 210 and the second isolation structure 220 are higher than the top surface of the substrate 100. In some embodiments, the top surfaces of the first isolation structure 210 and the second isolation structure 220 can also be flush with the top surface of the substrate 100.
[0076] The first isolation structure 210 and the second isolation structure 220 are both located between the fourth ohmic contact region 112 and the fifth ohmic contact region 122, and are spaced apart from each other. In this embodiment, the end portions of the first isolation structure 210 and the second isolation structure 220 have a beak structure.
[0077] Optionally, the thickness of the first isolation structure 210 and the second isolation structure 220 can be
[0078] Please continue to refer to Figure 3The second gate oxide layer 302 is located on a part of the top surface of the second well region 102, specifically between the first isolation structure 210 and the second isolation structure 220, and covers the top surface of the second well region 102 between the first isolation structure 210 and the second isolation structure 220. In this way, the fourth ohmic contact region 112 and the fifth ohmic contact region 122 are located on both sides of the second gate oxide layer 302, and the fourth ohmic contact region 112 is isolated from the second gate oxide layer 302 by the first isolation structure 210, and the fifth ohmic contact region 122 is isolated from the second gate oxide layer 302 by the second isolation structure 220.
[0079] Further, the second dielectric layer 502 is located on the second gate oxide layer 302, and the second gate electrode layer 402 is located on at least a part of the top surface of the second dielectric layer 502. In this embodiment, the second dielectric layer 502 is located on the entire top surface of the second gate oxide layer 302, and the second gate electrode layer 402 is located on the entire top surface of the second dielectric layer 502. The second dielectric layer 502 can improve the voltage resistance performance of the MOS capacitor structure, ensure that it has a high capacitance, and thus improve the reliability of the BCD device. Moreover, the preparation of the first dielectric layer is compatible with the BCD process, and the preparation cost is relatively low.
[0080] Further, the material of the second dielectric layer 502 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric capability of the high-k material, the second dielectric layer 502 can effectively improve the voltage resistance performance of the MOS capacitor structure at a smaller thickness. The second dielectric layer 502 can be a single-layer structure or a multi-layer structure. For example, the second dielectric layer 502 can be a nitride layer (such as a silicon nitride layer), or a stack of a nitride layer (such as a silicon nitride layer) and an oxide layer (such as a silicon oxide layer, with a thickness of 1-10 nm).
[0081] Further, the thickness of the second dielectric layer 502 can be 1-10 nm. The thickness of the second dielectric layer 502 can be 1-10 nm. But it should not be limited.
[0082] Please continue to refer to Figure 3 The second insulating layer 602 also completely covers the MOS capacitor structure, i.e. covers the fourth ohmic contact region 111, the first isolation structure 210, the second gate oxide layer 302, the second isolation structure 220, the fifth ohmic contact region 122 and the edge of the second well region 102 and the edge of the substrate 100, and the second gate oxide layer 302 and the second dielectric layer 502 are below the second insulating layer 602. The second insulating layer 602 has an opening, and the fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 are also in the opening of the second insulating layer 602, the fifth interconnection structure 705 and the sixth interconnection structure 706 are respectively interconnected with the fourth ohmic contact region 112 and the fifth ohmic contact region 122, and the seventh interconnection structure 707 is interconnected with the second gate electrode layer 402. The second gate electrode layer 402 and the substrate 100 serve as the plates of the MOS capacitor structure, the second gate oxide layer 302 serves as the dielectric layer of the MOS capacitor structure, and the fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 serve as connection and conduction. The voltage applied on the second gate electrode layer 402 and the substrate 100 can control the flow of carriers in the channel in the substrate 100, thereby inducing charges in the semiconductor to form an inversion layer. The fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 can each include an electrically connected plug and an interconnection metal layer, the plug is located in the second insulating layer 602, and at least part of the top surface of the interconnection metal layer is exposed to the second insulating layer 602.
[0083] Optionally, the first insulating layer 601 and the second insulating layer 602 are an integral structure, and the first dielectric layer 501 and the second dielectric layer 502 are an integral structure.
[0084] It should be noted that the field MOS structure in the embodiment is not limited to the field MOS structure in the first embodiment, but can also be the field MOS structure in the second embodiment, which will not be described one by one here.
[0085] Embodiment Four
[0086] Figure 4 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 4. Figure 4 The difference between the embodiment and the third embodiment is that, in the embodiment, the first isolation structure 210 and the second isolation structure 220 are both trench isolation structures.
[0087] Embodiment Five
[0088] Figure 5 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 5. Figure 5As shown, the difference between this embodiment and Embodiment Three is that, in this embodiment, the ohmic contact region includes a fourth ohmic contact region 112 and a fifth ohmic contact region 122, both of which extend from the top surface of the substrate 100 into the first well region 101, and are located on both sides of the first gate oxide layer 301, and contact the first gate oxide layer 301 on both sides, and are a certain distance apart. In this embodiment, the fourth ohmic contact region 112 and the fifth ohmic contact region 122 have the same doping type as the first well region 101, that is, the fourth ohmic contact region 112 and the fifth ohmic contact region 122 have the first doping type.
[0089] Further, the MOS capacitor structure further includes a first isolation structure 210 and a second isolation structure 220, both of which are trench isolation structures in this embodiment. The first isolation structure 210 and the second isolation structure 220 extend from the top surface of the substrate 100 into the first well region 101, and the first isolation structure 210 and the second isolation structure 220 also extend upward to be higher than the top surface of the substrate 100, and the first isolation structure 210 and the second isolation structure 220 are located between the fourth ohmic contact region 112 and the fifth ohmic contact region 122. Figure 5 As can be seen, the top surface of the first isolation structure 210 and the second isolation structure 220 is higher than the top surface of the substrate 100. In some embodiments, the top surface of the first isolation structure 210 and the second isolation structure 220 can also be flush with the top surface of the substrate 100.
[0090] The first isolation structure 210 and the second isolation structure 220 are both located between the fourth ohmic contact region 112 and the fifth ohmic contact region 122; at the same time, the first isolation structure 210 and the second isolation structure 220 are not in contact, but maintain a certain distance. In some embodiments, the first isolation structure 210 and the second isolation structure 220 can also be field oxide layers.
[0091] Optionally, the thickness of the first isolation structure 210 and the second isolation structure 220 can be 1-10 microns.
[0092] Please continue to refer to Figure 3The first gate oxide layer 301 is located on a part of the top surface of the first well region 101, specifically between the first isolation structure 210 and the second isolation structure 220, and covers the top surface of the first well region 101 between the first isolation structure 210 and the second isolation structure 220. In this way, the fourth ohmic contact region 112 and the fifth ohmic contact region 122 are located on both sides of the first gate oxide layer 301, the fourth ohmic contact region 112 is isolated from the second gate oxide layer 302 by the first isolation structure 210, and the fifth ohmic contact region 122 is isolated from the first gate oxide layer 301 by the second isolation structure 220.
[0093] Further, the first dielectric layer 501 is located on the first gate oxide layer 301, and the first gate electrode layer 401 is located on at least a part of the top surface of the first dielectric layer 501. In this embodiment, the first dielectric layer 501 is located on the entire top surface of the first gate oxide layer 301, and the first gate electrode layer 401 is located on the entire top surface of the first dielectric layer 501. The first dielectric layer 501 can improve the voltage resistance performance of the MOS capacitor structure, ensure that it has a high capacitance, and thus improve the reliability of the BCD device. Moreover, the preparation of the first dielectric layer is compatible with the BCD process, and the preparation cost is relatively low.
[0094] Further, the material of the first dielectric layer 501 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric capability of the high-k material, the first dielectric layer 501 can effectively improve the voltage resistance performance of the MOS capacitor structure at a smaller thickness. The first dielectric layer 501 can be a single-layer structure or a multi-layer structure. For example, the first dielectric layer 501 can be a nitride layer (such as a silicon nitride layer), or a stack of a nitride layer (such as a silicon nitride layer) and an oxide layer (such as a silicon oxide layer, with a thickness of 10-100 nm).
[0095] Further, the thickness of the first dielectric layer 501 can be 10-100 nm. The thickness of the first dielectric layer 501 can be 10-100 nm. But it should not be limited.
[0096] Please continue to refer to Figure 5 The first insulating layer 601 also completely covers the MOS capacitor structure, that is, covers the fourth ohmic contact region 111, the first isolation structure 210, the first gate oxide layer 301, the second isolation structure 220, the fifth ohmic contact region 122 and the edge of the first well region 101 and the edge of the substrate 100, and the first gate oxide layer 301 and the first dielectric layer 501 are below the first insulating layer 601. The first insulating layer 601 has an opening, and the fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 are also in the opening of the first insulating layer 601, the fifth interconnection structure 705 and the sixth interconnection structure 706 are respectively interconnected with the fourth ohmic contact region 112 and the fifth ohmic contact region 122, and the seventh interconnection structure 707 is interconnected with the first gate electrode layer 401. The first gate electrode layer 401 and the substrate 100 serve as the plates of the MOS capacitor structure, the first gate oxide layer 301 serves as the dielectric layer of the MOS capacitor structure, and the fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 serve as connection and conduction. Voltage applied on the first gate electrode layer 401 and the substrate 100 can control the flow of carriers in the channel in the substrate 100, thereby inducing charges in the semiconductor to form an inversion layer. The fifth interconnection structure 705, the sixth interconnection structure 706 and the seventh interconnection structure 707 can each include an electrically connected plug and an interconnection metal layer, the plug is located in the first insulating layer 601, and at least part of the top surface of the interconnection metal layer is exposed to the first insulating layer 601.
[0097] In summary, in the BCD device provided in the embodiment of the present application, the substrate, the first well region, the first gate oxide layer, at least one ohmic contact region, the first gate electrode layer and the first dielectric layer are included. The first well region extends downward from the top surface of the substrate, the first gate oxide layer is located on at least part of the top surface of the ohmic contact region in the first well region, the first dielectric layer is located on at least part of the top surface of the first gate oxide layer, and the second gate electrode layer is located on at least part of the top surface of the second dielectric layer. The first dielectric layer is used to lift at least part of the first gate electrode layer, thereby reducing the surface electric field of the first well region, further reducing the HCI (hot carrier injection) effect, improving the reliability of the BCD device, and the preparation of the first dielectric layer is compatible with the BCD process, and the preparation cost is also relatively low.
[0098] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.
[0099] It should also be noted that, although the utility model has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the utility model. For any skilled person in the art, without departing from the scope of the utility model technical scheme, the above disclosed technical content can be used to make many possible changes and modifications to the utility model technical scheme, or modified as equivalent changes and equivalent embodiments. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the utility model, without departing from the content of the utility model technical scheme, all still belong to the scope of the utility model technical scheme protection.
[0100] It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the specification are merely used to distinguish different components, elements, steps and the like in the specification, and are not intended to represent a logical relationship or sequence relationship between the components, elements, steps and the like.
[0101] In addition, it should be recognized that the terms described herein are used only to describe particular embodiments and do not limit the scope of the utility model. It must be noted that the singular forms "a", "an", and "the" used herein include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and can include sub-steps and sub-devices. All conjunctions used herein should be interpreted in the broadest possible sense. In addition, the word "or" should be interpreted as having the logical "or" definition, not the logical "exclusive or" definition, unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the utility model can include manually, automatically or a combination of performing selected tasks.
Claims
1. A BCD device, characterized by, The application relates to a semiconductor device, comprising: a substrate; a first well region extending downward from a top surface of the substrate; at least one ohmic contact region extending downward from a top surface of the first well region; a first gate oxide layer on a top surface of the first well region except a portion of the top surface where the ohmic contact region is located; a first dielectric layer on at least a portion of a top surface of the first gate oxide layer; and a first gate electrode layer on at least a portion of a top surface of the first dielectric layer. The first dielectric layer is on an edge region of the top surface of the first gate oxide layer, and the first gate electrode layer is on a remaining region of the top surface of the first dielectric layer and the first gate oxide layer.
2. The BCD device of claim 1, wherein, The first dielectric layer is on the entire top surface of the first gate oxide layer, and the first gate electrode layer is on the entire top surface of the first dielectric layer.
3. The BCD device of claim 1, wherein, The first dielectric layer is a nitride layer, or the first dielectric layer is a stack of a nitride layer and an oxide layer.
4. The BCD device of claim 1, wherein, The first dielectric layer has a thickness of 200-5000 angstroms.
5. The BCD device of claim 1, wherein, The first dielectric layer has a thickness of 2000-3300 angstroms.
6. The BCD device of claim 1, wherein, The ohmic contact region comprises a first ohmic contact region, a second ohmic contact region and a third ohmic contact region extending from the top surface of the substrate into the first well region, the first ohmic contact region and the second ohmic contact region are located on a first side of the first gate oxide layer, the first ohmic contact region and the second ohmic contact region are adjacent to each other, the second ohmic contact region is in contact with the first side of the first gate oxide layer, the third ohmic contact region is located on a second side of the first gate oxide layer, the third ohmic contact region is in contact with the second side of the first gate oxide layer, the first ohmic contact region has the same doping type as the first well region, and the second ohmic contact region and the third ohmic contact region have the opposite doping type to the first well region.
7. The BCD device of claim 1, wherein, A first insulating layer covers the first ohmic contact region, the second ohmic contact region, the first gate oxide layer, the third ohmic contact region, an edge portion of the first well region and a portion of the substrate without the edge portion, the first gate oxide layer and the first dielectric layer are below the first insulating layer, the first insulating layer has openings, and the first insulating layer has a first interconnection structure, a second interconnection structure, a third interconnection structure and a fourth interconnection structure in the openings of the first insulating layer, the first interconnection structure, the second interconnection structure and the third interconnection structure are respectively interconnected with the first ohmic contact region, the second ohmic contact region and the third ohmic contact region, and the fourth interconnection structure is interconnected with the first gate electrode layer. The application further relates to a semiconductor device, comprising:
8. The BCD device of claim 6, wherein, a substrate; a first well region extending downward from a top surface of the substrate; at least one ohmic contact region extending downward from a top surface of the first well region; a second gate oxide layer on a top surface of the second well region except a portion of the top surface where the ohmic contact region is located; a second dielectric layer on the second gate oxide layer; and a second gate electrode layer on at least a portion of a top surface of the second dielectric layer. The second dielectric layer is on the entire top surface of the second gate oxide layer, and the second gate electrode layer is on the entire top surface of the second dielectric layer.
9. The BCD device of claim 8, wherein, The application further relates to a semiconductor device, comprising:
10. The BCD device of claim 8, wherein, A first isolation structure and a second isolation structure extend from the top surface of the substrate into the second well region and are located on two sides of the second gate oxide layer, respectively.
11. The BCD device of claim 10, wherein, The top surfaces of the first and second isolation structures are flush with the top surface of the substrate, or the top surfaces of the first and second isolation structures are higher than the top surface of the substrate.
12. The BCD device of claim 10, wherein, The first and second isolation structures are field oxide layers or trench isolation structures.
13. The BCD device of claim 8, wherein, The second dielectric layer is a nitride layer, or the second dielectric layer is a stack of a nitride layer and an oxide layer.
14. The BCD device of claim 8, wherein, The thickness of the second dielectric layer is 200 Å to 5000 Å.
15. The BCD device of claim 8, wherein, The thickness of the second dielectric layer is 2000 Å to 3300 Å.
16. The BCD device of claim 8, wherein, The ohmic contact region includes a fourth ohmic contact region and a fifth ohmic contact region extending from the top surface of the substrate into the second well region, the fourth and fifth ohmic contact regions being located on two sides of the second gate oxide layer, respectively, the fourth and fifth ohmic contact regions contacting the two sides of the second gate oxide layer, respectively, and the fourth and fifth ohmic contact regions having the same doping type as the second well region. A second insulating layer covers the fourth ohmic contact region, the first isolation structure, the second gate electrode layer, the second isolation structure, the fifth ohmic contact region, and edges of the second well region and the substrate, the second gate oxide layer and the second dielectric layer being below the second insulating layer, the second insulating layer having openings, the fifth, sixth, and seventh interconnection structures being led out from the openings of the second insulating layer, the fifth and sixth interconnection structures being interconnected with the fourth and fifth ohmic contact regions, respectively, and the seventh interconnection structure being interconnected with the second gate electrode layer.
17. The BCD device of claim 1, wherein, The working voltage of the BCD device is 45 V to 120 V.
18. The BCD device of any of claims 1 to 6, wherein, Further comprising: A first isolation structure and a second isolation structure extend from the top surface of the substrate into the first well region and are located on two sides of the first gate oxide layer, respectively.
19. The BCD device of claim 18, wherein, The top surfaces of the first and second isolation structures are flush with the top surface of the substrate, or the top surfaces of the first and second isolation structures are higher than the top surface of the substrate.
20. The BCD device of claim 18, wherein, The first and second isolation structures are field oxide layers or trench isolation structures.
21. The BCD device of any of claims 1 to 6, wherein, The ohmic contact region includes a fourth ohmic contact region and a fifth ohmic contact region extending from the top surface of the substrate into the first well region, the fourth and fifth ohmic contact regions being located on two sides of the first gate oxide layer, respectively, the fourth and fifth ohmic contact regions contacting the two sides of the first gate oxide layer, respectively, and the fourth and fifth ohmic contact regions having the same doping type as the first well region. A first insulating layer covers the fourth ohmic contact region, the first isolation structure, the first gate electrode layer, the second isolation structure, the fifth ohmic contact region and the first well region edge and the substrate edge, the first gate oxide layer and the first dielectric layer are below the first insulating layer, the first insulating layer has an opening, the fifth interconnection structure, the sixth interconnection structure and the seventh interconnection structure are led out from the opening of the first insulating layer, the fifth interconnection structure and the sixth interconnection structure are interconnected with the fourth ohmic contact region and the fifth ohmic contact region respectively, and the seventh interconnection structure is interconnected with the first gate electrode layer.