Display device

Abstract

The display device comprises a display panel. The display panel includes a circuit layer disposed on a substrate and an element layer disposed on the circuit layer. The main area of the substrate includes a display area including an emission area, and a non-display area. The display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape. The element layer includes light emitting elements disposed in the emission regions, respectively. The circuit layer includes emission pixel drivers electrically connected to the light emitting elements, respectively, and alignment marks disposed in the non-display area. An edge of the main region includes four corner points at which respective sides of the main region extending in different directions are connected to each other. The alignment mark is disposed adjacent to a corresponding corner point of the four corner points.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0182523, filed on December 15, 2023, and all benefits therefrom, the contents of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display device. BACKGROUND

[0003] As the information society develops, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0004] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light emitting display device. Here, the light emitting display device can include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element including an inorganic semiconductor, and a micro light emitting display device including a micro light emitting element.

[0005] The organic light emitting display device can display an image using a plurality of light emitting elements each including a light emitting layer made of an organic light emitting material. As such, the organic light emitting display device uses elements that self-emit light to implement image display, and accordingly can have various desirable characteristics such as low power consumption, high response speed, high light emitting efficiency, high brightness, and wide viewing angle, etc.

[0006] The display surface of the display device from which light is emitted can include a display area in which an image is displayed and a non-display area that is a peripheral area of the display area. In the display area, an emission area for emitting light of various brightness and colors can be arranged. SUMMARY

[0007] When the display area of the display surface of the display device is set to be wide, the area of the display device in which light is emitted becomes wide, so that the aesthetic appeal can be improved, and the compatibility with various electronic devices can be improved. Accordingly, methods for reducing the width of the non-display area of the display surface have been researched and developed.

[0008] However, wires and elements are provided in the non-display area, and thus there is a limit in reducing the width of the non-display area.

[0009] Embodiments of the disclosure provide a display device in which the width of the non-display area viewed in a front direction facing the display surface can be reduced by deforming the edge of the display area into a curved shape.

[0010] However, embodiments of the present disclosure are not limited to those set forth herein. The above and other features of the embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure belongs by referencing the detailed description of the embodiments of the present disclosure given below.

[0011] According to embodiments of the present disclosure, a display device includes a display panel that emits light to display an image. In such embodiments, the display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. In such embodiments, a main area of the substrate includes a display area in which an emission area is arranged and a non-display area disposed around the display area, the display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape, and the element layer includes light emitting elements disposed in the emission area, respectively. In such embodiments, the circuit layer includes emission pixel drivers electrically connected to the light emitting elements, respectively, and an alignment mark disposed in the non-display area. In such embodiments, an edge of the main area includes four corner points at which respective sides of the main area extending in different directions are connected to each other, and the alignment mark is disposed adjacent to a corresponding one of the four corner points.

[0012] In embodiments, the front display area can include a first side and a second side extending in a first direction and opposite to each other, and a third side and a fourth side extending in a second direction crossing the first direction and opposite to each other. In such embodiments, the peripheral display area can include a first side region, a second side region, a third side region, and a fourth side region, respectively in contact with the first side, the second side, the third side, and the fourth side of the front display area; a first corner region in contact with a vertex at which the first side and the third side are connected to each other and disposed between the first side region and the third side region; a second corner region in contact with a vertex at which the second side and the third side are connected to each other and disposed between the second side region and the third side region; a third corner region in contact with a vertex at which the second side and the fourth side are connected to each other and disposed between the second side region and the fourth side region; and a fourth corner region in contact with a vertex at which the first side and the fourth side are connected to each other and disposed between the first side region and the fourth side region. In such embodiments, the alignment mark can include at least one selected from a first alignment mark disposed adjacent to the first corner region; a second alignment mark disposed adjacent to the second corner region; a third alignment mark disposed adjacent to the third corner region; and a fourth alignment mark disposed adjacent to the fourth corner region.

[0013] In an embodiment, the display panel can further include a sealing layer disposed on the element layer, a touch sensor layer disposed on the sealing layer, and one or more dam portions arranged in a dam area of the non-display area surrounding the display area and spaced apart from the display area. In such an embodiment, the circuit layer can include an interlayer insulating layer disposed on the substrate, a first source / drain conductive layer disposed on the interlayer insulating layer, a first planarization layer covering the first source / drain conductive layer, a second source / drain conductive layer disposed on the first planarization layer, and a second planarization layer covering the second source / drain conductive layer. In such an embodiment, the element layer can further include a pixel definition layer disposed on the circuit layer and overlapping with areas between the emission areas spaced apart from each other, and a spacer layer disposed on portions of the pixel definition layer. In such an embodiment, the touch sensor layer can include a touch buffer layer disposed on the sealing layer, a first touch conductive layer disposed on the touch buffer layer, a touch interlayer insulating layer covering the first touch conductive layer, a second touch conductive layer disposed on the touch interlayer insulating layer, and a touch planarization layer covering the second touch conductive layer. In such an embodiment, each of the one or more dam portions can include two or more dam layers, and each of the two or more dam layers can be disposed at the same layer as a corresponding one of the first planarization layer, the second planarization layer, the pixel definition layer, and the spacer layer.

[0014] In such an embodiment, the touch interlayer insulating layer can include an organic insulating material, and the display panel can further include a cap portion disposed at the same layer as the first touch conductive layer, overlapping with the dam area, and spaced apart from the alignment mark in a plan view.

[0015] In an embodiment, the display panel can further include a cap connection portion connecting adjacent ones of the cap portions to each other, disposed to have a width smaller than a width of the cap portion, and spaced apart from the alignment mark in a plan view.

[0016] In an embodiment, the circuit layer can further include a power line disposed in the non-display area, wherein the power line transmits a power source for driving the light emitting element. In such an embodiment, a portion of the power line overlapping with the dam area can include a first line layer disposed at the same layer as the first source / drain conductive layer, and a second line layer disposed at the same layer as the second source / drain conductive layer and in contact with the first line layer, and each of the alignment marks can be defined by an engraved pattern defined by the first line layer and the second line layer stacked in sequence.

[0017] In an embodiment, the circuit layer can further include a first semiconductor layer disposed on the substrate, a first gate insulating layer covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer, a second gate insulating layer covering the first gate conductive layer, and a second gate conductive layer disposed on the second gate insulating layer.

[0018] In an embodiment, the interlayer insulating layer can cover the second gate conductive layer, and the alignment mark can be defined by a relief pattern disposed at the same layer as one of the first gate conductive layer and the second gate conductive layer.

[0019] In an embodiment, the circuit layer can further include an auxiliary interlayer insulating layer covering the second gate conductive layer, a second semiconductor layer disposed on the auxiliary interlayer insulating layer, a third gate insulating layer covering the second semiconductor layer, and a third gate conductive layer disposed on the third gate insulating layer and covered by the interlayer insulating layer. In such an embodiment, the alignment mark can be defined by a relief pattern disposed at the same layer as one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer.

[0020] In an embodiment, the display device can further include a bracket supporting the display panel, and a cover window disposed on the display panel and coupled to the bracket. In such an embodiment, the cover window can be provided with an alignment hole corresponding to the alignment mark defined therein, and the peripheral display area can have a shape bent toward the bracket.

[0021] In an embodiment, the alignment mark can include two or more alignment keys spaced apart from each other.

[0022] According to an embodiment of the disclosure, there is provided a display device including a display panel emitting light to display an image, a bracket supporting the display panel, and a cover window disposed on the display panel and coupled to the bracket. In such an embodiment, the display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. In such an embodiment, a main area of the substrate includes a display area in which an emission area is arranged and a non-display area disposed around the display area, the display area includes a front display area and a peripheral display area disposed around the front display area and having a shape bent toward the bracket, and the circuit layer includes an alignment mark disposed in the non-display area. In such an embodiment, edges of the main area include four corner points at which respective sides of the main area extending in different directions are connected to each other. In such an embodiment, the alignment mark is disposed adjacent to a corresponding one of the four corner points, and the cover window is provided with an alignment hole corresponding to the alignment mark defined therein.

[0023] In an embodiment, the element layer can include light emitting elements respectively disposed in the emission regions, and the circuit layer can further include: emission pixel drivers respectively electrically connected to the light emitting elements; and a power line disposed in the non-display region, wherein the power line transmits a power source for driving the light emitting elements.

[0024] In an embodiment, the display panel can further include: a sealing layer disposed on the element layer; a touch sensor layer disposed on the sealing layer; and one or more dam portions arranged in a dam region of the non-display region surrounding the display region and spaced apart from the display region. In such an embodiment, the circuit layer can include: a first semiconductor layer disposed on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; and a second gate conductive layer disposed on the second gate insulating layer; an interlayer insulating layer disposed on the second gate conductive layer; a first source / drain conductive layer disposed on the interlayer insulating layer; a first planarization layer covering the first source / drain conductive layer; a second source / drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source / drain conductive layer. In such an embodiment, the element layer can further include: a pixel definition layer disposed on the circuit layer and overlapping with a region between the emission regions spaced apart from each other; and a spacer layer disposed on portions of the pixel definition layer. In such an embodiment, the touch sensor layer can include: a touch buffer layer disposed on the sealing layer; a first touch conductive layer disposed on the touch buffer layer; a touch interlayer insulating layer covering the first touch conductive layer; a second touch conductive layer disposed on the touch interlayer insulating layer; and a touch planarization layer covering the second touch conductive layer. In such an embodiment, each of the one or more dam portions can include two or more dam layers, and each of the two or more dam layers can be disposed at the same layer as a corresponding one of the first planarization layer, the second planarization layer, the pixel definition layer, and the spacer layer.

[0025] In an embodiment, the touch interlayer insulating layer can include an organic insulating material, and the display panel can further include: a capping portion disposed at the same layer as the first touch conductive layer, overlapping with the dam region, and spaced apart from the alignment mark in a plan view.

[0026] In an embodiment, the display panel can further include: a capping connection portion connecting adjacent ones of the capping portions to each other, disposed to have a width smaller than a width of the capping portions, and spaced apart from the alignment mark in a plan view.

[0027] In an embodiment, the portion of the power line that overlaps the dam region can include a first line layer disposed at the same layer as the first source / drain conductive layer, and a second line layer disposed at the same layer as the second source / drain conductive layer and in contact with the first line layer. In such an embodiment, the alignment mark can be defined by an engraved pattern defined by the first line layer and the second line layer stacked sequentially.

[0028] In an embodiment, the interlayer insulating layer can cover the second gate conductive layer, and the alignment mark can be defined by a relief pattern disposed at the same layer as one of the first gate conductive layer and the second gate conductive layer.

[0029] In an embodiment, the circuit layer can further include an auxiliary interlayer insulating layer covering the second gate conductive layer, a second semiconductor layer disposed on the auxiliary interlayer insulating layer, a third gate insulating layer covering the second semiconductor layer, and a third gate conductive layer disposed on the third gate insulating layer and covered by the interlayer insulating layer. In such an embodiment, the alignment mark can be defined by a relief pattern disposed at the same layer as one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer.

[0030] In an embodiment, the alignment mark can include two or more alignment keys having different shapes from each other and spaced apart from each other in a plan view.

[0031] A display device according to an embodiment can include a display panel that emits light to display an image, and a main area of a substrate of the display panel can include a display area in which an emission area is disposed, and a non-display area disposed around the display area. In such an embodiment, the display area can include a front display area, and a peripheral display area disposed around the front display area and having a curved shape.

[0032] According to an embodiment, the peripheral display area can include a first side area, a second side area, a third side area, and a fourth side area in contact with a first side, a second side, a third side, and a fourth side of the front display area, respectively, and a first corner area, a second corner area, a third corner area, and a fourth corner area in contact with vertices at which any two of the first side, the second side, the third side, and the fourth side of the front display area connect to each other, respectively.

[0033] In this embodiment, as described above, the display area includes a peripheral display area having a curved shape, and accordingly, a non-display area connected to the peripheral display area can have a curved shape together with the peripheral display area. That is, a width of the non-display area having a curved shape viewed in a front direction facing the display surface can be less than a width of the non-display area in a non-curved state. Accordingly, a width of the display area of the display surface of the display device viewed in the front direction can increase, and thus, the aesthetic appeal and compatibility of the display device can be improved.

[0034] According to an embodiment, the circuit layer of the display panel can include four alignment marks disposed in the non-display area and adjacent to four corner points of the edges of the main area at which respective sides of the main area extending in different directions are connected to each other.

[0035] That is, according to an embodiment, four alignment marks adjacent to four corner points of the main area are disposed in the non-display area.

[0036] In this embodiment, even in a state in which the non-display area is deformed into a curved shape together with the peripheral display area, the edges of the main area of the display panel can be more accurately inferred through the above-described four alignment marks, and thus, a process error during an alignment process between the display panel and the cover window can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the attached drawings, in which:

[0038] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0039] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1

[0040] Figure 3 is a plan view illustrating a display panel of Figure 2

[0041] Figure 4 is a layout view illustrating a portion C of Figure 3

[0042] Figure 5 is a plan view illustrating a cover window of Figure 2

[0043] Figure 6 is a view illustrating an alignment process between a display panel and a cover window according to an embodiment; ​​​​

[0044] Figure 7 is a cross-sectional view of the display panel taken along a line B-B’ of Figure 1 ;

[0045] Figure 8 is a schematic plan view of a touch sensor layer according to an embodiment of Figure 7 ;

[0046] Figure 9 is an enlarged plan view of a portion E of Figure 8 ;

[0047] Figure 10 is an equivalent circuit diagram of an emission pixel driver according to an embodiment of Figure 4 ;

[0048] Figure 11 is a cross-sectional view taken along a line F-F’ of Figure 10 according to an embodiment of Figure 9 ;

[0049] Figure 12 is an equivalent circuit diagram of an emission pixel driver according to an embodiment of Figure 4 ;

[0050] Figure 13 is a cross-sectional view taken along a line F-F’ of Figure 12 according to an embodiment of Figure 9 ;

[0051] Figure 14 is a plan view of a portion D of Figure 3 according to an embodiment of ;

[0052] Figure 15 is a cross-sectional view taken along a line G-G’ of Figure 14 ;

[0053] Figure 16 is a cross-sectional view taken along a line H-H’ of Figure 14 ;

[0054] Figure 17 is a plan view of a portion D of Figure 3 according to an embodiment of ;

[0055] Figure 18 is a plan view of a portion D of Figure 3 according to an embodiment of ;

[0056] Figure 19 is a cross-sectional view taken along a line I-I’ of Figure 18 ;

[0057] Figure 20 is a plan view of a portion D of Figure 3a plan view of portion D of FIG. 1; and

[0058] Figure 21 is a cross-sectional view taken along line J-J' of FIG. 1. Figure 20 DETAILED DESCRIPTION

[0059] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0060] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" another element, then there are no intervening elements or layers present. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, and the like that are disclosed in the drawings are only examples and the present disclosure is not limited to the details of the drawings.

[0061] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms "a," "an," and "at least one" do not denote the limitation of quantity, but rather denote the inclusion of one and more than one, unless the context clearly indicates otherwise. Thus, reference to "a" element is a reference to one or more elements. For example, "a" element has the same meaning as "at least one" element, unless the context clearly indicates otherwise. "At least one" should not be interpreted as limiting only to "one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0063] ​Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's relationship to another element as the device is illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower", can encompass both an orientation of "lower" and "upper", depending on the particular orientation being referred to. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The terms "below" and "beneath" can encompass both an orientation of above and below, depending on the particular orientation being referred to.

[0064] Features of various embodiments of the present disclosure can be partially or entirely coupled or combined with each other and can interoperate and interdrive in technically different ways. The embodiments can be implemented independently of each other or together in interdependent relationships.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0066] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, a region illustrated or described as flat can often have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present disclosure.

[0067] Embodiments of the present disclosure will be described in detail below with reference to the attached drawings.

[0068] Figure 1 is a perspective view illustrating a display device according to an embodiment. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 .

[0069] Reference will now be made to Figure 1The display device 10 according to the embodiment is a device that displays a moving image or a still image, and can be used to provide a display screen of various products such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet Personal Computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a Portable Multimedia Player (PMP), a navigation device, and an Ultra Mobile PC (UMPC).

[0070] Alternatively, the display device 10 according to the embodiment can be applied to a Central Information Display (CID) disposed on an instrument panel, a center console, or an instrument cluster of a vehicle, an interior mirror display that replaces a side mirror of a vehicle, or a display disposed on a back of a front seat as an entertainment facility of a rear seat of a vehicle.

[0071] Reference Figure 2 The display device 10 according to the embodiment can include a display panel 100 that emits light for displaying an image.

[0072] Further, the display device 10 according to the embodiment can further include a bracket 200 that supports the display panel 100, and a cover window 300 disposed on the display panel 100 and coupled to the bracket 200.

[0073] The display panel 100 can be a light emitting display panel including a light emitting element. In an embodiment, for example, the display panel 100 can be an organic light emitting display panel using an organic light emitting diode including an organic light emitting layer, a micro light emitting diode display panel using a micro light emitting diode (LED), a quantum dot light emitting display panel using a quantum dot light emitting diode including a quantum dot light emitting layer, or an inorganic light emitting display panel using an inorganic light emitting diode including an inorganic semiconductor. Hereinafter, for convenience of description, an embodiment in which the display panel 100 is an organic light emitting display panel will be mainly described.

[0074] The bracket 200 can include a rigid insulating material to prevent the display panel 100 from being deformed and to mitigate physical and electrical impacts of the outside on the display panel 100. However, this is merely an example, and the material of the bracket 200 can be variously changed.

[0075] The cover window 300 can include a light-transmitting material. The cover window 300 can include or be made of an inorganic material such as glass or an organic material such as plastic or a polymer material.

[0076] The cover window 300 can be coupled (e.g., fastened) to the bracket 200 by an adhesive material 400 disposed at an edge thereof.

[0077] The cover window 300 can also be attached to the display panel 100 through a transparent adhesive member such as an optical clear adhesive (OCA) film or an optical clear resin (OCR) layer.

[0078] In this embodiment, the cover window 300 can protect the display panel 100 from the effects of electrical and physical impacts on the display surface.

[0079] As Figure 1 illustrated in FIG. 1, according to an embodiment, the display panel 100 can include a display area DA that emits light and a non-display area NDA disposed around the display area DA.

[0080] The display area DA can include a front display area FSA having a flat shape and a peripheral display area PSA disposed around the front display area FSA and having a curved shape.

[0081] The front display area FSA can include first and second sides SD1 and SD2 extending in a first direction DR1 and facing each other in a second direction DR2, and third and fourth sides SD3 and SD4 extending in the second direction DR2, connecting the first and second sides SD1 and SD2 to each other, and facing each other in the first direction DR1.

[0082] In an embodiment, for example, the first and second sides SD1 and SD2 can be shorter than the third and fourth sides SD3 and SD4. That is, the front display area FSA can have a quadrangular shape in a plan view (or when viewed in a third direction DR3). Here, the third direction can be a direction perpendicular to a plane defined by the first and second directions DR1 and DR2. The third direction DR3 can be a thickness direction of the display device 10.

[0083] In another embodiment, for example, a corner where each of the first and second sides SD1 and SD2 and each of the third and fourth sides SD3 and SD4 meet together can be formed as an arc having a curved shape or a vertex having a right angle shape.

[0084] However, the shape of the front display area FSA according to an embodiment is not limited to the quadrangular shape illustrated in FIG. 1, and can also be a polygonal shape other than the quadrangular shape, a circular shape, or an elliptical shape. Figure 1

[0085] The peripheral display area PSA can include a first side region SS1 in contact with the first side SD1 of the front display area FSA, a second side region SS2 in contact with the second side SD2 of the front display area FSA, a third side region SS3 in contact with the third side SD3 of the front display area FSA, and a fourth side region SS4 in contact with the fourth side SD4 of the front display area FSA.​

[0086] Further, the peripheral display area PSA can further include a first corner area CS1 contacting vertices at which the first side SD1 and the third side SD3 are connected to each other and disposed between the first side area SS1 and the third side area SS3, a second corner area CS2 contacting vertices at which the second side SD2 and the third side SD3 are connected to each other and disposed between the second side area SS2 and the third side area SS3, a third corner area CS3 contacting vertices at which the second side SD2 and the fourth side SD4 are connected to each other and disposed between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 contacting vertices at which the first side SD1 and the fourth side SD4 are connected to each other and disposed between the first side area SS1 and the fourth side area SS4.

[0087] The first side area SS1 can extend from the first side SD1 and be curved toward the bracket 200 with a predetermined first curvature.

[0088] The second side area SS2 can extend from the second side SD2 and be curved toward the bracket 200 with a predetermined second curvature. The second curvature can be in the same range as that of the first curvature.

[0089] The third side area SS3 can extend from the third side SD3 and be curved toward the bracket 200 with a predetermined third curvature. The third curvature can be in the same or similar range as that of the first or second curvature, but is not limited thereto.

[0090] The fourth side area SS4 can extend from the fourth side SD4 and be curved toward the bracket 200 with a predetermined fourth curvature. The fourth curvature can be in the same range as that of the third curvature.

[0091] The first corner area CS1 can be disposed between one side of the first side area SS1 and one side of the third side area SS3.

[0092] The first corner area CS1 can be a dual curvature area curved with the first curvature of the first side area SS1 and the third curvature of the third side area SS3.

[0093] The second corner area CS2 can be disposed between one side of the second side area SS2 and the other side of the third side area SS3.

[0094] The second corner area CS2 can be a dual curvature area curved with the second curvature of the second side area SS2 and the third curvature of the third side area SS3.

[0095] The third corner area CS3 can be disposed between the other side of the second side area SS2 and one side of the fourth side area SS4.

[0096] The third corner region CS3 can be a hyperbolic region that bends with the second curvature of the second side region SS2 and the fourth curvature of the fourth side region SS4.

[0097] The fourth corner area CS4 can be set between the other side of the first side area SS1 and the other side of the fourth side area SS4.

[0098] The fourth corner region CS4 can be a hyperbolic region that bends with the first curvature of the first side region SS1 and the fourth curvature of the fourth side region SS4.

[0099] As described above, according to the embodiment, the display area DA includes not only the front display area FSA with a flat shape, but also the peripheral display area PSA with a shape that curves toward the bracket 200.

[0100] The non-display area NDA is positioned around the display area DA, and therefore can be connected to the outside of the peripheral display area PSA.

[0101] In other words, the non-display area NDA connected to the peripheral display area PSA with a curved shape can have a curved shape together with the peripheral display area PSA with a curved shape.

[0102] like Figure 2 As illustrated, the display device 10 may include a display area DA in which light is emitted from the display panel 100, and a non-display area NDA disposed around the display area DA and not emitting light.

[0103] The display area DA of the display panel 100 may have a peripheral display area PSA at its edge (see...). Figure 1 The peripheral display area PSA has a curved shape, so the non-display area NDA of the display device 10 can be disposed on the side of the display device 10.

[0104] In addition, each of the bracket 200 and the cover window 300 may have its edges curved to correspond to (or be similar to) the shape of the display panel 100.

[0105] Accordingly, when in the front display area FSA facing the display device 10 (see...) Figure 1 When viewed from the front direction of the light (e.g., the opposite direction of the third direction DR3), the width W of the non-display area NDA with a curved shape of the display device 10 can be smaller than the width L of the non-display area NDA in its non-curved state.

[0106] Therefore, since the width W of the non-display area NDA in the display surface of the display device 10, which is viewed from the front, is reduced, the proportion of the display area DA of the display surface can be increased, and thus the aesthetic appeal and compatibility of the display device 10 can be improved.

[0107] Figure 3 It is a diagram. Figure 2 A floor plan of the display panel. Figure 4 It is a diagram. Figure 3 The layout diagram of part C.

[0108] refer to Figure 3 According to the embodiment, the display panel 100 of the display device 10 may include a substrate 110 and four alignment marks ALMS that are adjacent to four corner points VT1, VT2, VT3 and VT4 at the edges of the main region MA of the substrate 110.

[0109] The substrate 110 may include a main region MA corresponding to the display surface and a sub-region SBA protruding from one side of the main region MA.

[0110] The main area MA may include a display area DA that emits light and a non-display area NDA that is located around the display area DA and does not emit light.

[0111] refer to Figure 4 An emission area EA can be arranged in the display area DA to emit light of various colors and brightness to display images.

[0112] The display area DA may further include a non-emission area located in the interval between the emission areas EA.

[0113] The emission area EA may have a rhomboid shape in the plan view (or when viewed on a third-party DR3), or a rectangular shape in the plan view. However, this is merely an example, and the shape of the emission area EA in the plan view according to the embodiment is not limited to this. Figure 4 The shape is illustrated in the figure. Alternatively, the emission area EA can have a polygonal shape such as other quadrilateral, pentagonal, or hexagonal shapes in the plan view, or a circular or elliptical shape including curved edges in the plan view.

[0114] The emission region EA may include a first emission region EA1 that emits light of a first color in a predetermined wavelength band, a second emission region EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission region EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0115] In an embodiment, for example, the first color can be red corresponding to a wavelength band of about 600 nanometers (nm) to about 750 nm. The second color can be green corresponding to a wavelength band of about 480 nm to about 560 nm. The third color can be blue corresponding to a wavelength band of about 370 nm to about 460 nm.

[0116] The first emission area EA1 and the third emission area EA3 can be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0117] The second emission area EA2 can be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0118] Further, the second emission area EA2 can be adjacent to the first emission area EA1 and the third emission area EA3 in diagonal directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2.

[0119] Pixels PX for displaying various luminances and colors can be provided by the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other among such emission areas EA.

[0120] In other words, the pixel PX can be a basic unit for displaying various colors including white at a predetermined luminance.

[0121] Each of the pixels PX can include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Accordingly, each of the pixels PX can display various colors by mixing light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other.

[0122] As Figure 3 As illustrated in FIG. 1, the display panel 100 according to an embodiment can include a substrate 110, a plurality of pixels PX, and a plurality of emission areas EA.

[0123] The front surface display area FSA can maintain a flat shape on a plane defined by the first direction DR1 and the second direction DR2.

[0124] The front surface display area FSA can include a first side SD1 and a second side SD2 extending in the first direction DR1 and facing each other in the second direction DR2, and a third side SD3 and a fourth side SD4 extending in the second direction DR2, connecting the first side SD1 and the second side SD2 to each other and facing each other in the first direction DR1.

[0125] The peripheral display area PSA can be disposed between the front display area FSA and the non-display area NDA. The peripheral display area PSA can have a ring shape surrounding the front display area FSA.

[0126] In an embodiment, as illustrated in Figure 1 and Figure 2 , the peripheral display area PSA can be deformed into a curved shape.

[0127] As illustrated in Figure 3 , the peripheral display area PSA can include first, second, third, and fourth side areas SS1, SS2, SS3, and SS4 respectively contacting first, second, third, and fourth sides SD1, SD2, SD3, and SD4 of the front display area FSA, a first corner area CS1 contacting vertices at which the first and third sides SD1 and SD3 are connected to each other and disposed between the first and third side areas SS1 and SS3, a second corner area CS2 contacting vertices at which the second and third sides SD2 and SD3 are connected to each other and disposed between the second and third side areas SS2 and SS3, a third corner area CS3 contacting vertices at which the second and fourth sides SD2 and SD4 are connected to each other and disposed between the second and fourth side areas SS2 and SS4, and a fourth corner area CS4 contacting vertices at which the first and fourth sides SD1 and SD4 are connected to each other and disposed between the first and fourth side areas SS1 and SS4.

[0128] The non-display area NDA can be disposed at (or along) an edge of the main area MA and can have a ring shape surrounding the display area DA.

[0129] The non-display area NDA can include a dam area DMA surrounding the display area DA and spaced apart from the display area DA. One or more dam portions (DM1 and DM2, see Figure 14 , Figure 15 and Figure 16 ) having a ring shape surrounding the display area DA can be arranged in the dam area DMA.

[0130] The sub area SBA can face the first side SD1 of the front display area FSA.

[0131] The sub area SBA can include a bend area BA deformed (or curved) into a meandering shape and a pad area PDA connected to the bend area BA.

[0132] When the main area MA has a shape similar to that of the front side display area FSA, the edge of the main area MA can include four corner points VT1, VT2, VT3, and VT4 at which respective sides of the main area MA extending in different directions are connected to each other.

[0133] According to an embodiment, the display panel 100 can include four alignment marks ALMS disposed in the non-display area NDA and adjacent to the four corner points VT1, VT2, VT3, and VT4 at the edge of the main area MA, in each of which two sides of the main area MA extending in different directions are connected to each other.

[0134] According to an embodiment, the alignment marks ALMS can include a first alignment mark ALM1 disposed adjacent to the first corner point VT1 of the main area MA and the first corner area CS1 of the peripheral display area PSA, a second alignment mark ALM2 disposed adjacent to the second corner point VT2 of the main area MA and the second corner area CS2 of the peripheral display area PSA, a third alignment mark ALM3 disposed adjacent to the third corner point VT3 of the main area MA and the third corner area CS3 of the peripheral display area PSA, and a fourth alignment mark ALM4 disposed adjacent to the fourth corner point VT4 of the main area MA and the fourth corner area CS4 of the peripheral display area PSA.

[0135] Such alignment marks ALMS can be used as an alignment reference during an alignment process between the display panel 100 and the cover window 300 (see Figure 2 ).

[0136] Figure 5 is a plan view illustrating a cover window of Figure 2 . Figure 6 is a view illustrating an alignment process between a display panel and a cover window according to an embodiment.

[0137] As illustrated in Figure 5 , the cover window 300 of the display device 10 according to an embodiment can include a light transmission portion TRL that transmits light and a light blocking portion BLL disposed at an edge around the light transmission portion TRL.

[0138] The light transmission portion TRL can overlap the display area DA (see Figure 3 ) of the display panel 100 (see Figure 3 ). Accordingly, light can be emitted from the display area DA (see Figure 3 ) of the display panel 100 (see Figure 3 ) through the light transmission portion TRL to the outside to display an image.

[0139] The light-blocking portion BLL can overlap with a non-display area NDA (see Figure 2 ) which is an area other than the display area DA of the display device 10. In this embodiment, light emission in the non-display area NDA can be reduced by the light-blocking portion BLL.

[0140] The cover window 300 can be provided with an alignment hole ALH corresponding to an alignment mark ALMS of the display panel 100 (see Figure 3 ).

[0141] The alignment hole ALH can be a hole defined or formed through the light-blocking portion BLL.

[0142] Referring to Figure 6 , in an alignment process between the display panel 100 and the cover window 300, the cover window 300 can be disposed on the display panel 100 in the third direction DR3 in parallel with the display panel 100. In this process, in the third direction DR3, whether the position of the cover window 300 with respect to the display panel 100 is normal can be determined by whether the alignment marks ALMS of the display panel 100 are all seen through the alignment holes ALH of the cover window 300.

[0143] According to an embodiment, the display panel 100 includes first, second, third, and fourth alignment marks ALM1, ALM2, ALM3, and ALM4 adjacent to the first, second, third, and fourth corner areas CS1, CS2, CS3, and CS4, respectively, and the cover window 300 includes four alignment holes ALH corresponding to the four alignment marks ALMS of the display panel 100, respectively.

[0144] Therefore, even if the peripheral display area PSA of the edge of the display area DA is deformed into a curved shape, alignment between the display panel 100 and the cover window 300 can be performed at the four corners of the main area MA having a quadrangular shape, so that a process error in the alignment process between the display panel 100 and the cover window 300 can be reduced.

[0145] Figure 7 is a cross-sectional view of the display panel taken along a line B-B' of Figure 1 .

[0146] Referring to Figure 7 , the display panel 100 of the display device 10 according to an embodiment can include a substrate 110, a circuit layer 120 disposed on the substrate 110, and an element layer 130 disposed on the circuit layer 120.

[0147] The substrate 110 can include a main area MA and a sub area SBA.

[0148] The main area MA can include a display area DA and a non-display area NDA disposed around the display area DA.

[0149] The display area DA can include a front-side display area FSA and a peripheral-side display area PSA disposed around the front-side display area FSA and having a curved shape.

[0150] The edge of the front-side display area FSA can include a first side SD1 and a second side SD2 opposite each other in the second direction DR2.

[0151] The peripheral-side display area PSA can include a first side area SS1 disposed between the first side SD1 of the front-side display area FSA and the non-display area NDA and a second side area SS2 disposed between the second side SD2 of the front-side display area FSA and the non-display area NDA.

[0152] Further, as Figure 3 illustrated in FIG. 1B, the edge of the front-side display area FSA can further include a third side SD3 and a fourth side SD4 opposite each other in the first direction DR1.

[0153] The peripheral-side display area PSA can further include a third side area SS3 disposed between the third side SD3 of the front-side display area FSA and the non-display area NDA and a fourth side area SS4 disposed between the fourth side SD4 of the front-side display area FSA and the non-display area NDA.

[0154] Further, the peripheral-side display area PSA can further include a first corner area CS1 contacting a vertex at which the first side SD1 and the third side SD3 are connected to each other and disposed between the first side area SS1 and the third side area SS3, a second corner area CS2 contacting a vertex at which the second side SD2 and the third side SD3 are connected to each other and disposed between the second side area SS2 and the third side area SS3, a third corner area CS3 contacting a vertex at which the second side SD2 and the fourth side SD4 are connected to each other and disposed between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 contacting a vertex at which the first side SD1 and the fourth side SD4 are connected to each other and disposed between the first side area SS1 and the fourth side area SS4.

[0155] According to an embodiment, the display device 10 can further include a display driving circuit 500 provided as an integrated circuit (IC) chip and mounted in a pad area PDA of the sub area SBA of the substrate 110.

[0156] The display driving circuit 500 can supply a data signal to the data lines DL (see Figure 10 and Figure 12) supply data signal Vdata (see Figure 10 and Figure 12 ).

[0157] According to an embodiment, the display device 10 can further include a circuit board combined with the pad area PDA of the sub area SBA of the substrate 110. The circuit board can be combined to the signal pads SPD (see Figure 8 ) provided in the sub area SBA of the substrate 110 using a low-resistance and high-reliability material such as anisotropic conductive film or self-assembled anisotropic conductive paste (SAP).

[0158] As illustrated in Figure 4 , the emission area EA can be disposed in the display area DA.

[0159] The circuit layer 120 (see Figure 7 ) can include the emission pixel drivers EPD disposed side by side in the first direction DR1 and the second direction DR2.

[0160] As illustrated in Figure 7 , the element layer 130 can include the light emitting elements LE (see Figure 10 , Figure 11 , Figure 12 and Figure 13 ) disposed in the emission area EA, respectively.

[0161] The emission pixel drivers EPD (see Figure 4 ) of the circuit layer 120 can be electrically connected to the light emitting elements LE (see Figure 10 , Figure 11 , Figure 12 and Figure 13 ) of the element layer 130.

[0162] According to an embodiment, the display panel 100 can further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140.

[0163] The sealing layer 140 can be disposed on the element layer 130 and can have a structure in which two or more inorganic films and at least one organic film are alternately stacked.

[0164] The touch sensor layer 150 can include a touch electrode for detecting a signal that changes depending on a touch by a person or an object to sense a point of the main area MA at which the touch by the person or the object has occurred.

[0165] According to an embodiment, the display panel 100 can prevent deterioration of image visibility due to reflection of external light by blocking the external light reflected from the touch sensor layer 150, the sealing layer 140, the element layer 130, and the circuit layer 120, and the interfaces between these layers.

[0166] Figure 8 is a schematic plan view illustrating a touch sensor layer according to an embodiment. Figure 7 Figure 9 is an enlarged plan view of a portion E of Figure 8

[0167] Figure 8 and Figure 9 Embodiments in which the touch sensor layer 150 is a capacitive type touch sensor layer are illustrated. In such embodiments, the display device 10 can further include a touch driving circuit for sensing a touch based on whether capacitance is changed. The touch driving circuit can be mounted on the pad area PDA of the substrate 110 or on a circuit board. However, the touch driving circuit is not limited to being mounted on the pad area PDA of the substrate 110 or on the circuit board. Figure 8 and Figure 9 Embodiments illustrated in Figure 8 and Figure 9 are merely examples for the sake of description, and the touch sensor layer 150 according to an embodiment is not limited to the touch sensor layer 150 illustrated in

[0168] For the sake of illustration and description, Figure 8 only some of the components of the touch sensor layer 150 are illustrated.

[0169] Referring to Figure 8 , the touch sensor layer 150 can be disposed in the main area MA of the substrate 110. The touch sensor layer 150 can include a touch sensing area TSA for sensing a touch of a user and a touch peripheral area TPA disposed around the touch sensing area TSA.

[0170] The touch sensing area TSA can be wider than the display area DA and can be similar to the display area DA. Accordingly, the touch peripheral area TPA, which is a peripheral area of the touch sensing area TSA, can be similar to the non-display area NDA, which is a peripheral area of the display area DA.

[0171] In an embodiment, for example, the touch sensing area TSA can overlap the display area DA and an edge of the non-display area NDA that contacts the display area DA. In such an embodiment, the touch peripheral area TPA can overlap a remaining portion of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0172] ​​The touch sensor layer 150 can include sensor electrodes SE and dummy electrodes DE which are arranged in a matrix form in the touch sensing area TSA and generate mutual capacitances, and sensor lines TL1, TL2, and RL which are disposed in the touch peripheral area TPA.

[0173] The sensor electrodes SE can include touch driving electrodes TE to which a touch driving signal is applied, and receiving electrodes RE for sensing a voltage charged in mutual capacitances with the touch driving electrodes TE.

[0174] The sensor lines TL1, TL2, and RL can include a first driving line TL1, a second driving line TL2, and a sensing line RL.

[0175] Each of the first driving line TL1 and the second driving line TL2 can be electrically connected to two or more touch driving electrodes TE among the touch driving electrodes TE which are connected to each other in the second direction DR2.

[0176] The first driving line TL1 can extend from a side of an edge of the touch sensing area TSA which extends in the first direction DR1 and is adjacent to the sub area SBA to reach the sub area SBA.

[0177] The second driving line TL2 can extend from another side of the edge of the touch sensing area TSA which extends in the first direction DR1 and is spaced apart from the sub area SBA and in parallel with a side of the edge of the touch sensing area TSA which extends in the second direction DR2 to reach the sub area SBA.

[0178] The sensing line RL can be electrically connected to two or more receiving electrodes RE among the receiving electrodes RE which are connected to each other in the first direction DR1.

[0179] The receiving electrodes RE can be arranged side by side in the first direction DR1. The receiving electrodes RE which are adjacent to each other in the first direction DR1 can be electrically connected to each other by a protruding portion in the first direction DR1.

[0180] The touch driving electrodes TE can be arranged side by side in the second direction DR2. The touch driving electrodes TE which are adjacent to each other in the second direction DR2 can be electrically connected to each other by a bridge electrode BE (see Figure 9 ).

[0181] Each of the touch driving electrodes TE and the receiving electrodes RE can have a shape which surrounds the dummy electrode DE disposed at the center thereof.

[0182] Each of the dummy electrodes DE can be spaced apart from the touch driving electrodes TE or the receiving electrodes RE which surround each of the dummy electrodes DE. The dummy electrodes DE can be maintained in a floating state.

[0183] Figure 9 Embodiments in which each of the touch driving electrodes TE, the reception electrodes RE, and the dummy electrodes DE has a rhombus shape in a plan view are illustrated, but embodiments are not limited to Figure 9 Embodiments illustrated in FIGS. 1A and 1B. In embodiments, for example, the shape in a plan view of each of the touch driving electrodes TE, the reception electrodes RE, and the dummy electrodes DE can be a quadrilateral shape other than a rhombus shape, a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0184] According to embodiments, the display panel 100 can include signal pads SPD disposed in the pad area PDA of the sub-area SBA of the substrate 110 and connected to the circuit board.

[0185] In embodiments, for example, the display driving circuit 500 can be mounted in the pad area PDA.

[0186] The pad area PDA can include a display pad area DPDA adjacent to the display driving circuit 500, and a first touch pad area TPDA1 and a second touch pad area TPDA2 disposed on both sides of the display pad area DPDA, respectively.

[0187] The signal pads SPD can include display signal pads DPD disposed in the display pad area DPDA, and first and second touch pads TPD1 and TPD2 disposed in the first and second touch pad areas TPDA1 and TPDA2, respectively.

[0188] The display signal pads DPD can be electrically connected to the circuit layer 120 or the display driving circuit 500.

[0189] The first touch pad TPD1 can be electrically connected to the first and second driving lines TL1 and TL2.

[0190] The second touch pad TPD2 can be electrically connected to the sensing line RL.

[0191] Referring to Figure 9 , the touch sensor layer 150 can further include bridge electrodes BE electrically connecting the touch driving electrodes TE adjacent to each other in the second direction DR2 to each other.

[0192] The bridge electrodes BE can be electrically connected to the touch driving electrodes TE through the touch electrode connection holes TCNT.

[0193] The touch driving electrodes TE adjacent to each other in the second direction DR2 can be electrically connected to each other through two or more bridge electrodes BE. In this way, the reliability of the electrical connection between the touch driving electrodes TE can be improved.

[0194] Figure 9 Embodiments are illustrated in which two bridge electrodes BE parallel to each other are provided between touch drive electrodes TE adjacent to each other in the second direction DR2, but embodiments are not limited to Figure 10 the embodiments illustrated in FIG. 1.

[0195] Figure 4 Embodiments are illustrated in which the bridge electrode BE has a shape including one bend, but the shape of the bridge electrode BE according to embodiments is not limited to Figure 10 the shape illustrated in FIG. 1.

[0196] The touch drive electrodes TE and the reception electrodes RE can be spaced apart from each other.

[0197] The bridge electrode BE can be provided in a different conductive layer from the touch drive electrodes TE and the reception electrodes RE.

[0198] Each of the touch drive electrodes TE, the reception electrodes RE, and the bridge electrode BE can have a mesh shape or a shape of a mesh structure in a plan view. The dummy electrode DE can also have a mesh shape or a shape of a mesh structure in a plan view. In this way, the width of the emission area EA overlapping the touch drive electrodes TE, the reception electrodes RE, the dummy electrode DE, and the bridge electrode BE can be reduced, and thus, the degree to which the light emission efficiency of the emission area EA is reduced due to the touch drive electrodes TE, the reception electrodes RE, the dummy electrode DE, and the bridge electrode BE can be mitigated.

[0199] Figure 10 is an equivalent circuit diagram of an emission pixel driver according to an embodiment. Figure 11

[0200] Referring to Figure 10 , the emission pixel driver EPD of the circuit layer 120 can be electrically connected between the first power supply ELVDD and the light emitting element LE of the element layer 130. One of the light emitting elements LE of the element layer 130 can be electrically connected between one of the emission pixel drivers EPD of the circuit layer 120 and the second power supply ELVSS.

[0201] In an embodiment, the anode electrode of the light emitting element LE can be electrically connected to the emission pixel driver EPD, and the second power supply ELVSS having a voltage level lower than that of the first power supply ELVDD can be applied to the cathode electrode of the light emitting element LE.

[0202] The capacitor Cel connected in parallel to the light emitting element LE refers to a parasitic capacitance between the anode electrode and the cathode electrode.

[0203] ​The circuit layer 120 can include a first power line VDL that transmits a first power source ELVDD, a gate initialization voltage line VGIL that transmits a gate initialization voltage VGINT, and an anode initialization voltage line VAIL that transmits an anode initialization voltage VAINT.

[0204] The circuit layer 120 can further include a scan write line GWL that transmits a scan write signal GW, a scan initialization line GIL that transmits a scan initialization signal GI, an emission control line ECL that transmits an emission control signal EC, and a gate control line GCL that transmits a gate control signal GC.

[0205] One emission pixel driver EPD of the circuit layer 120 can include a first transistor T1 that generates a driving current for driving a light emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one capacitor PC1.

[0206] The first transistor T1 can be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (e.g., a source electrode) of the first transistor T1. The second node N2 is electrically connected to a second electrode (e.g., a drain electrode) of the first transistor T1.

[0207] The first node N1 can be electrically connected to the first power line VDL through a fifth transistor T5.

[0208] The second node N2 can be electrically connected to an anode electrode of the light emitting element LE through a sixth transistor T6.

[0209] The pixel capacitor PC1 can be electrically connected between the first power line VDL and a third node N3. The third node N3 is electrically connected to a gate electrode of the first transistor T1.

[0210] That is, the gate electrode of the first transistor T1 can be electrically connected to the first power line VDL through the pixel capacitor PC1.

[0211] Accordingly, the potential of the gate electrode of the first transistor T1 can be maintained as a voltage charged in the pixel capacitor PC1.

[0212] The second transistor T2 can be electrically connected between the data line DL and the first node N1.

[0213] The second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0214] That is, the first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0215] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0216] The fifth transistor T5 can be electrically connected between the first node N1 and the first power line VDL.

[0217] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light emitting element LE.

[0218] That is, the fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0219] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LE.

[0220] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emission control signal EC of the emission control line ECL.

[0221] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be a voltage difference between the first power ELVDD and the data signal Vdata.

[0222] In this case, when the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., gate-source voltage difference) is greater than or equal to a threshold voltage, the first transistor T1 is turned on, so that a drain-source current of the first transistor T1 corresponding to the data signal Vdata can be generated.

[0223] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first power ELVDD, the first transistor T1, the light emitting element LE, and the second power ELVSS can be connected in series to each other. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0224] Accordingly, the light emitting element LE can emit light of a luminance corresponding to the data signal Vdata.

[0225] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0226] The third transistor T3 can include a plurality of sub-transistors connected in series to each other. In an embodiment, for example, the third transistor T3 can include a first sub-transistor T31 and a second sub-transistor T32.

[0227] The first electrode of the first sub transistor T31 can be connected to the gate electrode of the first transistor T1, the second electrode of the first sub transistor T31 can be connected to the first electrode of the second sub transistor T32, and the second electrode of the second sub transistor T32 can be connected to the second electrode of the first transistor T1.

[0228] In this embodiment, the potential of the gate electrode of the first transistor T1 can be effectively prevented from changing due to a leakage current caused by the non-conducting third transistor T3.

[0229] The first sub transistor T31 and the second sub transistor T32 can be turned on by a scan write signal GW of a scan write line GWL.

[0230] When the first sub transistor T31 and the second sub transistor T32 are turned on, a voltage difference between the second node N2 and the third node N3 can be initialized.

[0231] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0232] The fourth transistor T4 can include a plurality of sub transistors connected in series to each other. In an embodiment, for example, the fourth transistor T4 can include a third sub transistor T41 and a fourth sub transistor T42.

[0233] The first electrode of the third sub transistor T41 can be connected to the gate electrode of the first transistor T1, the second electrode of the third sub transistor T41 can be connected to the first electrode of the fourth sub transistor T42, and the second electrode of the fourth sub transistor T42 can be connected to the gate initialization voltage line VGIL.

[0234] In this embodiment, the potential of the gate electrode of the first transistor T1 can be effectively prevented from changing due to a leakage current caused by the non-conducting fourth transistor T4.

[0235] The third sub transistor T41 and the fourth sub transistor T42 can be turned on by a scan initialization signal GI of a scan initialization line GIL.

[0236] When the third sub transistor T41 and the fourth sub transistor T42 are turned on, the potential of the third node N3 can be initialized to the gate initialization voltage VGINT.

[0237] The seventh transistor T7 can be electrically connected between the fourth node N4 and an anode initialization voltage line VAIL. That is, the seventh transistor T7 can be electrically connected between the anode electrode of the light emitting element LE and the anode initialization voltage line VAIL.

[0238] The seventh transistor T7 can be turned on by a gate control signal GC of a gate control line GCL.

[0239] The potential of the fourth node N4 can be initialized to the anode initialization voltage VAINT through the turned-on seventh transistor T7.

[0240] As Figure 9 illustrated in FIG. 1A, according to an embodiment, the first to seventh transistors T1 to T7 can be provided as P-type metal oxide semiconductor field effect transistors (MOSFETs), but are not limited thereto.

[0241] Figure 11 is a cross-sectional view taken along a line F-F' of Figure 10 according to an embodiment. Figure 10

[0242] Referring to Figure 11 , the display panel 100 of the display device 10 according to an embodiment can include a substrate 110, a circuit layer 120 disposed on the substrate 110, and an element layer 130 disposed on the circuit layer 120.

[0243] The display panel 100 of the display device 10 according to an embodiment can further include a sealing layer 140 disposed on the element layer 130, a touch sensor layer 150 disposed on the sealing layer 140, and a polarizing layer 160 disposed on the touch sensor layer 150.

[0244] The circuit layer 120 can include an interlayer insulating layer 124 disposed on the substrate 110, a first source / drain conductive layer (including a first anode connection electrode ANE1) disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source / drain conductive layer, a second source / drain conductive layer (including a data line DL and a second anode connection electrode ANE2) disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source / drain conductive layer.

[0245] According to an embodiment, the circuit layer 120 can further include a first semiconductor layer (including channel portions CH1 and CH6 and electrode portions E11, E21, E16, and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1 and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (including a capacitor electrode CAE) disposed on the second gate insulating layer 123.

[0246] According to an embodiment, the interlayer insulating layer 124 can be disposed on the second gate insulating layer 123 and cover the second gate conductive layer.

[0247] ​The circuit layer 120 can further include a buffer layer 121 covering the substrate 110.

[0248] In an embodiment, a first semiconductor layer can be disposed on the buffer layer 121.

[0249] The circuit layer 120 can include emission pixel drivers EPD corresponding to the emission areas EA, respectively.

[0250] Each of the emission pixel drivers EPD can include a first transistor T1, second to seventh transistors T2 to T7 (see Figure 10 ) electrically connected to the first transistor T1, and at least one capacitor PC1 (see Figure 10 ).

[0251] Figure 10 A portion corresponding to the light emitting element LE of Figure 10 and the first transistor T1 and the sixth transistor T6 of the emission pixel driver EPD is illustrated.

[0252] The first semiconductor layer disposed on the buffer layer 121 can include a channel portion CH1 or CH6, a first electrode portion E11 or E16, and a second electrode portion E21 or E26 of each of the first to seventh transistors T1 to T7.

[0253] In the first transistor T1 and the sixth transistor T6, the first electrode portions E11 and E16 can be connected to one end of the channel portions CH1 and CH6, respectively, and the second electrode portions E21 and E26 can be connected to the other end of the channel portions CH1 and CH6, respectively.

[0254] The second electrode portion E21 of the first transistor T1 can be connected to the first electrode portion E16 of the sixth transistor T6.

[0255] The first gate conductive layer disposed on the first gate insulating layer 122 can include a gate electrode G1 or G6 of each of the first to seventh transistors T1 to T7.

[0256] In the first transistor T1 and the sixth transistor T6, the gate electrodes G1 and G6 can overlap the channel portions CH1 and CH6, respectively.

[0257] Figure 12 The second transistor T2, the first sub-transistor T31, the second sub-transistor T32, the third sub-transistor T41, the fourth sub-transistor T42, the fifth transistor T5, and the seventh transistor T7 of the emission pixel driver EPD of

[0258] The second gate conductive layer disposed on the second gate insulating layer 123 can include a capacitor electrode CAE.

[0259] The capacitor electrode CAE can overlap the gate electrode G1 of the first transistor T1.

[0260] Accordingly, a pixel capacitor PC1 (see Figure 4 ) can be provided by an overlapping area between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0261] The first source / drain conductive layer disposed on the interlayer insulating layer 124 can include a first anode connection electrode ANCE1.

[0262] The first anode connection electrode ANCE1 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 through a first anode connection hole ANCH1.

[0263] The second source / drain conductive layer disposed on the first planarization layer 125 can include a second anode connection electrode ANCE2.

[0264] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through a second anode connection hole ANCH2.

[0265] The anode electrode 131 of the element layer 130 can be disposed on the second planarization layer 126 and can be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3.

[0266] Accordingly, the anode electrode 131 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0267] The element layer 130 disposed on the circuit layer 120 can include light emitting elements LE disposed in the emission areas EA1, EA2, and EA3, respectively.

[0268] Each of the light emitting elements LE can have a structure in which the light emitting layer 133 is disposed between the anode electrode 131 and the cathode electrode 134 facing each other.

[0269] According to an embodiment, the element layer 130 can include the anode electrode 131 disposed in the emission areas EA, the pixel definition layer 132 disposed in the non-emission areas NEA and covering edges of the anode electrode 131, the spacer layer 132' disposed on a portion of the pixel definition layer 132, the light emitting layer 133 disposed on the anode electrode 131, respectively, and the cathode electrode 134 disposed on the light emitting layer 133, the pixel definition layer 132, and the spacer layer 132'.

[0270] Alternatively, the light emitting element LE can further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133, and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134.

[0271] The sealing layer 140 can cover the element layer 130.

[0272] The sealing layer 140 can prevent oxygen or moisture from penetrating into the element layer 130, and can mitigate an electrical or physical shock to the circuit layer 120 and the element layer 130.

[0273] The sealing layer 140 can include a first sealing layer 141 covering the element layer 130 and including an inorganic insulating material, a second sealing layer 142 disposed on the first sealing layer 141, overlapping the element layer 130, and including an organic insulating material, and a third sealing layer 143 disposed on the first sealing layer 141, covering the second sealing layer 142, and including an inorganic insulating material.

[0274] The touch sensor layer 150 can be disposed on the sealing layer 140.

[0275] The touch sensor layer 150 can include a touch buffer layer 151 disposed on the sealing layer 140, a first touch conductive layer (including a bridge electrode BE) disposed on the touch buffer layer 151, a touch interlayer insulating layer 152 covering the first touch conductive layer, a second touch conductive layer (including a reception electrode RE and a touch driving electrode TE) disposed on the touch interlayer insulating layer 152, and a touch planarization layer 153 covering the second touch conductive layer.

[0276] The first touch conductive layer disposed on the touch buffer layer 151 can include the bridge electrode BE.

[0277] The second touch conductive layer disposed on the touch interlayer insulating layer 152 can include the touch driving electrode TE and the reception electrode RE.

[0278] Like the touch driving electrode TE and the reception electrode RE, a dummy electrode DE disposed inside each of the touch driving electrode TE and the reception electrode RE, a first driving line TL1 and a second driving line TL2 connected to the touch driving electrode TE, and a sensing line RL connected to the reception electrode RE can be disposed at the second touch conductive layer disposed on the touch interlayer insulating layer 152.

[0279] The touch driving electrode TE can be electrically connected to the bridge electrode BE through a touch electrode connection hole TCNT defined or formed by passing through the touch interlayer insulating layer 152.

[0280] The touch buffer layer 151 can include an inorganic insulating material.

[0281] According to an embodiment, each of the touch interlayer insulating layer 152 and the touch planarization layer 153 can include an organic insulating material.

[0282] The polarizing layer 160 can be disposed on the touch sensor layer 150.

[0283] In an embodiment, Figure 12 The emission pixel driver EPD includes the first through seventh transistors T1 through T7 provided as P-type MOSFETs. However, this is merely an example, and some of the first through seventh transistors T1 through T7 can also be provided as N-type MOSFETs. In an embodiment, for example, the third transistor T3 and the fourth transistor T4 can be provided as N-type MOSFETs.

[0284] Figure 10 is a circuit diagram of an emission pixel driver according to an embodiment. Figure 10 of the emission pixel driver.

[0285] Except that the third transistor T3 and the fourth transistor T4 among the first through seventh transistors T1 through T7 of the emission pixel driver EPD are provided as N-type MOSFETs, the circuit layer 120 of the display panel 100 according to Figure 12 the embodiment illustrated in Figure 13 the circuit layer 120 of the display panel 100 according to the embodiment illustrated in Figure 12 will be omitted below.

[0286] According to an embodiment, Figure 9 The third transistor T3 can be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0287] The third transistor T3 is provided as an N-type MOSFET, and accordingly, can be turned on by a gate control signal GC of a gate control line GCL.

[0288] A voltage difference between the second node N2 and the third node N3 can be initialized through the turned-on third transistor T3.

[0289] In such an embodiment, the seventh transistor T7 can be turned on by a bias control signal GB of a bias control line GBL, instead of being turned on by a gate control signal GC of a gate control line GCL.

[0290] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0291] The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0292] The potential of the third node N3 can be initialized through the turned-on fourth transistor T4.

[0293] Figure 13 is a cross-sectional view taken along the line F-F’ of the display panel 100 according to Figure 11 . Figure 11 is a cross-sectional view taken along the line F-F’ of the display panel 100 according to

[0294] The circuit layer 120 of the display panel 100 according to the embodiment of Figure 13 is substantially the same as the circuit layer 120 of the display panel 100 according to the embodiment illustrated in Figure 12 , and thus, any repetitive detailed description of elements identical or similar to those described above with reference to Figure 13 will be omitted or simplified below.

[0295] Figure 13 corresponding portions of the first transistor T1, the second transistor T2, and the sixth transistor T6 provided as P-type MOSFETs and the fourth transistor T4 provided as N-type MOSFET among the transistors T1 to T7 (see Figure 13 ) of the emission pixel driver EPD and the light emitting element LE are illustrated.

[0296] According to the embodiment of Figure 13 , the circuit layer 120 can include an interlayer insulating layer 124 disposed on the substrate 110, a first source / drain conductive layer (including a first anode connection electrode ANCE1, a gate initialization voltage line VGIL, a data connection electrode DCE, and a node auxiliary connection electrode NACE) disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source / drain conductive layer, a second source / drain conductive layer (including a data line DL and a second anode connection electrode ANCE2) disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source / drain conductive layer.

[0297] According to the embodiment of Figure 12According to an embodiment of the present disclosure, the circuit layer 120 can further include a first semiconductor layer (including channel portions CH1, CH2, and CH6 and electrode portions E11, E21, E12, E22, E16, and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1, G2, and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (including a capacitor electrode CAE and a second light-blocking layer LB2) disposed on the second gate insulating layer 123.

[0298] According to an embodiment of the present disclosure, the circuit layer 120 can further include a first semiconductor layer (including channel portions CH1, CH2, and CH6 and electrode portions E11, E21, E12, E22, E16, and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1, G2, and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (including a capacitor electrode CAE and a second light-blocking layer LB2) disposed on the second gate insulating layer 123. Figure 12

[0299] According to an embodiment of the present disclosure, the circuit layer 120 can further include a first semiconductor layer (including channel portions CH1, CH2, and CH6 and electrode portions E11, E21, E12, E22, E16, and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1, G2, and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (including a capacitor electrode CAE and a second light-blocking layer LB2) disposed on the second gate insulating layer 123. Figure 12 According to an embodiment of the present disclosure, the circuit layer 120 can further include a first semiconductor layer (including channel portions CH1, CH2, and CH6 and electrode portions E11, E21, E12, E22, E16, and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (including gate electrodes G1, G2, and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (including a capacitor electrode CAE and a second light-blocking layer LB2) disposed on the second gate insulating layer 123.

[0300] Figure 12 The first semiconductor layer disposed on the buffer layer 121 can include a channel portion CH1, CH2, or CH6, a first electrode portion E11, E12, or E16, and a second electrode portion E21, E22, or E26 of each of the first to seventh transistors T1 to T7 provided as P-type MOSFETs. Figure 12 The first gate conductive layer disposed on the first gate insulating layer 122 can include a gate electrode G1, G2, or G6 of each of the first to seventh transistors T1 to T7 provided as P-type MOSFETs.

[0301] Figure 12 The fifth transistor T5 and the seventh transistor T7 have the same structure as that of the first to sixth transistors T1 to T6, and thus, any repetitive detailed description thereof will be omitted below. Figure 12

[0302] The fifth transistor T5 and the seventh transistor T7 have the same structure as that of the first to sixth transistors T1 to T6, and thus, any repetitive detailed description thereof will be omitted below.

[0303] ​​​​In the first transistor T1, the second transistor T2, and the sixth transistor T6, the channel portions CH1, CH2, and CH6 can overlap with the gate electrodes G1, G2, and G6, respectively.

[0304] The channel portion CH1 of the first transistor T1 can overlap with the first light-blocking layer LB1 provided below the buffer layer 121.

[0305] In the first transistor T1, the second transistor T2, and the sixth transistor T6, the first electrode portions E11, E12, and E16 can be connected to one end of the channel portions CH1, CH2, and CH6, respectively, and the second electrode portions E21, E22, and E26 can be connected to the other end of the channel portions CH1, CH2, and CH6, respectively.

[0306] The first electrode portion E11 of the first transistor T1 can be connected to the second electrode portion E22 of the second transistor T2.

[0307] The second electrode portion E21 of the first transistor T1 can be connected to the first electrode portion E16 of the sixth transistor T6.

[0308] The second gate conductive layer provided on the second gate insulating layer 123 can include a capacitor electrode CAE and a second light-blocking layer LB2.

[0309] The second semiconductor layer provided on the auxiliary interlayer insulating layer 127 can include a channel portion CH4, a first electrode portion E14, and a second electrode portion E24 of each of the third transistor T3 (see Figure 13 ) and the fourth transistor T4, which are provided as N-type MOSFETs.

[0310] The third gate conductive layer provided on the third gate insulating layer 128 can include a gate electrode G4 of each of the third transistor T3 (see Figure 11 ) and the fourth transistor T4, which are provided as N-type MOSFETs.

[0311] In each of the third transistor T3 (see Figure 14 ) and the fourth transistor T4, the channel portion CH4 can overlap with the second light-blocking layer LB2 provided below the auxiliary interlayer insulating layer 127.

[0312] The channel portion CH4 of the fourth transistor T4 can overlap with the gate electrode G4 of the fourth transistor T4.

[0313] The first electrode portion E14 of the fourth transistor T4 can be connected to one end of the channel portion CH4 of the fourth transistor T4, and the second electrode portion E24 of the fourth transistor T4 can be connected to the other end of the channel portion CH4 of the fourth transistor T4.

[0314] The third transistor T3 and the fourth transistor T4 are provided as the same N-type MOSFET, and therefore, repeated descriptions will be omitted below.

[0315] The first source / drain conductive layer disposed on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1, a data connection electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0316] The second source / drain conductive layer disposed on the first planarization layer 125 may include a second anode connection electrode ANCE2 and a data line DL.

[0317] The data connection electrode DCE can be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data connection hole DCH1.

[0318] The data cable DL can be electrically connected to the data connection electrode DCE through the second data connection hole DCH2.

[0319] Accordingly, the data line DL can be electrically connected to the first electrode portion E12 of the second transistor T2 via the data connection electrode DCE.

[0320] The gate initialization voltage line VGIL can be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0321] The node auxiliary connection electrode NACE can be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0322] according to Figure 3 In the embodiment illustrated, the element layer 130, sealing layer 140, touch sensor layer 150, and polarization layer 160 of the display panel 100 are in accordance with... Figure 3 The display panels 100 of the embodiments illustrated herein are substantially the same, and therefore any repeated detailed descriptions thereof will be omitted below.

[0323] Figure 14 The illustration is based on an embodiment. Figure 14 Plan view of part D.

[0324] like Figure 10 As illustrated in the figure, the substrate 110 of the display panel 100 of the display device 10 according to the embodiment may include a display area DA and a non-display area NDA, and the display area DA may include a front display area FSA and a peripheral display area PSA disposed around the front display area FSA and having a curved shape.

[0325] The peripheral display area PSA can include a first side area SS1 contacting a first side SD1 of the front display area FSA, a second side area SS2 contacting a second side SD2 of the front display area FSA, a third side area SS3 contacting a third side SD3 of the front display area FSA, a fourth side area SS4 contacting a fourth side SD4 of the front display area FSA, a first corner area CS1 contacting a vertex at which the first side SD1 and the third side SD3 connect to each other and disposed between the first side area SS1 and the third side area SS3, a second corner area CS2 contacting a vertex at which the second side SD2 and the third side SD3 connect to each other and disposed between the second side area SS2 and the third side area SS3, a third corner area CS3 contacting a vertex at which the second side SD2 and the fourth side SD4 connect to each other and disposed between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 contacting a vertex at which the first side SD1 and the fourth side SD4 connect to each other and disposed between the first side area SS1 and the fourth side area SS4.

[0326] The circuit layer 120 of the display panel 100 of the display device 10 according to an embodiment can include four alignment marks ALMS (ALM1, ALM2, ALM3, and ALM4) disposed in the non-display area NDA and respectively adjacent to the four corner points VT1, VT2, VT3, and VT4 of the main area MA.

[0327] The four alignment marks ALMS (ALM1, ALM2, ALM3, and ALM4) can include a first alignment mark ALM1 disposed adjacent to the first corner point VT1 of the main area MA and the first corner area CS1 of the peripheral display area PSA, a second alignment mark ALM2 disposed adjacent to the second corner point VT2 of the main area MA and the second corner area CS2 of the peripheral display area PSA, a third alignment mark ALM3 disposed adjacent to the third corner point VT3 of the main area MA and the third corner area CS3 of the peripheral display area PSA, and a fourth alignment mark ALM4 disposed adjacent to the fourth corner point VT4 of the main area MA and the fourth corner area CS4 of the peripheral display area PSA.

[0328] The non-display area NDA of the substrate 110 of the display panel 100 of the display device 10 according to an embodiment can include a dam area DMA surrounding the display area DA and spaced apart from the display area DA.

[0329] Figure 11The corner portion of the second alignment mark ALM2 is illustrated as being disposed adjacent to a second corner area CS2 of the main area MA and a peripheral display area PSA of the display area DA (which is hereinafter referred to simply as a peripheral display area CS2_PSA).

[0330] In this embodiment, the first alignment mark ALM1, the third alignment mark ALM3, and the fourth alignment mark ALM4 disposed at portions of the non-display area NDA adjacent to the first corner point VT1, the third corner point VT3, and the fourth corner point VT4, respectively, are substantially the same as the second alignment mark ALM2 disposed adjacent to the second corner point VT2, and the first corner area CS1, the third corner area CS3, and the fourth corner area CS4 of the peripheral display area PSA of the display area DA are substantially the same as the second corner area CS2, and thus any repetitive detailed description thereof will be omitted herein.

[0331] Reference Figure 12 The display panel 100 of the display device 10 according to the embodiment can further include one or more dam portions (DM1 and DM2) arranged in the dam area DMA of the non-display area NDA.

[0332] The circuit layer 120 of the display panel 100 of the display device 10 according to the embodiment can further include a power supply line VSPL disposed in the non-display area NDA to transmit a power source ELVDD or ELVSS (see Figure 13 , Figure 10 , Figure 12 and Figure 10 ) for driving the light emitting elements LE (see Figure 12 and Figure 10 ).

[0333] The power supply line VSPL can be disposed or formed to surround at least three sides of the edge of the display area DA, and can overlap the dam area DMA in a plan view.

[0334] The power supply line VSPL can transmit the first power source ELVDD (see Figure 12 and Figure 10 ) or the second power source ELVSS (see Figure 12 and Figure 10 ).

[0335] In an embodiment, for example, the power supply line VSPL can transmit the second power source ELVSS (see Figure 12 and Figure 3 ).

[0336] In another embodiment, for example, the power supply line VSPL can include a first power supply line VSPL1 to transmit the first power source ELVDD (see Figure 3 andFigure 3 a first power line that transmits a first power ELVDD (see Figure 3 and Figure 11 a second power line that transmits a second power ELVSS (see

[0337] According to an embodiment, the alignment marks ALMS (see Figure 13 ) including the second alignment mark ALM2 of the non-display area NDA can be spaced apart from the power line VSPL in a direction away from the display area DA. That is, the alignment marks ALMS (see Figure 11 ) including the second alignment mark ALM2 of the non-display area NDA can be disposed adjacent to the edge of the substrate 110.

[0338] Each of the alignment marks ALMS (see Figure 13 ) including the second alignment mark ALM2 can include two or more alignment keys EKY1, EKY2, and EKY3 spaced apart from each other.

[0339] Each of the two or more alignment keys EKY1, EKY2, and EKY3 can have one of two or more different polygonal patterns or shapes. Alternatively, the two or more alignment keys EKY1, EKY2, and EKY3 can have different patterns or shapes from each other.

[0340] In an embodiment, for example, a first alignment key EKY1 of the two or more alignment keys EKY1, EKY2, and EKY3 can have a cross pattern, a second alignment key EKY2 of the two or more alignment keys EKY1, EKY2, and EKY3 can have a W pattern, and a third alignment key EKY3 of the two or more alignment keys EKY1, EKY2, and EKY3 can have a belt pattern (or a belt shape) in which two rhombuses contact each other at their vertices.

[0341] The display panel 100 of the display device 10 according to an embodiment can further include a capping portion CPP overlapping the dam area DMA and spaced apart from the alignment marks ALMS (see Figure 11 ) including the second alignment mark ALM2.

[0342] The capping portion CPP is used to protect the inorganic insulating material located at the uppermost end of the one or more dam portions (DM1 and DM2) arranged in the dam area DMA from the etching process for disposing the second touch conductive layer (including the touch driving electrode TE and the receiving electrode RE, see Figure 13 and Figure 3 ).

[0343] According to an embodiment, one or more dam portions (DM1 and DM2) disposed in the dam area DMA are provided to limit a diffusion range of the organic insulating material of the second sealing layer 142 of the sealing layer 140, and have a relatively large step with the substrate 110. However, the touch interlayer insulating layer 152 of the touch sensor layer 150 includes an organic insulating material, and thus, the one or more dam portions (DM1 and DM2) can not be completely covered by the touch interlayer insulating layer 152. In this case, the inorganic insulating material of the portions (e.g., the touch buffer layer 151, the third sealing layer 143, and the first sealing layer 141) of the one or more dam portions (DM1 and DM2) not covered by the touch interlayer insulating layer 152 can be exposed to an etching process for setting the second touch conductive layer (including the touch driving electrodes TE and the receiving electrodes RE, see Figure 3 and Figure 3 ) and thus be easily damaged.

[0344] To prevent such damage to the inorganic insulating material in the portions of the one or more dam portions (DM1 and DM2), the display panel 100 according to an embodiment can include a capping portion CPP overlapping the dam area DMA.

[0345] The capping portion CPP can be disposed at the same layer (disposed in the same layer or directly disposed on the same layer) as the first touch conductive layer (including the bridge electrode BE, see Figure 3 and Figure 14 ).

[0346] According to an embodiment, the capping portions CPP can be spaced apart from each other and can be spaced apart from the alignment marks ALMS (e.g., ALM2 in Figure 3 such that the alignment marks ALMS (e.g., ALM2 in Figure 3 ) can be effectively prevented from being hidden (or covered) by the capping portions CPP.

[0347] In this embodiment, the capping portions CPP can be disposed as islands in which the capping portions CPP are respectively spaced apart from the alignment marks ALMS (e.g., ALM2 in Figure 3 ).

[0348] Figure 3 is a cross-sectional view taken along the line G-G' of Figure 17 . Figure 3 is a cross-sectional view taken along the line H-H' of Figure 3 .

[0349] As Figure 17As illustrated in the middle, according to an embodiment, the peripheral display area CS2_PSA of the display area DA, like the front surface display area FSA, includes an emission area EA. Accordingly, the element layer 130 can include light emitting elements LE disposed in the emission area EA of the peripheral display area CS2_PSA, and the circuit layer 120 can include emission pixel drivers EPD electrically connected with the light emitting elements LE of the peripheral display area CS2_PSA.

[0350] According to an embodiment, each of the one or more dam portions disposed in the dam area DMA of the non-display area NDA can include two or more dam layers DML11, DML21, and DML31; DML12, DML22, DML32, and DML42; DML13 and DML23; or DML14 and DML24.

[0351] Each of the two or more dam layers DML11, DML21, and DML31; DML12, DML22, DML32, and DML42; DML13 and DML23; or DML14 and DML24 can be disposed at the same layer as one of the first planarization layer 125, the second planarization layer 126, the pixel definition layer 132, and the spacer layer 132’ (see Figures 14 to 16 and Figures 14 to 16 ).

[0352] In an embodiment, for example, the one or more dam portions disposed in the dam area DMA can include a first dam portion DM1 surrounding the display area DA and a second dam portion DM2 surrounding the first dam portion DM1.

[0353] The first dam portion DM1 can include a first dam layer DML11 disposed at the same layer as the second planarization layer 126, a second dam layer DML21 disposed at the same layer as the pixel definition layer 132, and a third dam layer DML31 disposed at the same layer as the spacer layer 132’. Here, the layers disposed at the same layer as each other can correspond to a patterned portion of the same layer or multiple same layers formed using the same material during the same process.

[0354] The second dam portion DM2 can include a first dam layer DML12 disposed at the same layer as the first planarization layer 125, a second dam layer DML22 disposed at the same layer as the second planarization layer 126, a third dam layer DML32 disposed at the same layer as the pixel definition layer 132, and a fourth dam layer DML42 disposed at the same layer as the spacer layer 132’.

[0355] The one or more dam portions disposed in the dam area DMA can further include one or more auxiliary dam portions ADM1 and ADM2 arranged between the display area DA and the first dam portion DM1 and surrounding the display area DA.

[0356] The one or more auxiliary dam portions ADM1 and ADM2 can include first dam layers DML13 and DML14 disposed on the second planarization layer 126 and second dam layers DML23 and DML24 disposed on the first dam layers DML13 and DML14, respectively.

[0357] As an example, the one or more auxiliary dam portions ADM1 and ADM2 can include a first auxiliary dam portion ADM1 disposed adjacent to the display area DA and a second auxiliary dam portion ADM2 disposed between the first auxiliary dam portion ADM1 and the first dam portion DM1.

[0358] The first dam layers DML13 and DML14 of the first auxiliary dam portion ADM1 and the second auxiliary dam portion ADM2 can be disposed at the same layer as the pixel definition layer 132.

[0359] The second dam layers DML23 and DML24 of the first auxiliary dam portion ADM1 and the second auxiliary dam portion ADM2 can be disposed at the same layer as the spacer layer 132'.

[0360] According to an embodiment, the circuit layer 120 can include a power supply line VSPL overlapping the dam area DMA.

[0361] The portion of the power supply line VSPL overlapping the dam area DMA can include a first line layer VSPLL1 disposed at the same layer as the first source / drain conductive layer disposed on the interlayer insulating layer 124 and a second line layer VSPLL2 disposed at the same layer as the second source / drain conductive layer disposed on the first planarization layer 125.

[0362] In a region between the first dam portion DM1 and the second dam portion DM2 spaced apart from each other in the dam area DMA, the first planarization layer 125 is removed, and accordingly, the second line layer VSPLL2 can be in direct contact with the first line layer VSPLL1. Accordingly, the second line layer VSPLL2 can be electrically connected to the first line layer VSPLL1.

[0363] According to an embodiment, the circuit layer 120 can further include a cathode extension line 134' disposed in the non-display area NDA.

[0364] The cathode extension line 134' can be provided at the same layer as the anode electrode 131. That is, the cathode extension line 134' can be disposed on the second planarization layer 126.

[0365] When the power supply line VSPL transmits the second power ELVSS (see Figure 3 and Figure 18 ), the cathode extension line 134' can extend from the edge of the display area DA to the dam area DMA.

[0366] In the area between the first dam portion DM1 and the second auxiliary dam portion ADM2 spaced apart from each other, the second planarization layer 126 is removed, and accordingly, the cathode extension line 134' can be in direct contact with the second line layer VSPLL2 of the power supply line VSPL. Accordingly, the cathode extension line 134' can be electrically connected to the power supply line VSPL.

[0367] According to an embodiment, the capping portion CPP disposed on the touch buffer layer 151 can overlap all of the one or more dam portions DM1, DM2, ADM1, and ADM2.

[0368] Accordingly, even if some of the one or more dam portions DM1, DM2, ADM1, and ADM2 are not covered by the touch interlayer insulating layer 152 including the organic insulating material, the portion of the one or more dam portions DM1, DM2, ADM1, and ADM2 not covered by the touch interlayer insulating layer 152 can be protected from the etching process for disposing the second touch conductive layer (including the touch driving electrode TE and the receiving electrode RE) by the capping portion CPP.

[0369] According to an embodiment, the first planarization layer 125, the second planarization layer 126, the pixel definition layer 132, the spacer layer 132', the touch interlayer insulating layer 152, and the touch planarization layer 153 including the organic insulating material can be spaced apart from the edge of the substrate 110 so that penetration of oxygen or moisture from the edge of the substrate 110 through the organic insulating material can be effectively prevented.

[0370] Accordingly, as Figure 3 illustrated in FIG. 11, according to an embodiment, the alignment mark ALMS (see Figure 19 ) (for example, the second alignment key EKY2 of the second alignment mark ALM2, which is hereinafter simply referred to as the alignment mark EKY2_ALM2) can be defined by a conductive layer covered by the interlayer insulating layer 124 including the inorganic insulating material.

[0371] That is, according to an embodiment, the alignment mark ALMS (see Figure 18 ) (for example, EKY2_ALM2) can be defined by the first gate conductive layer (including the gate electrodes G1 and G6, see Figure 3 ) disposed on the first gate insulating layer 122 and the second gate conductive layer (including the capacitor electrode CAE, see Figure 18The embossed pattern is set on the same layer to define the area.

[0372] Alternatively, according to an embodiment, alignment markers ALMS (see...) Figure 19 (For example, EKY2_ALM2) can be formed by a first gate conductive layer (including gate electrodes G1, G2 and G6, see [reference]) disposed on the first gate insulating layer 122. Figures 14 to 16 The second gate conductive layer (including capacitor electrode CAE and second light-blocking layer LB2, see below) is disposed on the second gate insulating layer 123. Figures 14 to 16 ) and the third gate conductive layer (including gate electrode G4, see below) disposed on the third gate insulating layer 128 Figure 19 The embossed pattern is set on the same layer to define the area.

[0373] According to an embodiment, the alignment mark ALMS (see...) Figure 3 (For example, EKY2_ALM2) can be disposed adjacent to the edge of substrate 110, so that alignment marks ALMS (see...) can be effectively prevented from being placed. Figure 18 (For example, EKY2_ALM2) is hidden or covered by other conductive layers disposed on the interlayer insulating layer 124. That is, the alignment mark ALMS (see Figure 3 (For example, EKY2_ALM2) can be set at the corner points VT1, VT2, VT3, and VT4 between the dam area DMA and the main area MA (see...) Figure 3 (e.g., VT2) between.

[0374] according to Figures 14 to 19 In one embodiment, four alignment markers ALMS (see Figure 3 (For example, ALM2) is provided with a raised pattern at the four corner points VT1, VT2, VT3 and VT4 of the main area MA (see...). Figure 20 (For example, VT2) and the dam area DMA, and the alignment marker ALMS (see Figure 3 (For example, ALM2) includes a first alignment key EKY1, a second alignment key EKY2, and a third alignment key EKY3, each having a cross pattern, a W pattern, and a stripe pattern, respectively, and correspondingly, due to the alignment mark ALMS (see... Figure 21 The settings may have limitations in reducing the width of the non-display area NDA.

[0375] Figure 20 The illustration is based on an embodiment. Figure 3 Plan view of part D.

[0376] In addition to the alignment marker ALMS (see...) Figure 20Each of the alignment marks ALMS (see FIG. 1) (e.g., the second alignment mark ALM2) according to the embodiment illustrated in Figure 21 The display device 10 according to the embodiment illustrated in Figures 14 to 19 is substantially the same as the display device 10 according to the embodiment illustrated in Figures 14 to 19 and thus, any repetitive detailed description of elements identical or similar to those described above with reference to

[0377] In the embodiment, the rectangular pattern of the fourth alignment key EKY4 and the rectangular pattern of the fifth alignment key EKY5 can be arranged parallel to each other.

[0378] In this embodiment, the width of each of the alignment marks ALMS (see Figure 20 ) (e.g., the second alignment mark ALM2) can be reduced, and thus, the width of the non-display area NDA can be reduced.

[0379] Figure 3 is a plan view illustrating a portion D of the display device 10 according to the embodiment. Figure 3 is a cross-sectional view taken along the line I-I’ of Figure 3 ​ The display device 10 according to the embodiment illustrated in

[0380] Except that the first, second, and third alignment keys IKY1, IKY2, and IKY3 of each of the alignment marks ALMS (see ​ ) (e.g., the second alignment mark ALM2) are defined by an engraved pattern defined or formed by the power supply line VSPL instead of a relief pattern, the display device 10 according to the embodiment illustrated in ​ and ​ is substantially the same as the display device 10 according to the embodiment illustrated in ​ and thus, any repetitive detailed description of elements identical or similar to those described above with reference to ​ will be omitted below.

[0381] As illustrated in ​ , according to the embodiment, the portion of the power supply line VSPL overlapping the dam area DMA can include a first wire layer VSPLL1 disposed at the same layer as the first source / drain conductive layer disposed on the interlayer insulating layer 124 and a second wire layer VSPLL2 disposed at the same layer as the second source / drain conductive layer disposed on the first planarization layer 125.

[0382] ​Further, in the region between the first dam portion DM1 and the second dam portion DM2 spaced apart from each other in the dam region DMA, the second line layer VSPLL2 can be in direct contact with the first line layer VSPLL1.

[0383] That is, the portion of the power supply line VSPL whose region between the first dam portion DM1 and the second dam portion DM2 spaced apart from each other overlaps can include the first line layer VSPLL1 and the second line layer VSPLL2 which are sequentially stacked.

[0384] The first, second, and third alignment keys IKY1, IKY2, and IKY3 of each of the alignment marks ALMS (see ​ ) (e.g., the second alignment mark ALM2) can be defined by an engraved pattern defined or formed by passing through the first line layer VSPLL1 and the second line layer VSPLL2 which are sequentially stacked.

[0385] In such an embodiment, as illustrated in ​ , the alignment marks ALMS (see ​ ) (e.g., ALM2) can be disposed in the region between the first dam portion DM1 and the second dam portion DM2 spaced apart from each other in the dam region DMA, and thus, an increase in the width of the non-display region NDA due to the disposition of the alignment marks ALMS (see ​ ) can be effectively prevented.

[0386] According to the embodiment illustrated in ​ , the capping portions CPP disposed in the dam region DMA can be disposed in an island shape in which they are spaced apart from the alignment marks ALMS (see ​ ). In such an embodiment, the influence of static electricity introduced into the edge of the substrate 110 on the capping portions CPP can increase.

[0387] ​ is a plan view of a portion D of ​ illustrated according to an embodiment. ​ is a cross-sectional view taken along the line J-J' of ​ .

[0388] The display device 10 according to the embodiment illustrated in ​ and ​ is the same as the display device 10 according to the embodiment illustrated in ​ except that the display panel 100 of the display device 10 further includes capping connection portions CPCN connecting the capping portions CPP to each other, having a width smaller than the width of the capping portions CPP, and being spaced apart from the alignment marks ALMS (see ​The display apparatus 10 of the embodiment illustrated in FIG. 1 is substantially the same as the display apparatus 10 of the embodiment illustrated in FIG. 2, and thus, detailed descriptions of any repeated elements of the elements described above with reference to the embodiment illustrated in FIG. 2 will be omitted below. ​ Any repeated detailed descriptions of elements described above with reference to the embodiment illustrated in FIG. 2.

[0389] In an embodiment, as illustrated in FIG. 2, the cover portions CPP can be spaced apart from the alignment marks ALMS (see, e.g., ALM2) in a direction perpendicular to the extension direction of the dam region DMA. ​ ​

[0390] Each of the cover portions CPP can be disposed to have a first line width LWD1 in a direction perpendicular to the extension direction of the dam region DMA.

[0391] The cover connection portions CPCN can be disposed in parallel with the alignment marks ALMS (see, e.g., ALM2) in the extension direction of the dam region DMA, and can connect adjacent ones of the cover portions CPP to each other. ​

[0392] The cover connection portions CPCN can be spaced apart from the alignment marks ALMS (see, e.g., ALM2) in a direction perpendicular to the extension direction of the dam region DMA, and can be disposed to have a second line width LWD2 smaller than the first line width LWD1. ​

[0393] In such an embodiment in which the cover connection portions CPCN are provided, the cover portions CPP can have a closed curve shape rather than an island shape, and thus, the influence of static electricity can be reduced.

[0394] The present disclosure should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0395] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the present disclosure as defined by the following claims.​​​​

Claims

1. A display device comprising: a display panel that emits light to display an image, wherein the display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer, wherein a main area of the substrate includes a display area in which an emission area is arranged, and a non-display area disposed around the display area, wherein the display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape, wherein the element layer includes light emitting elements respectively disposed in the emission area, wherein the circuit layer includes emission pixel drivers electrically connected to the light emitting elements, respectively, and an alignment mark disposed in the non-display area, wherein an edge of the main area includes four corner points at which respective sides of the main area extending in different directions are connected to each other, and wherein the alignment mark is disposed adjacent to a corresponding one of the four corner points.

2. The display device according to claim 1, wherein the front display area includes a first side and a second side extending in a first direction and opposite to each other, and a third side and a fourth side extending in a second direction crossing the first direction and opposite to each other, wherein the peripheral display area includes: a first side area, a second side area, a third side area, and a fourth side area, which are in contact with the first side, the second side, the third side, and the fourth side of the front display area, respectively; a first corner area which is in contact with a vertex at which the first side and the third side are connected to each other and is disposed between the first side area and the third side area; a second corner area which is in contact with a vertex at which the second side and the third side are connected to each other and is disposed between the second side area and the third side area; a third corner area which is in contact with a vertex at which the second side and the fourth side are connected to each other and is disposed between the second side area and the fourth side area; and a fourth corner area which is in contact with a vertex at which the first side and the fourth side are connected to each other and is disposed between the first side area and the fourth side area, and wherein the alignment mark includes at least one selected from: a first alignment mark disposed adjacent to the first corner area; a second alignment mark disposed adjacent to the second corner area; a third alignment mark disposed adjacent to the third corner area; and a fourth alignment mark disposed adjacent to the fourth corner area.

3. The display device according to claim 1, wherein the display panel further includes: a sealing layer disposed on the element layer; a touch sensor layer disposed on the sealing layer; and one or more dam portions arranged in a dam area of the non-display area surrounding the display area and spaced apart from the display area, wherein the circuit layer includes: an interlayer insulating layer disposed on the substrate; a first source / drain conductive layer disposed on the interlayer insulating layer; a first planarization layer covering the first source / drain conductive layer; a second source / drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source / drain conductive layer, wherein the element layer further includes: a pixel-defining layer disposed on the circuit layer and overlapping with areas between the emission regions spaced apart from each other; and a spacer layer disposed on portions of the pixel-defining layer, wherein the touch sensor layer includes: a touch buffer layer disposed on the sealing layer; a first touch conductive layer disposed on the touch buffer layer; a touch interlayer insulating layer covering the first touch conductive layer; a second touch conductive layer disposed on the touch interlayer insulating layer; and a touch planarization layer covering the second touch conductive layer, wherein each of the one or more dam portions includes two or more dam layers, and wherein each of the two or more dam layers is disposed at the same layer as a corresponding one of the first planarization layer, the second planarization layer, the pixel-defining layer, and the spacer layer, wherein the touch interlayer insulating layer includes an organic insulating material, and wherein the display panel further includes: a cap portion disposed at the same layer as the first touch conductive layer, overlapping with the dam region, and spaced apart from the alignment mark in a plan view.

4. The display device according to claim 3, wherein The display panel further includes: a cap connection portion connecting adjacent ones of the cap portions to each other, disposed to have a width smaller than that of the cap portion, and spaced apart from the alignment mark in the plan view.

5. The display device according to claim 3, wherein The circuit layer further includes: a power line disposed in the non-display region, wherein the power line transmits a power source for driving the light emitting element, wherein a portion of the power line overlapping with the dam region includes: a first line layer disposed at the same layer as the first source / drain conductive layer; and a second line layer disposed at the same layer as the second source / drain conductive layer and in contact with the first line layer, and wherein the alignment mark is defined by an engraved pattern defined by the first line layer and the second line layer stacked sequentially.

6. The display device according to claim 3, wherein The circuit layer further includes: a first semiconductor layer disposed on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; and a second gate conductive layer disposed on the second gate insulating layer.

7. The display device of claim 6, wherein, The interlayer insulating layer covers the second gate conductive layer, and wherein the alignment mark is defined by a relief pattern disposed at the same layer as one of the first gate conductive layer and the second gate conductive layer.

8. The display device of claim 6, wherein, The circuit layer further includes: an auxiliary interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer disposed on the auxiliary interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; and a third gate conductive layer disposed on the third gate insulating layer and covered by the interlayer insulating layer, and wherein the alignment mark is defined by a relief pattern disposed at the same layer as one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer.

9. The display device according to any one of claims 3 to 8, further comprising: a support supporting the display panel; and a cover window disposed on the display panel and coupled to the support, wherein the cover window is provided with an alignment hole corresponding to the alignment mark defined therein, and wherein the peripheral display area has a shape bent toward the support.

10. The display device according to any one of claims 3 to 8, wherein, The alignment mark includes two or more alignment keys spaced apart from each other.

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