Testing device for RK3568 core board

Abstract

The utility model discloses a testing device for an RK3568 core board, which comprises a testing mainboard and a core board to be tested, the testing mainboard is connected with the core board to be tested through a BTB connector, the testing mainboard is provided with a testing main control chip U8, a power supply circuit and a power consumption detection circuit, the power supply circuit is connected with the core board to be tested through the BTB connector, and the power consumption detection circuit is connected with the testing main control chip U8. The test main control chip U8 and the power consumption detection circuit are respectively connected with the power supply circuit, the power consumption detection circuit comprises a voltage acquisition circuit, a current acquisition circuit and a power consumption display circuit, and the voltage acquisition circuit, the current acquisition circuit and the power consumption display circuit are respectively and electrically connected with the test main control chip U8. Total current and real-time voltage consumed by power supply input are acquired through the voltage acquisition circuit and the current acquisition circuit, the test main control chip U8 converts the total current and the real-time voltage, and the voltage and the current are displayed through the power consumption display circuit, so that power consumption is monitored in real time, and troubleshooting is facilitated; by integrating various test interfaces, an additional independent connection module is not needed for testing, and the test speed is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to core board testing arrangement technical field especially is related to a kind of testing device for RK3568 core board. BACKGROUND

[0002] RK3568 core board is the small volume development board based on the RK3568J / RK3568B2 processor of Rui Chip, when developing test, developer usually needs to use multiple independent modules to test the different functions and interfaces of RK3568 core board, not only increase the demand of hardware, also make the test process become tedious and time consumption is larger, in the process of testing, it is difficult to monitor hardware power consumption in real time, cannot obtain detailed power consumption data, and in the process of debugging, hardware is often manually operated or through complex software instruction to switch system mode, test efficiency is low, operation is complex, therefore it is necessary to improve. SUMMARY

[0003] In view of the deficiencies in the prior art, the utility model aims at providing a kind of testing device for RK3568 core board, integrates multiple test interfaces, improves test speed, can monitor power consumption in real time, and is convenient for troubleshooting.

[0004] To achieve the above object, the technical scheme adopted by the utility model is: a kind of testing device for RK3568 core board, including test mainboard and the core board to be measured, test mainboard is connected with the core board to be measured by BTB connector, test mainboard is provided with test main control chip U8, power supply circuit and power consumption detection circuit, power supply circuit is connected with the core board to be measured by BTB connector, test main control chip U8 and power consumption detection circuit are connected with power supply circuit respectively,

[0005] Power consumption detection circuit includes voltage acquisition circuit, current acquisition circuit and power consumption display circuit, voltage acquisition circuit, current acquisition circuit and power consumption display circuit are electrically connected with test main control chip U8 respectively, current acquisition circuit sends acquisition voltage signal Voltage_FB to test main control chip U8, current acquisition circuit sends acquisition current signal Current_FB to test main control chip U8.

[0006] Further technical scheme, voltage acquisition circuit includes resistance R23, resistance R28 and capacitor C46,

[0007] The first end of resistance R23 is connected with the VCC_12V power supply end of the power supply circuit, the second end of resistance R23, the first end of resistance R28 and the first end of capacitor C46 are connected with test main control chip U8 respectively, the second end of resistance R28 and the second end of capacitor C46 are grounded respectively.

[0008] In a further technical solution, the resistance R23 is 80.6K, the resistance R28 is 10K, and the capacitance C46 is 10nF.

[0009] In a further technical solution, the current collection circuit includes an operational amplifier U7, resistors R26, R27, R29, R30, R31, R32, capacitors C38, C45, and C47,

[0010] The positive power supply end of the operational amplifier U7 is connected to the VCC_ADC power supply end of the power supply circuit and the first end of the capacitor C38, respectively, the negative power supply end of the operational amplifier U7 and the second end of the capacitor C38 are grounded, the non-inverting input end of the operational amplifier U7 is connected to the first end of the capacitor C45, the first end of the resistor R31, and the second end of the resistor R26, respectively, the inverting input end of the operational amplifier U7 is connected to the first end of the resistor R32, the second end of the capacitor C45, and the second end of the resistor R30, respectively, the output end of the operational amplifier U7 is connected to the second end of the resistor R32 and the first end of the resistor R27, respectively, the first end of the resistor R30 is connected to the second end of the resistor R29 and the ground, respectively, the first end of the resistor R29 is connected to the first end of the resistor R26 and the ground, respectively, the second end of the resistor R31 is grounded, the second end of the resistor R27 is connected to the first end of the capacitor C47 and the test master chip U8, respectively, and the second end of the capacitor C47 is grounded.

[0011] In a further technical solution, the resistances R26 and R30 are 1K, the resistances R31 and R32 are 10K, the resistance R27 is 100R, the resistance R29 is 0.2R, the capacitances C38 and C45 are 0.1nF, and the capacitance C47 is 10nF.

[0012] In a further technical solution, the power consumption display circuit includes a voltage display circuit and a current display circuit,

[0013] The voltage display circuit includes a digital tube LED2, a resistor R35, a resistor R36, a resistor R39, a resistor R41, a resistor R43, a resistor R45, a resistor R47 and a resistor R48, the resistor R35 is connected in series between the eleventh pin of the digital tube LED2 and the LED_A pin of the test main control chip U8, the resistor R36 is connected in series between the seventh pin of the digital tube LED2 and the LED_B pin of the test main control chip U8, the resistor R39 is connected in series between the fourth pin of the digital tube LED2 and the LED_C pin of the test main control chip U8, the resistor R41 is connected in series between the second pin of the digital tube LED2 and the LED_D pin of the test main control chip U8, the resistor R43 is connected in series between the first pin of the digital tube LED2 and the LED_E pin of the test main control chip U8, the resistor R45 is connected in series between the tenth pin of the digital tube LED2 and the LED_F pin of the test main control chip U8, the resistor R47 is connected in series between the fifth pin of the digital tube LED2 and the LED_G pin of the test main control chip U8, the resistor R48 is connected in series between the third pin of the digital tube LED2 and the LED_DP pin of the test main control chip U8, the twelfth pin of the digital tube LED2 is connected with the CM1 pin of the test main control chip U8, the ninth pin of the digital tube LED2 is connected with the CM2 pin of the test main control chip U8, the eighth pin of the digital tube LED2 is connected with the CM3 pin of the test main control chip U8.

[0014] The current display circuit includes a digital tube LED3, a resistor R33, a resistor R34, a resistor R37, a resistor R38, a resistor R40, a resistor R42, a resistor R44 and a resistor R46, the resistor R33 is connected in series between the eleventh pin of the digital tube LED3 and the LED_A pin of the test main control chip U8, the resistor R34 is connected in series between the seventh pin of the digital tube LED3 and the LED_B pin of the test main control chip U8, the resistor R37 is connected in series between the fourth pin of the digital tube LED3 and the LED_C pin of the test main control chip U8, the resistor R38 is connected in series between the second pin of the digital tube LED3 and the LED_D pin of the test main control chip U8, the resistor R40 is connected in series between the first pin of the digital tube LED3 and the LED_E pin of the test main control chip U8, the resistor R42 is connected in series between the tenth pin of the digital tube LED3 and the LED_F pin of the test main control chip U8, the resistor R44 is connected in series between the fifth pin of the digital tube LED3 and the LED_G pin of the test main control chip U8, the resistor R46 is connected in series between the third pin of the digital tube LED3 and the LED_DP pin of the test main control chip U8, the twelfth pin of the digital tube LED3 is connected with the CM4 pin of the test main control chip U8, the ninth pin of the digital tube LED3 is connected with the CM5 pin of the test main control chip U8, the eighth pin of the digital tube LED3 is connected with the CM6 pin of the test main control chip U8.

[0015] In a further technical solution, the test mainboard is provided with a burning connector J2, a first pin of the burning connector J2 is connected with a VCC MCU power supply end of the power supply circuit, a second pin of the burning connector J2 is connected with a SWDIO pin of the test main control chip U8, a fourth pin of the burning connector J2 is connected with an LED_DP pin of the test main control chip U8, a fifth pin of the burning connector J2 is connected with an NRST pin of the test main control chip U8, and a third pin of the burning connector J2 is grounded.

[0016] In a further technical solution, the test mainboard is provided with a display output interface circuit, a display input interface circuit and an audio interface circuit, the display interface circuit includes a first MIPI interface circuit, a second MIPI interface circuit, an eDP interface circuit and an HDMI interface circuit, and the first MIPI interface circuit, the second MIPI interface circuit, the eDP interface circuit and the HDMI interface circuit are connected with the to-be-tested core board through the BTB connector respectively.

[0017] The display input interface circuit is provided with an IMX415 camera, and the IMX415 camera is connected with the to-be-tested core board through the BTB connector.

[0018] The audio interface circuit is provided with a first SPK loudspeaker socket, a second SPK loudspeaker socket, a MIC microphone and a buzzer, and the first SPK loudspeaker socket, the second SPK loudspeaker socket, the MIC microphone and the buzzer are connected with the to-be-tested core board through the BTB connector respectively.

[0019] In a further technical solution, the test mainboard is further provided with a communication circuit, the communication circuit includes a Debug interface circuit, an SD card interface circuit, a SIM card interface circuit, a MIPI-PCIE interface circuit, a TYPE-C interface circuit, a USB-A interface circuit and a network port circuit, and the Debug interface circuit, the SD card interface circuit, the SIM card interface circuit, the MIPI-PCIE interface circuit, the TYPE-C interface circuit, the USB-A interface circuit and the network port circuit are connected with the to-be-tested core board through the BTB connector respectively.

[0020] In a further technical solution, the test mainboard is further provided with an expansion IO detection circuit, and the expansion IO detection circuit is provided with a plurality of expansion control chips, and each expansion control chip is connected with the to-be-tested core board through the BTB connector.

[0021] Compared with the prior art, the utility model has the advantages that: through voltage acquisition circuit and current acquisition circuit gather total current and real -time voltage of power supply input consumption, and send gathered acquisition voltage signal Voltage_FB and acquisition current signal Current_FB to test main control chip U8, test main control chip U8 carries out conversion to acquisition voltage signal Voltage_FB and acquisition current signal Current_FB and shows real -time voltage and current through power consumption display circuit, so that the power consumption during testing is monitored in real time, and troubleshooting is facilitated, through integrated multiple test interfaces, testing is carried out without additional independent connection module, and testing speed is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] The utility model is further explained below in combination with the drawings and examples.

[0023] Figure 1 It is the structural schematic diagram of the utility model;

[0024] Figure 2 It is the circuit diagram of voltage acquisition circuit of the utility model;

[0025] Figure 3 It is the circuit diagram of current acquisition circuit of the utility model;

[0026] Figure 4 It is the circuit diagram of voltage display circuit of the utility model;

[0027] Figure 5 It is the circuit diagram of current display circuit of the utility model;

[0028] Figure 6 It is the circuit diagram of test main control chip U8 of the utility model;

[0029] Figure 7 It is the circuit diagram of Debug interface circuit of the utility model;

[0030] Figure 8 It is the circuit diagram of net mouth circuit of the utility model;

[0031] Figure 9 It is the circuit diagram of TYPE-C interface circuit and USB-A interface circuit of the utility model;

[0032] Figure 10 It is the circuit diagram of HDMI interface circuit of the utility model;

[0033] Figure 11 It is the circuit diagram of first MIPI interface circuit and second MIPI interface circuit of the utility model;

[0034] Figure 12is a circuit diagram of the MIPI-PCIE interface circuit of the utility model;

[0035] Figure 13 is a circuit diagram of the audio interface circuit of the utility model;

[0036] Figure 14 is a circuit diagram of the extension IO detection circuit of the utility model;

[0037] Figure 15 is a circuit diagram of the IMX415 camera of the utility model;

[0038] Figure 16 is a flow chart of the starting mode of the utility model;

[0039] Figure 17 is a test flow chart of the utility model.

[0040] In the figure:

[0041] 104 test main control chip U8, 112 BTB connector, 101 digital tube LED 2, 102 digital tube LED 3, 103 burning connector J2, 111 first MIPI interface circuit, 105 second MIPI interface circuit, 107 eDP interface circuit, 127 HDMI interface circuit, 106 IMX415 camera, 110 first SPK loudspeaker socket, 108 second SPK loudspeaker socket, 109 MIC microphone, 121 buzzer, 128 Debug interface circuit, 118 SD card interface circuit, 119 SIM card interface circuit, 120 MIPI-PCIE interface circuit, 124 TYPE-C interface circuit, 125 USB-A interface circuit, 126 network port circuit, 113 extension IO detection circuit. DETAILED DESCRIPTION

[0042] The following is only the preferred embodiment of the utility model, and does not limit the protection scope of the utility model.

[0043] A kind of test device for RK3568 core board, as shown in Figures 1 to 17As shown, including test mainboard and to be tested core board, test mainboard and to be tested core board are connected through BTB connector 112, test mainboard is provided with test main control chip U8, power supply circuit and power consumption detection circuit, power supply circuit is connected with to be tested core board through BTB connector 112, test main control chip U8 and power consumption detection circuit are connected with power supply circuit respectively, power consumption detection circuit includes voltage acquisition circuit, current acquisition circuit and power consumption display circuit, voltage acquisition circuit, current acquisition circuit and power consumption display circuit are electrically connected with test main control chip U8 respectively, current acquisition circuit sends acquisition voltage signal Voltage_FB to test main control chip U8, current acquisition circuit sends acquisition current signal Current_FB to test main control chip U8.RK3568 core board needs to connect corresponding module when testing each function, and the test procedure is complicated, the module demand is large, the test efficiency is low, and the current and voltage cannot be monitored in real time, which is not convenient for troubleshooting, and the utility model discloses a voltage acquisition circuit and a current acquisition circuit are used to collect the total current and real-time voltage consumed by power supply input, and the collected acquisition voltage signal Voltage_FB and acquisition current signal Current_FB are sent to test main control chip U8, test main control chip U8 converts acquisition voltage signal Voltage_FB and acquisition current signal Current_FB and displays real-time voltage and current through power consumption display circuit, so as to monitor power consumption in real time during testing, which is convenient for troubleshooting;By integrating a variety of test interfaces, there is no need to connect the module independently for testing, and the test speed is improved.

[0044] Specifically, the voltage acquisition circuit includes a resistor R23, a resistor R28, and a capacitor C46. The first end of the resistor R23 is connected to the VCC_12V power supply end of the power supply circuit. The second end of the resistor R23, the first end of the resistor R28, and the first end of the capacitor C46 are connected to the test main control chip U8. The second end of the resistor R28 and the second end of the capacitor C46 are grounded. The input voltage is divided by the resistor R23 and the resistor R28. The value of the acquisition voltage signal Voltage_FB is VCC_12V*((R28) / (R23+R28)) (unit: V). The resistance value of the resistor R23 is 80.6K. The resistance value of the resistor R28 is 10K. The capacitance of the capacitor C46 is 10nF. Substituting the resistance values, we get voltage_ADC=(VCC_12V / 9.06)*1 (unit: V).

[0045] Specifically, the current collection circuit comprises an operational amplifier U7, a resistor R26, a resistor R27, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a capacitor C38, a capacitor C45 and a capacitor C47, the positive power supply end of the operational amplifier U7 is connected with the VCC_ADC power supply end of the power supply circuit and the first end of the capacitor C38 respectively, the negative power supply end of the operational amplifier U7 and the second end of the capacitor C38 are grounded respectively, the non-inverting input end of the operational amplifier U7 is connected with the first end of the capacitor C45, the first end of the resistor R31 and the second end of the resistor R26 respectively, the inverting input end of the operational amplifier U7 is connected with the first end of the resistor R32, the second end of the capacitor C45 and the second end of the resistor R30 respectively, the output end of the operational amplifier U7 is connected with the second end of the resistor R32 and the first end of the resistor R27 respectively, the first end of the resistor R30 is connected with the second end of the resistor R29 and the ground respectively, the first end of the resistor R29 is connected with the first end of the resistor R26 and the ground respectively, the second end of the resistor R31 is grounded, the second end of the resistor R27 is connected with the first end of the capacitor C47 and the test master control chip U8 respectively, and the second end of the capacitor C47 is grounded. Specifically, the resistance values of the resistor R26 and the resistor R30 are 1K respectively, the resistance values of the resistor R31 and the resistor R32 are 10K respectively, the resistance value of the resistor R27 is 100R, the resistance value of the resistor R29 is 0.2R, the capacitances of the capacitor C38 and the capacitor C45 are 0.1nF, and the capacitance of the capacitor C47 is 10nF. The current on the resistor R29 is the total current consumed by the power supply input, and when the power supply is normal, the current flowing through the sampling resistor is current (unit: A); the current current flows through the resistor R29, and a corresponding voltage is generated, according to the virtual break analysis principle of the operational amplifier, Ib-=Ib+=0, according to the virtual short principle of the operational amplifier, V+=V-, (Vdgnd-V-) / R30=(V--Vout) / R32, (Vgnd-V+) / R26=V+ / R31; the solution is: Vout=(R32 / R30)*(Vgnd-Vdgnd)=(10K / 1K)*Vr20=(10 / 1)*(R20*current), that is, Current_FB=(10 / 1)*0.2*current.

[0046] Specifically, the power consumption display circuit includes a voltage display circuit and a current display circuit, the voltage display circuit includes a digital tube LED2, a resistor R35, a resistor R36, a resistor R39, a resistor R41, a resistor R43, a resistor R45, a resistor R47 and a resistor R48, the resistor R35 is connected in series between an eleventh pin of the digital tube LED2 and an LED_A pin of the test main control chip U8, the resistor R36 is connected in series between a seventh pin of the digital tube LED2 and an LED_B pin of the test main control chip U8, the resistor R39 is connected in series between a fourth pin of the digital tube LED2 and an LED_C pin of the test main control chip U8, the resistor R41 is connected in series between a second pin of the digital tube LED2 and an LED_D pin of the test main control chip U8, the resistor R43 is connected in series between a first pin of the digital tube LED2 and an LED_E pin of the test main control chip U8, the resistor R45 is connected in series between a tenth pin of the digital tube LED2 and an LED_F pin of the test main control chip U8, the resistor R47 is connected in series between a fifth pin of the digital tube LED2 and an LED_G pin of the test main control chip U8, the resistor R48 is connected in series between a third pin of the digital tube LED2 and an LED_DP pin of the test main control chip U8, a twelfth pin of the digital tube LED2 is connected with a CM1 pin of the test main control chip U8, a ninth pin of the digital tube LED2 is connected with a CM2 pin of the test main control chip U8, and an eighth pin of the digital tube LED2 is connected with a CM3 pin of the test main control chip U8; the current display circuit includes a digital tube LED3, a resistor R33, a resistor R34, a resistor R37, a resistor R38, a resistor R40, a resistor R42, a resistor R44 and a resistor R46, the resistor R33 is connected in series between an eleventh pin of the digital tube LED3 and an LED_A pin of the test main control chip U8, the resistor R34 is connected in series between a seventh pin of the digital tube LED3 and an LED_B pin of the test main control chip U8, the resistor R37 is connected in series between a fourth pin of the digital tube LED3 and an LED_C pin of the test main control chip U8, the resistor R38 is connected in series between a second pin of the digital tube LED3 and an LED_D pin of the test main control chip U8, the resistor R40 is connected in series between a first pin of the digital tube LED3 and an LED_E pin of the test main control chip U8, the resistor R42 is connected in series between a tenth pin of the digital tube LED3 and an LED_F pin of the test main control chip U8, the resistor R44 is connected in series between a fifth pin of the digital tube LED3 and an LED_G pin of the test main control chip U8, the resistor R46 is connected in series between a third pin of the digital tube LED3 and an LED_DP pin of the test main control chip U8, a twelfth pin of the digital tube LED3 is connected with a CM4 pin of the test main control chip U8, a ninth pin of the digital tube LED3 is connected with a CM5 pin of the test main control chip U8, and an eighth pin of the digital tube LED3 is connected with a CM6 pin of the test main control chip U8.The test main control chip U8 converts the values of the collected voltage signal Voltage_FB and the collected current signal Current_FB back to the values of VCC_12V and current, and drives the nixie tube LED2 and the nixie tube LED3 to display the real-time current and voltage through the above-mentioned pins, which is simple in structure and low in cost.

[0047] Specifically, the test mainboard is provided with a burning connector J2, a first pin of the burning connector J2 is connected with the VCC_MCU power supply end of the power supply circuit, a second pin of the burning connector J2 is connected with the SWDIO pin of the test main control chip U8, a fourth pin of the burning connector J2 is connected with the LED_DP pin of the test main control chip U8, a fifth pin of the burning connector J2 is connected with the NRST pin of the test main control chip U8, and the third pin of the burning connector J2 is grounded. The test main control chip U8 is connected through the burning connector J2, so that the burning device is conveniently connected for testing program burning.

[0048] Specifically, the test mainboard is provided with a display output interface circuit, a display input interface circuit and an audio interface circuit, the display interface circuit includes a first MIPI interface circuit 111, a second MIPI interface circuit 105, an eDP interface circuit 107 and an HDMI interface circuit 127, and the first MIPI interface circuit 111, the second MIPI interface circuit 105, the eDP interface circuit 107 and the HDMI interface circuit 127 are connected with the to-be-tested core board through the BTB connector 112 respectively; the MIPI screen is connected through the first MIPI interface circuit 111 and the second MIPI interface circuit 105, which is used for testing the MIPI DSI signal and video display of the to-be-tested core board, the first MIPI interface circuit 111 is used for connecting the MIPI screen built-in the test mainboard, so as to facilitate the display and selection control of the test result, and the second MIPI interface circuit 105 is used for connecting the external MIPI screen, the eDP screen is connected through the eDP interface circuit 107, which is used for testing the eDP signal and video display of the to-be-tested core board, the screen of the HDMI interface is connected through the HDMI interface circuit 127, which is used for testing the HDMI signal and video display of the to-be-tested core board, and the test mainboard integrates multiple different display interfaces to test different display signals, so as to expand the test range and adaptability of the display signal.

[0049] The display input interface circuit is provided with an IMX415 camera 106, and the IMX415 camera 106 is connected with the to-be-tested core board through the BTB connector 112; the IMX415 camera 106 is used for testing the MIPI CSI signal of the to-be-tested core board, and the decoding capability of the to-be-tested core board is tested through image or video acquisition.

[0050] The audio interface circuit is provided with a first SPK loudspeaker socket 110, a second SPK loudspeaker socket 108, a MIC microphone 109 and a buzzer 121, and the first SPK loudspeaker socket 110, the second SPK loudspeaker socket 108, the MIC microphone 109 and the buzzer 121 are connected with the core board to be tested through the BTB connector 112 respectively. The HP_OUT earphone signal of the core board to be tested is connected to a power amplifier chip with a model number of 8002A, loudspeakers are connected through the first SPK loudspeaker socket 110 and the second SPK loudspeaker socket 108, thereby forming two sound channels, which are used for testing the audio playback of the core board to be tested, supporting the access of loudspeakers with large power, and directly leading out the original SPK signal. Audio is collected through the MIC microphone 109, which is used for testing the audio collection performance of the core board to be tested, and after the test is completed, a buzzer sound is emitted through the buzzer 121 to remind that the test is completed.

[0051] Specifically, the test mainboard is further provided with a communication circuit, and the communication circuit includes a Debug interface circuit 128, an SD card interface circuit 118, a SIM card interface circuit 119, an MIPI-PCIE interface circuit 120, a TYPE-C interface circuit 124, a USB-A interface circuit 125 and a network port circuit 126, and the Debug interface circuit 128, the SD card interface circuit 118, the SIM card interface circuit 119, the MIPI-PCIE interface circuit 120, the TYPE-C interface circuit 124, the USB-A interface circuit 125 and the network port circuit 126 are connected with the core board to be tested through the BTB connector 112 respectively. A TF card is installed through the SD card interface circuit 118, and when starting, if Figure 16As shown, first detect whether the SD card interface circuit 118 is inserted into the TF card, such as after inserting the TF card, read the program in the TF card to start, so as to start from the TF card, without repeatedly burning the program; connect the SIM card through the SIM card interface circuit 119, so as to realize the cellular network connection, in order to test the mobile Internet function; connect the PCIE network card or 4G module through the MIPI-PCIE interface circuit 120, which can detect the PCIE signal and USB signal of the core board to be tested, and improve the expansion capability; connect the computer through the TYPE-C interface circuit 124, so as to be able to burn the program of the core board to be tested, and give the test motherboard programming function, connect USB3.0 and USB2.0 equipment through USB-A interface circuit 125, so as to test the USB3.0 and USB2.0 signal of the core board to be tested, control the power-on of the USB port through the power switch chip with model LPW5209AB5F, and limit the output current to 2A to meet the USB power requirement and protect the damage caused by overcurrent. The USB-A interface circuit 125 uses double-layer interface to access USB3.0 and USB2.0 signals, reducing space occupation. The TYPE-C interface circuit 124 accesses the USB2.0 signal to support hardware master-slave switching. Through the network port circuit 126, JL2101B PHY chip is used to support gigabit rate, 10 / 100 / 1000M adaptive, which can test the GMAC related pins of the core board to be tested, and the network port can update the program and communicate through the network; access the serial module through the Debug interface circuit 128, and carry out serial interaction, which is convenient for troubleshooting. The Debug interface circuit 128 is isolated by the chip with model 74LVC1G125GW. After power off, the power supply of VDD_3V3 becomes 0V. At this time, the A and Y pins of the 74LVC1G125GW chip are in high resistance state, thereby cutting off the current backflow of the Debug serial module.

[0052] Specifically, the test mainboard is further provided with an expansion IO detection circuit 113, which is provided with a plurality of expansion control chips, each of which is connected with the to-be-tested core board through the BTB connector 112. The expansion IO detection circuit 113 is provided with a plurality of XL9535QF24 chips for expansion IO, and the to-be-tested core board communicates with each XL9535QF24 chip through an I2C bus. In the first round of testing, first, all pins of the XL9535QF24 chip are set as input, and the native pins of the to-be-tested core board are set as high-level output, so that the level read by the XL9535QF24 chip is high, and then the first round of high-level test is passed. If the read pin is not high, the test fails. In the second round of testing, the native pins of the to-be-tested core board are set as low-level output, so that the level read by the XL9535QF24 chip is low, and then the second round of low-level test is passed. If the read pin is not low, the test fails. Through the two rounds of testing, the native pins of the to-be-tested core board are tested for high and low levels, so as to ensure that the native pins of the to-be-tested core board communicate normally.

[0053] As shown in Figure 17 The utility model discloses after the test mainboard is powered on, automatic judgment starting mode, starting, complete starting and automatically running test program, utilize each interface and automatically complete multiple function test, finally through the buzzer 121 short reminder test completion, need not manual access, improve test efficiency, and the degree of automation is high.

[0054] The above content is only the preferred embodiment of the utility model, for the ordinary skilled person in the art, according to the thought of the utility model, in specific implementation mode and application range, will have the change, the content of this specification should not be understood as the limitation of the utility model.

Claims

1. A test device for RK3568 core board, comprising a test mainboard and a to-be-tested core board, the test mainboard is connected with the to-be-tested core board through a BTB connector (112), characterized in that: The test mainboard is provided with a test main control chip U8 (104), a power supply circuit and a power consumption detection circuit, the power supply circuit is connected with the core board to be tested through a BTB connector (112), the test main control chip U8 (104) and the power consumption detection circuit are connected with the power supply circuit, The power consumption detection circuit comprises a voltage acquisition circuit, a current acquisition circuit and a power consumption display circuit, the voltage acquisition circuit, the current acquisition circuit and the power consumption display circuit are electrically connected with the test main control chip U8 (104), the current acquisition circuit sends an acquisition voltage signal Voltage_FB to the test main control chip U8 (104), and the current acquisition circuit sends an acquisition current signal Current_FB to the test main control chip U8 (104).

2. The testing device for the RK3568 core board according to claim 1, wherein: The voltage acquisition circuit comprises a resistor R23, a resistor R28 and a capacitor C46, a first end of the resistor R23 is connected with a VCC_12V power supply end of the power supply circuit, a second end of the resistor R23, a first end of the resistor R28 and a first end of the capacitor C46 are connected with the test main control chip U8 (104) respectively, and a second end of the resistor R28 and a second end of the capacitor C46 are grounded respectively.

3. The testing device for RK3568 core board according to claim 2, characterized in that: The resistance value of the resistor R23 is 80.6K, the resistance value of the resistor R28 is 10K, and the capacitance of the capacitor C46 is 10nF.

4. The testing device for the RK3568 core board according to claim 1, wherein: The current acquisition circuit comprises an operational amplifier U7, a resistor R26, a resistor R27, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a capacitor C38, a capacitor C45 and a capacitor C47, a positive power supply end of the operational amplifier U7 is connected with a VCC_ADC power supply end of the power supply circuit and a first end of the capacitor C38 respectively, a negative power supply end of the operational amplifier U7 and a second end of the capacitor C38 are grounded respectively, a noninverting input end of the operational amplifier U7 is connected with a first end of the capacitor C45, a first end of the resistor R31 and a second end of the resistor R26 respectively, an inverting input end of the operational amplifier U7 is connected with a first end of the resistor R32, a second end of the capacitor C45 and a second end of the resistor R30 respectively, an output end of the operational amplifier U7 is connected with a second end of the resistor R32 and a first end of the resistor R27 respectively, a first end of the resistor R30 is connected with a second end of the resistor R29 and a grounding end respectively, a first end of the resistor R29 is connected with a first end of the resistor R26 and a grounding end respectively, a second end of the resistor R31 is grounded, a second end of the resistor R27 is connected with a first end of the capacitor C47 and the test main control chip U8 (104) respectively, and a second end of the capacitor C47 is grounded.

5. The testing device for RK3568 core board according to claim 4, characterized in that: The resistance values of the resistor R26 and the resistor R30 are 1K respectively, the resistance values of the resistor R31 and the resistor R32 are 10K respectively, the resistance value of the resistor R27 is 100R, the resistance value of the resistor R29 is 0.2R, the capacitances of the capacitor C38 and the capacitor C45 are 0.1nF, and the capacitance of the capacitor C47 is 10nF.

6. The testing device for the RK3568 core board according to claim 1, wherein: The power consumption display circuit comprises a voltage display circuit and a current display circuit, The voltage display circuit comprises a digital tube LED 2 (101), a resistor R35, a resistor R36, a resistor R39, a resistor R41, a resistor R43, a resistor R45, a resistor R47 and a resistor R48, the resistor R35 is connected in series between the eleventh pin of the digital tube LED 2 (101) and the LED_A pin of the test master chip U8 (104), the resistor R36 is connected in series between the seventh pin of the digital tube LED 2 (101) and the LED_B pin of the test master chip U8 (104), the resistor R39 is connected in series between the fourth pin of the digital tube LED 2 (101) and the LED_C pin of the test master chip U8 (104), the resistor R41 is connected in series between the second pin of the digital tube LED 2 (101) and the LED_D pin of the test master chip U8 (104), the resistor R43 is connected in series between the first pin of the digital tube LED 2 (101) and the LED_E pin of the test master chip U8 (104), the resistor R45 is connected in series between the tenth pin of the digital tube LED 2 (101) and the LED_F pin of the test master chip U8 (104), the resistor R47 is connected in series between the fifth pin of the digital tube LED 2 (101) and the LED_G pin of the test master chip U8 (104), the resistor R48 is connected in series between the third pin of the digital tube LED 2 (101) and the LED_DP pin of the test master chip U8 (104), the twelfth pin of the digital tube LED 2 (101) is connected with the CM1 pin of the test master chip U8 (104), the ninth pin of the digital tube LED 2 (101) is connected with the CM2 pin of the test master chip U8 (104), and the eighth pin of the digital tube LED 2 (101) is connected with the CM3 pin of the test master chip U8 (104); The current display circuit includes a digital tube LED 3 (102), a resistor R33, a resistor R34, a resistor R37, a resistor R38, a resistor R40, a resistor R42, a resistor R44 and a resistor R46, the resistor R33 is connected in series between the eleventh pin of the digital tube LED 3 (102) and the LED_A pin of the test main control chip U8 (104), the resistor R34 is connected in series between the seventh pin of the digital tube LED 3 (102) and the LED_B pin of the test main control chip U8 (104), the resistor R37 is connected in series between the fourth pin of the digital tube LED 3 (102) and the LED_C pin of the test main control chip U8 (104), the resistor R38 is connected in series between the second pin of the digital tube LED 3 (102) and the LED_D pin of the test main control chip U8 (104), the resistor R40 is connected in series between the first pin of the digital tube LED 3 (102) and the LED_E pin of the test main control chip U8 (104), the resistor R42 is connected in series between the tenth pin of the digital tube LED 3 (102) and the LED_F pin of the test main control chip U8 (104), the resistor R44 is connected in series between the fifth pin of the digital tube LED 3 (102) and the LED_G pin of the test main control chip U8 (104), the resistor R46 is connected in series between the third pin of the digital tube LED 3 (102) and the LED_DP pin of the test main control chip U8 (104), the twelfth pin of the digital tube LED 3 (102) is connected with the CM4 pin of the test main control chip U8 (104), the ninth pin of the digital tube LED 3 (102) is connected with the CM5 pin of the test main control chip U8 (104), and the eighth pin of the digital tube LED 3 (102) is connected with the CM6 pin of the test main control chip U8 (104).

7. The testing device for the RK3568 core board according to claim 1, wherein: The test mainboard is provided with a burning connector J2 (103), the first pin of the burning connector J2 (103) is connected with the VCC_MCU power supply end of the power supply circuit, the second pin of the burning connector J2 (103) is connected with the SWDIO pin of the test main control chip U8 (104), the fourth pin of the burning connector J2 (103) is connected with the LED_DP pin of the test main control chip U8 (104), the fifth pin of the burning connector J2 (103) is connected with the NRST pin of the test main control chip U8 (104), and the third pin of the burning connector J2 (103) is grounded.

8. The testing device for the RK3568 core board according to claim 1, wherein: The test mainboard is provided with a display output interface circuit, a display input interface circuit and an audio interface circuit, and the display interface circuit includes a first MIPI interface circuit (111), a second MIPI interface circuit (105), an eDP interface circuit (107) and an HDMI interface circuit (127), and the first MIPI interface circuit (111), the second MIPI interface circuit (105), the eDP interface circuit (107) and the HDMI interface circuit (127) are connected with the to-be-tested core board through the BTB connector (112) respectively. The display input interface circuit is provided with an IMX415 camera (106), and the IMX415 camera (106) is connected with the core board to be tested through a BTB connector (112); The audio interface circuit is provided with a first SPK loudspeaker socket (110), a second SPK loudspeaker socket (108), a MIC microphone (109) and a buzzer (121), and the first SPK loudspeaker socket (110), the second SPK loudspeaker socket (108), the MIC microphone (109) and the buzzer (121) are connected with the core board to be tested through the BTB connector (112) respectively.

9. The testing device for the RK3568 core board according to claim 1, wherein: The test mainboard is further provided with a communication circuit, and the communication circuit comprises a Debug interface circuit (128), an SD card interface circuit (118), a SIM card interface circuit (119), an MIPI-PCIE interface circuit (120), a TYPE-C interface circuit (124), a USB-A interface circuit (125) and a network port circuit (126), and the Debug interface circuit (128), the SD card interface circuit (118), the SIM card interface circuit (119), the MIPI-PCIE interface circuit (120), the TYPE-C interface circuit (124), the USB-A interface circuit (125) and the network port circuit (126) are connected with the core board to be tested through the BTB connector (112) respectively.

10. The testing device for the RK3568 core board according to claim 1, wherein: The test mainboard is further provided with an extension IO detection circuit (113), and the extension IO detection circuit (113) is provided with a plurality of extension control chips, and each extension control chip is connected with the core board to be tested through the BTB connector (112).

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