System-level stacking structure and electronic equipment

Abstract

The utility model discloses a system-level stacking structure and electronic equipment. The system-level stack structure includes a substrate, a conductive connection element, an integrated circuit, and a conductive component. The substrate comprises a supporting surface, and the conductive connecting element and the integrated circuit are arranged on the supporting surface in parallel. The conductive part is located on the surfaces of the conductive connecting element and the integrated circuit, the conductive part is connected with the conductive connecting element and electrically connected with the integrated circuit, and the conductive part and the integrated circuit are spaced by a first distance in the direction perpendicular to the supporting face. The integrated circuit and the conductive component form a gap for heat dissipation through the spacing distance, so that the safety and reliability of the system-level stacking structure and the electronic equipment are effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor, especially to a system level stacking structure and electronic equipment. BACKGROUND

[0002] System in a package (SIP) realizes the basic complete function by integrating multiple functional chips, including processor, memory and other functional chips in a package, from the structure of SIP package, mainly is the arrangement, compatibility and layout of multiple functional chips and discrete components. From the current product packaging structure, the chip and discrete component mainly appear as a flat structure, which obviously increases the overall size of the packaging structure, or selects the substrate embedding process of passive components, increases the substrate processing cycle and cost, and the yield of the substrate is relatively poor.

[0003] With the gradual development of Internet technology and the increasing demand for network, in order to meet the requirement of high-speed processing performance, multi-dimensional (3D) stacked semiconductor chips are usually used to adapt to high-power chips. Multi-dimensional stacked semiconductor chips usually stack multiple chips in the vertical direction, so as to increase the chip interconnection density, reduce the packaging volume and improve the electrical and thermal transmission efficiency. Since the multiple chips of the stacked semiconductor chips are arranged in the vertical direction, the heat is not easy to dissipate during the operation of the semiconductor chip, especially when the power SIP module works with large current, the heat accumulates in the internal of the semiconductor chip, so that the heat of the chip is difficult to dissipate, resulting in high junction temperature of the stacked chip, and the high temperature environment of the stacking structure between the chip and the discrete component, which easily affects the service life of the semiconductor chip and even causes the failure of the semiconductor chip. According to the statistical data, at least 55% of the failure reasons of electronic equipment are temperature rise failure, and the reliability of electronic devices decreases by 5% for every 1℃ increase of the temperature of semiconductor chip. Therefore, it is necessary to improve the heat dissipation effect of the stacked chip to meet the heat dissipation demand of high-power devices. SUMMARY

[0004] To solve the foregoing technical problems, the utility model provides a system level stacking structure with high safety and reliability.

[0005] Further, the utility model also provides an electronic equipment comprising the foregoing system level stacking structure.

[0006] In a first aspect, the utility model embodiment provides a system level stacking structure, include: substrate, including support surface, conductive connecting element with at least one integrated circuit, the conductive connecting element with the integrated circuit is arranged in parallel on the support surface, conductive part, located the conductive connecting element with the integrated circuit surface, the conductive part connects the conductive connecting element, and with the integrated circuit electric connection, the conductive part with the integrated circuit is spaced first distance in along the direction perpendicular to the support surface.

[0007] In one embodiment, a heat conduction layer is arranged between the conductive part and the integrated circuit, and the heat conduction layer is used to conduct heat generated by the integrated circuit and / or the conductive part.

[0008] In one embodiment, the conductive part is an inductor, and a conductive pin of the inductor is connected to the conductive part.

[0009] In one embodiment, the inductor is a single-winding inductor or a double-winding inductor.

[0010] In one embodiment, the system level stacking structure includes a plurality of conductive connecting elements arranged at different positions.

[0011] In one embodiment, a plurality of separate conductive connecting elements are arranged at positions spaced by a predetermined distance around the peripheral edge of the substrate.

[0012] In one embodiment, the material of the conductive connecting element is copper.

[0013] In one embodiment, the system level stacking structure further includes a plurality of discrete elements, the discrete elements are arranged in parallel with the integrated circuit on the support surface, and are electrically connected to the integrated circuit and / or the conductive part through a conductive circuit.

[0014] In one embodiment, the system level stacking structure is a power module of a system in package.

[0015] In a second aspect, the utility model embodiment further provides an electronic device, including functional module and the system level stacking structure of preceding, the functional module with the system level stacking structure is connected to execute predetermined function.

[0016] Compared with the prior art, since the conductive component and the integrated circuit are not arranged in the support surface of the substrate at the same time, but are arranged in the thickness direction in a stacked manner, and a gap is formed between the conductive component and the integrated circuit by the first distance, heat generated by the conductive component is quickly dissipated without affecting the working performance of the integrated circuit, and meanwhile, heat generated by the integrated circuit in working is conducted and dissipated through the gap formed by the first distance, so that the heat generated by the integrated circuit can also be quickly dissipated, thereby ensuring the safety and reliability of the working of the overall element of the system-level stacked structure. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0018] Figure 1 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application.

[0019] Figure 2 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 1

[0020] It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 3 Figure 2 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application.

[0021] Figure 4 Figure 2 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application.

[0022] Figure 5 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 2

[0023] It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 6 Figure 2 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application.

[0024] Figure 7 It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 2

[0025] It is a perspective view of the system-level stacked structure shown in the first embodiment of the present application. Figure 8 Figure 2 ​​​​A schematic diagram of a cross-sectional structure along an IV-IV line of the system-level stacked structure shown in FIG. 1A;

[0026] Figure 9 A partial structure top view of the system-level stacked structure shown in FIG. 1A. Figure 2 A partial structure top view of the system-level stacked structure shown in FIG. 1A.

[0027] Figure 10 A functional block diagram of the electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. The description of each embodiment below is with reference to the additional drawings to illustrate specific embodiments in which the present application can be implemented.

[0029] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include", "may include", "contain" or "may contain" used in the present application represent the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit other one or more functions, operations, elements, etc. In addition, the terms "include" or "contain" represent the existence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusion. It should also be understood that the meaning of "at least one" described herein is one and more, for example, one, two or three, etc., and the meaning of "multiple" is at least two, for example, two or three, etc., unless otherwise explicitly specified and limited.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0031] Please refer to Figure 1 and Figure 2 , wherein, Figure 1 is a perspective structure schematic diagram of a system-level stacked structure 1 in the embodiments of the application, Figure 2 is Figure 1 a perspective structure schematic diagram of the system-level stacked structure 1. In the embodiments, the system-level stacked structure 1 can be a microcircuit structure using system-in-package (SIP) stacking, and the system-level stacked structure 1 can be a power module, a high-speed storage module, a processor module, a semiconductor device module, etc. In the embodiments, the system-level stacked structure 1 is taken as a system-level stacked power module as an example for description.

[0032] Specifically, as shown in Figure 1 and Figure 2 , the system-level stacked structure 1 includes a substrate 10, an integrated circuit layer 20, and a conductive element layer 30 which are sequentially stacked.

[0033] The substrate 10 includes a support surface 10a( Figure 3 ) and a connecting surface 10b( Figure 3 ) which are oppositely arranged, the integrated circuit layer 20 is arranged on the support surface 10a of the substrate 10, and the conductive element layer 30 is arranged on the surface of the integrated circuit layer 20 and is electrically connected to part of the circuit of the integrated circuit layer 20 through part of the conductive connecting elements of the integrated circuit layer 20. The integrated circuit layer 20 and the conductive element layer 30 cooperate with each other to perform a predetermined function.

[0034] It can be understood that the integrated circuit layer 20 includes a plurality of integrated circuits, a plurality of discrete electronic elements, and at least one conductive connecting element, and the conductive element layer 30 includes at least one conductive component which is electrically connected to the integrated circuit through the conductive connecting element. In the embodiments, the conductive element layer 30 is located on the upper side of the integrated circuit layer 20, and the distance between them is a certain distance, so that the heat generated by the conductive element layer 30 and the integrated circuit layer 20 in operation has less mutual influence, which is more conducive to the heat dissipation of the two, thereby ensuring the safety and reliability of the system-level stacked structure.

[0035] It can be understood that the system-level stacked structure 1 can be directly matched with other modules to perform preset functions, or can be molded with a packaging material such as epoxy resin, that is, the epoxy resin is covered on the system-level stacked structure 1 by using a molding process, so as to protect the substrate 10 and the devices in the integrated circuit layer 20 and the conductive element layer 30.

[0036] More specifically, please refer to Figure 3 、 Figure 4 and Figure 5 , wherein, Figure 3 is a cross-sectional structure diagram of the system-level stacked structure along the III-III line as shown in Figure 2 , Figure 4 is a cross-sectional structure diagram of the system-level stacked structure along the IV-IV line as shown in Figure 2 , Figure 5 is a partial structure top view of the system-level stacked structure as shown in Figure 1 , wherein in the embodiment, Figure 5 is a top view of the system-level stacked structure corresponding to the integrated circuit layer 20 as shown in Figure 1 .

[0037] As shown in Figure 3 to 5 , among the support surfaces 10a and the connecting surfaces 10b on the opposite sides of the substrate 10, the support surfaces 10a are used to support and arrange the integrated circuit layer 20. In the embodiment, the inside of the substrate 10, the support surfaces 10a and the connecting surfaces 10b are all provided with corresponding conductive lines (printed traces) to facilitate the electrical connection of the electronic components arranged on the support surfaces 10a of the substrate 10. The connecting surfaces 10b are provided with a plurality of conductive pins P, which are electrically connected with the electronic components in the integrated circuit layer 20 and the conductive element layer 30 through the conductive lines in the inside of the substrate 10, and the system-level stacked structure 1 is connected with other electronic modules through the plurality of conductive pins P. In the embodiment, the substrate 10 can be a printed circuit board (PCB), or a packaging substrate made of resin or other materials.

[0038] The integrated circuit layer 20 includes a plurality of integrated circuits and auxiliary matching discrete electronic components. Specifically, the integrated circuit layer 20 includes a plurality of integrated circuits 201 and a plurality of discrete components 202. The integrated circuits 201 can be integrated chips. In this embodiment, the integrated circuits 201 are connected to the conductive circuit in the substrate 10 through conductive hardware (not shown). For example, when the system-level stacked structure 1 is a power management chip in a power module, the integrated circuits 201 can be one or more of a chip containing an operational amplifier circuit, a chip containing a voltage conversion circuit such as a boost circuit or a buck circuit, a micro-processing management chip, and the like. Of course, the system-level stacked structure 1 can also be other integrated packaged chips, and is not limited to the above examples.

[0039] The plurality of discrete components 202 can include resistors, capacitors, inductors, transformer windings, or other electronic components. The plurality of discrete components 202 are connected and bonded to each other through the conductive traces in the substrate 10, and are electrically connected to the integrated circuits 201 to form corresponding functional circuits.

[0040] In this embodiment, the integrated circuits 201 have a first height H1 in the direction perpendicular to the support surface 10a, i.e., the thickness dimension of the integrated circuits 201 is the first height H1. The discrete components 202 have a dimension along the direction perpendicular to the support surface 10a that is less than the first height H1.

[0041] The integrated circuit layer 20 further includes a plurality of conductive connection elements 203 arranged along the edge of the substrate 10, and the conductive connection elements 203 have a second height H2 in the direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In this embodiment, the number and position of the conductive connection elements 203 can be adjusted according to actual needs. The conductive connection elements 203 can be made of conductive metal materials such as copper, aluminum, or other alloy conductive materials, and the surface of the conductive connection elements 203 can be plated with nickel, tin, gold, or other surface treatment processes to form a conductive structure.

[0042] In this embodiment, the conductive connection elements 203 are cuboid structures and are arranged on the support surface 10a of the substrate 10 by welding. Alternatively, in other embodiments of the present application, the conductive connection elements 203 can also be columnar, strip-shaped, sheet-shaped, or other shapes formed by CNC or casting.

[0043] The conductive element layer 30 includes at least a conductive component 31, wherein the conductive component 31 is located on a portion of the surface of a plurality of integrated circuits 201 and a plurality of discrete components 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects to a conductive connection element 203. Correspondingly, since the height of the conductive connection element 203 is greater than the height of the integrated circuit 201, the conductive component 31 connected to the conductive connection element 203 and the integrated circuit 201 are spaced apart by a first distance D1 in a direction perpendicular to the substrate 10. In other words, the conductive component 31 and the integrated circuit 201 have a gap of a first distance D1 in a direction perpendicular to the substrate 10.

[0044] In this embodiment, the conductive component 31 is an inductor, wherein the conductive pins (not shown) of the inductor are connected to the conductive connecting elements 203. The number of pins of the inductor directly corresponds to the number of conductive connecting elements 203. In this embodiment, when the inductor is a single-winding inductor, the inductor includes conductive pins at two different locations, and therefore there are also two conductive connecting elements 203, positioned at the corresponding pin positions of the inductor.

[0045] In this embodiment, since the conductive component 31 and the integrated circuit 201 are not simultaneously disposed in the support surface 10a of the substrate 10, but are stacked in the thickness direction, and an air gap is formed between the conductive component 31 and the integrated circuit 201 by a first distance D1, the heat generated by the conductive component 31 is quickly dissipated without affecting the working performance of the integrated circuit 201. At the same time, the heat generated by the integrated circuit 201 during operation is conducted and dissipated through the gap formed by the first distance D1, so that the heat generated by the integrated circuit 201 can also be quickly dissipated, ensuring the safety and reliability of the overall component operation of the system-level stacked structure 1.

[0046] Furthermore, the conductive component 31 only requires connection and support from the conductive connection element 203 on the surface of the substrate 10, effectively reducing the area and weight occupied by the conductive component 31 on the substrate 10. This effectively improves the power density of the SIP package structure and results in lower thermal resistance when the conductive component 31 carries a large current under a heat dissipation structure, thereby effectively improving the yield of the system-level stacked structure 1. In addition, the arrangement of the conductive component 31 allows the use of standard devices during the development of the system-level stacked structure, effectively simplifying the design structure and shortening the development and design time of the system-level stacked structure.

[0047] Please see Figure 6 This is an example of the second embodiment of the present utility model. Figure 2 The diagram shows a cross-sectional view of the system-level stacked structure along line III-III, where... Figure 6 The system-level stacking structure 2 shown is... Figure 3 to 5The system-level stacked structure 1 shown is basically the same, the only difference being that a heat-conducting layer 40 is provided in the gap between the conductive component 31 and the integrated circuit 201.

[0048] Specifically, such as Figure 6 As shown, in the substrate 10, the support surface 10a and the connecting surface 10b on opposite sides are used to support and mount the integrated circuit layer 20. In this embodiment, the substrate 10, the support surface 10a, and the connecting surface 10b are all provided with corresponding conductive lines (printed traces) to facilitate the electrical connection of electronic components mounted on the support surface 10a of the substrate 10. The connecting surface 10b is provided with multiple conductive pins P, which are electrically connected to the electronic components in the integrated circuit layer 20 and the conductive component layer 30 through the conductive lines inside the substrate 10. The system-level stacked structure 2 is connected to other electronic modules through the multiple conductive pins P. In this embodiment, the substrate 10 can be a PCB circuit board, or a substrate made of resin or other materials.

[0049] The integrated circuit layer 20 includes multiple integrated circuits and discrete electronic components that work together. Specifically, the integrated circuit layer 20 includes multiple integrated circuits 201 and multiple discrete components 202. The integrated circuits 201 can be integrated chips. For example, when the system-level stacked structure 2 is a power management chip in a power module, the integrated circuit 201 can be a chip containing operational amplifier circuits, a chip containing transformer circuits such as boost or buck circuits, a microprocessor management chip, etc. Of course, the system-level stacked structure 2 can also be other integrated packaged chips, and is not limited to this example.

[0050] The discrete components 202 may include resistors, capacitors, inductors, transformer windings or other electronic components. The discrete components 202 are interconnected with each other through conductive traces in the substrate 10 and electrically connected to the integrated circuit 201 to form corresponding functional circuits.

[0051] In this embodiment, the integrated circuit 201 has a first height H1 in the direction perpendicular to the support surface 10a, that is, the thickness of the integrated circuit 201 is the first height H1, wherein the discrete element 202 has a dimension smaller than the first height H1 in the direction perpendicular to the support surface 10a.

[0052] The integrated circuit layer 20 further comprises a plurality of conductive connecting elements 203 arranged along the edge of the substrate 10, and the conductive connecting elements 203 have a second height H2 in the direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In the embodiment, the number and position of the conductive connecting elements 203 can be adjusted according to actual needs, and the material of the conductive connecting elements 203 can be a conductive metal material such as copper or aluminum or other conductive materials.

[0053] The conductive element layer 30 at least comprises a conductive component 31, wherein the conductive component 31 is located on the surface of the plurality of integrated circuits 201 and the plurality of discrete elements 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects the conductive connecting elements 203. Correspondingly, since the height of the conductive connecting elements 203 is greater than the height of the integrated circuits 201, the conductive component 31 connected with the conductive connecting elements 203 is spaced from the integrated circuits 201 by a first distance D1 in the direction perpendicular to the substrate 10. In other words, the conductive component 31 has a gap with the integrated circuits 201 by the first distance D1 in the direction perpendicular to the substrate 10.

[0054] In the embodiment, the conductive component 31 is an inductor, wherein the conductive pins (not shown) of the inductor are connected to the conductive connecting elements 203. The number of the pins of the inductor directly corresponds to the number of the conductive connecting elements 203. In the embodiment, when the inductor is a single-winding inductor, the inductor includes two conductive pins at different positions, and the number of the conductive connecting elements 203 is also two, which are arranged at positions corresponding to the pin positions of the inductor.

[0055] The heat conduction layer 40 is arranged between the conductive component 31 and the integrated circuits 201, or in other words, the gap between the conductive component 31 and the integrated circuits 201 is filled with the heat conduction layer 40.

[0056] In the embodiment, the thermal conductivity of the heat conduction layer 40 is at least greater than the thermal conductivity of the conductive component 31 and the integrated circuits 201, and the greater the thermal conductivity of the heat conduction layer 40, the better the uniform temperature and heat dissipation effect.

[0057] In the embodiment of the utility model, the thermal conductivity of the heat conduction layer 40 ranges from 5 W / mK to 20 W / mK, for example, the thermal conductivity of the heat conduction layer 40 can be 6 W / mK or 12 W / mK, so that the heat conduction layer 40 maintains the desired uniform temperature and more uniform heat dissipation effect. Of course, the thermal conductivity of the heat conduction layer 40 can be adjusted according to actual needs, and is not limited to this example.

[0058] In the embodiment, the material of the heat conduction layer 40 is selected from heat conduction gel, which has better heat conduction and heat dissipation performance, thereby achieving uniform heat dissipation.

[0059] In the embodiment, the conductive component 31 and the integrated circuit 201 are not arranged in the support surface 10a of the substrate 10 at the same time, but are arranged in the thickness direction, and the heat conduction layer 40 is arranged between the conductive component 31 and the integrated circuit 201, so that the heat generated by the conductive component 31 is quickly dissipated without affecting the working performance of the integrated circuit 201, and the heat generated by the integrated circuit 201 during working is conducted and dissipated through the heat conduction layer 40, so that the heat generated by the integrated circuit 201 can also be quickly dissipated, thereby ensuring the safety and reliability of the working of the overall elements of the system-level stacked structure 2.

[0060] Please refer to Figure 7 , Figure 8 and Figure 9 , Figure 7 , as shown in the system-level stacked structure along the III-III line profile structure schematic view of the third embodiment of the utility model Figure 2 , Figure 8 , as shown in the system-level stacked structure along the IV-IV line profile structure schematic view of the third embodiment of the utility model Figure 2 , Figure 9 , as shown in the partial structure top view of the system-level stacked structure of the third embodiment of the utility model Figure 2 , Figure 9 , as shown in the top view of the integrated circuit layer 20 in the system-level stacked structure Figure 2 .

[0061] Among them, the system-level stacked structure 2 and the system-level stacked structure 1 shown in the structure are basically the same, and the difference is only that the structure of the conductive component 31 is different. Figure 3 to 5

[0062] Specifically, as shown in Figure 7 to 9 ​As shown, the support surface 10a and the connecting surface 10b of the substrate 10, the support surface 10a is used to support and dispose the integrated circuit layer 20. In this embodiment, the support surface 10a and the connecting surface 10b of the substrate 10 are both provided with corresponding conductive lines (printed traces) to facilitate the electrical connection of the electronic components disposed on the support surface 10a of the substrate 10. The connecting surface 10b is provided with a plurality of conductive pins P, which are electrically connected to the electronic components in the integrated circuit layer 20 and the conductive element layer 30 through the conductive lines inside the substrate 10, and the system-level stacked structure 3 is connected to other electronic modules through the plurality of conductive pins P. In this embodiment, the substrate 10 can be a PCB circuit board, or a substrate made of resin or other materials.

[0063] The integrated circuit layer 20 includes a plurality of integrated circuits and auxiliary matching discrete electronic components. Specifically, the integrated circuit layer 20 includes a plurality of integrated circuits 201 and a plurality of discrete components 202. The integrated circuits 201 can be integrated chips. In this embodiment, the integrated circuits 201 are connected to the conductive lines in the substrate 10 through conductive hardware (not shown). For example, when the system-level stacked structure 3 is a power management chip, the integrated circuits 201 can be chips containing operational amplifier circuits, chips containing voltage conversion circuits such as boost circuits or buck circuits, microprocessor management chips, etc. Of course, the system-level stacked structure 2 can also be other integrated packaged chips, and is not limited to the examples.

[0064] The plurality of discrete components 202 can include resistors, capacitors, inductors, transformer windings, or other electronic components. The plurality of discrete components 202 are connected to each other and to the integrated circuits 201 through the conductive traces inside the substrate 10 to form corresponding functional circuits.

[0065] In this embodiment, the integrated circuits 201 have a first height H1 in the direction perpendicular to the support surface 10a, i.e., the thickness dimension of the integrated circuits 201 is the first height H1, and the discrete components 202 have a dimension along the direction perpendicular to the support surface 10a that is less than the first height H1.

[0066] The integrated circuit layer 20 further includes a plurality of conductive connection elements 203 disposed along the edge of the substrate 10, and the conductive connection elements 203 have a second height H2 in the direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In this embodiment, the number and position of the conductive connection elements 203 can be adjusted according to actual needs, and the material of the conductive connection elements 203 can be a conductive metal material such as copper or aluminum, or other conductive materials.

[0067] The conductive element layer 30 at least comprises a conductive component 31, wherein the conductive component 31 is located on the surface of the plurality of integrated circuits 201 and the plurality of discrete components 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects the conductive connecting elements 203, and correspondingly, since the height of the conductive connecting elements 203 is greater than the height of the integrated circuits 201, the conductive component 31 connected with the conductive connecting elements 203 is spaced apart from the integrated circuits 201 by a first distance D1 in the direction perpendicular to the substrate 10, in other words, the conductive component 31 has a gap with the integrated circuits 201 by the first distance D1 in the direction perpendicular to the substrate 10.

[0068] In the embodiment, the conductive component 31 is an inductor, wherein the conductive pins (not shown) of the inductor are connected to the conductive connecting elements 203, and the inductor is a double-winding inductor, comprising two groups of four conductive pins in different positions, and the number of the conductive connecting elements 203 is also two groups of four, which are arranged at positions corresponding to the pin positions of the inductor.

[0069] In the embodiment, since the conductive component 31 and the integrated circuits 201 are not arranged in the support surface 10a of the substrate 10 at the same time, but are arranged in the thickness direction, and the air gap is formed between the conductive component 31 and the integrated circuits 201 by the first distance D1, the heat generated by the conductive component 31 is quickly dissipated without affecting the working performance of the integrated circuits 201, and at the same time, the heat generated by the integrated circuits 201 in the working process is conducted and dissipated through the gap formed by the first distance D1, so that the heat generated by the integrated circuits 201 can also be quickly dissipated, thereby ensuring the safety and reliability of the overall element working of the system-level stacked structure 3.

[0070] Please refer to Figure 10 which is a functional block diagram of the electronic equipment 100 in an embodiment of the present application. In the embodiment, the electronic equipment 100 comprises functional modules and Figure 1 to 9 The system-level stacked structure in the electronic equipment 100 is connected with and cooperates with the functional modules to realize the corresponding preset functions of the electronic equipment 100. For example, when the system-level stacked structure is a power management chip, the functional modules can be a processor (CPU), a graphics processing unit (GPU), and a peripheral circuit, or a display screen, a loudspeaker, and other workloads, and the power management chip is used to provide a driving power source for the functional modules. Of course, in other embodiments of the present application, the conductor device stacked package structure can also be a storage chip, a processor, and the like, and is not limited to the above examples. Since Figure 1 to 9 The system-level stacked structures 1-3 have good safety and reliability, and thus the electronic equipment 100 has good safety and reliability.

[0071] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0072] The above-described embodiments do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described embodiments shall be included in the protection scope of the technical solution.

Claims

1. A system-in-a-stack structure, comprising: Comprising: a substrate comprising a support surface; at least one integrated circuit and a conductive connecting element disposed on the support surface in parallel with the integrated circuit; a conductive component disposed on the conductive connecting element and the surface of the integrated circuit, the conductive component connecting the conductive connecting element and electrically connecting with the integrated circuit, the conductive component and the integrated circuit being spaced apart by a first distance in a direction perpendicular to the support surface.

2. The system-in-a-stack structure of claim 1, wherein, a thermally conductive layer disposed between the conductive component and the integrated circuit, the thermally conductive layer being used to conduct heat generated by the integrated circuit and / or the conductive component.

3. The system-in-a-stack structure of claim 1, wherein, The conductive component is an inductor, and a conductive pin of the inductor connects the conductive component.

4. The system-in-a-stack structure of claim 3, wherein, The inductor is a single-winding inductor or a double-winding inductor.

5. The system-in-a-stack structure of claim 4, wherein, The system-level stacked structure comprises a plurality of conductive connecting elements disposed at different positions.

6. The system-in-a-stack structure of claim 5, wherein, A plurality of separate conductive connecting elements are disposed at positions around the periphery of the substrate at a predetermined distance.

7. The system-in-a-stack structure of any one of claims 1-6, wherein, The material of the conductive connecting element is copper.

8. The system-in-a-stack structure of claim 7, wherein, The system-level stacked structure further comprises a plurality of discrete elements disposed on the support surface in parallel with the integrated circuit and electrically connected with the integrated circuit and / or the conductive component through a conductive circuit.

9. The system-in-a-stack structure of claim 8, wherein, The system-level stacked structure is a power module of a system-in-package.

10. An electronic device, comprising: A functional module connected with the system-level stacked structure of any one of claims 1-9 to perform a predetermined function.

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