Ceramic insulating substrate and packaging structure

Abstract

The utility model provides a ceramic insulation substrate and a packaging structure, the ceramic insulation substrate comprises a first metal layer, a second metal layer and a ceramic layer clamped between the first metal layer and the second metal layer, and the ceramic layer is an aluminum oxynitride layer. According to the ceramic insulation substrate, the aluminum oxynitride layer is used as the middle ceramic layer, and the dielectric constant of the aluminum oxynitride layer is lower than that of aluminum oxide and aluminum nitride, so that the thickness of the ceramic layer can be further reduced on the premise of meeting the electrical insulation function, and the overall heat dissipation function of the ceramic insulation substrate is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to a ceramic insulating substrate and packaging structure. Background Technology

[0002] With the rapid development of the new energy industry, semiconductor power modules have been widely used in high-power, high-voltage environments. These modules place higher demands on the current-carrying capacity, insulation withstand voltage, and efficient heat dissipation capabilities of the substrate. Ceramic insulating substrates, due to their high current-carrying capacity, high withstand voltage, and high heat dissipation, have become an ideal choice for power modules.

[0003] There are two main types of ceramic insulating substrates: one is the direct bond copper (DBC) substrate, which is widely used in the packaging and heat dissipation of devices such as IGBT power modules, lasers (LDs) and photovoltaics (PVs); the other is the active metal brazing (AMB) substrate. Because the AMB substrate can achieve better heat dissipation and insulation performance and higher reliability, it can be used to support high-power chips and is mainly used in electric vehicle power modules.

[0004] Currently, the ceramic layers in ceramic insulating substrates mainly include Al2O3, AlN, and Si3N4. These three ceramic materials have similar dielectric constants, all ranging from 8 to 10. For electrical insulation and product operational stability, the industry generally ensures that the thickness of the ceramic layer is greater than or equal to 250 micrometers. However, the thermal path of the ceramic layer is the dominant heat dissipation path for power modules, and an excessively thick ceramic layer is detrimental to heat dissipation. Utility Model Content

[0005] In view of the above problems, the purpose of this disclosure is to provide a ceramic insulating substrate and packaging structure, which can reduce the thickness of the ceramic layer and improve heat dissipation by setting the ceramic layer as an aluminum oxynitride layer, while ensuring electrical insulation performance.

[0006] According to one aspect of the present disclosure, a ceramic insulating substrate is provided, comprising a first metal layer, a second metal layer, and a ceramic layer sandwiched between the first metal layer and the second metal layer.

[0007] The ceramic layer is an aluminum oxynitride layer.

[0008] Optionally, both the first metal layer and the second metal layer are copper layers.

[0009] Optionally, the thickness of the ceramic layer ranges from 10 to 100 micrometers.

[0010] Optionally, the thickness of the first metal layer is 150 to 200 micrometers.

[0011] According to another aspect of the embodiments of this disclosure, a packaging structure is provided, including:

[0012] Ceramic insulating substrate;

[0013] The die is fixed on the ceramic insulating substrate; and

[0014] The signal terminal is fixed on the ceramic insulating substrate and separated from the die.

[0015] The ceramic insulating substrate includes a first metal layer, a second metal layer, and a ceramic layer sandwiched between the first metal layer and the second metal layer.

[0016] The ceramic layer is an aluminum oxide layer.

[0017] Optionally, the die is used to form a power semiconductor device.

[0018] Optionally, both the first metal layer and the second metal layer are copper layers.

[0019] Optionally, the thickness of the ceramic layer ranges from 10 to 100 micrometers.

[0020] Optionally, the thickness of the first metal layer is 150 to 200 micrometers.

[0021] One of the above technical solutions has the following beneficial effects:

[0022] Compared to the three conventional ceramic materials Al2O3, AlN, and Si3N4, AlON has a lower dielectric constant. After optimization, the dielectric constant of AlON can reach half or even lower than that of conventional ceramic materials. Moreover, AlON has higher strength than Al2O3 and AlN.

[0023] Because AlON has a lower dielectric constant than conventional ceramic materials, the thickness of the ceramic layer can be further reduced while meeting electrical insulation requirements and product operational stability. The thickness of the AlON layer can be as low as 10 to 100 micrometers, thereby reducing the thermal resistance of the entire package heat dissipation path. This allows the heat generated by the power die to be conducted to the external environment more efficiently, greatly improving the reliability and lifespan of power module products, and promoting the thinning and lightening of packaged power modules.

[0024] In addition, compared with aluminum, copper has better heat dissipation performance, which further improves the overall heat dissipation performance of the ceramic insulating substrate composed of Cu+AlON+Cu.

[0025] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only involve some embodiments of this disclosure, and are not intended to limit this disclosure.

[0027] Figure 1 A schematic diagram of a partial packaging structure according to an embodiment of the present disclosure is shown.

[0028] Figure 2 It shows Figure 1 A schematic diagram of the external frame of the encapsulation structure. Detailed Implementation

[0029] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0030] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0031] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0032] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0033] Figure 1 A partial packaging structure schematic diagram of an embodiment of this disclosure is shown. Figure 2 It shows Figure 1 A schematic diagram of the external frame of the encapsulation structure.

[0034] See Figure 1 The packaging structure in this embodiment includes: a ceramic insulating substrate 100, one or more dies 200, a signal terminal 300, a fixing layer 10, a bonding wire 20, and a pin-fin 30.

[0035] See Figure 2 The packaging structure in this embodiment further includes an outer frame consisting of a heat dissipation base plate 11, a frame 12, a sealant 13, and a cover plate 14. The outer frame encloses and forms a receiving cavity 500. The receiving cavity 500 is filled with potting gel, thereby covering and protecting the ceramic insulating substrate 100, die 200, signal terminal 300, fixing layer 10, bonding wire 20, and needle-shaped sheet 30 located inside the receiving cavity 500. The needle-shaped sheet 30 and the signal terminal 300 respectively extend out of the outer frame from inside the receiving cavity 500.

[0036] The ceramic insulating substrate 100 includes a first metal layer 121, a second metal layer 122, and a ceramic layer 110 sandwiched between the first metal layer 121 and the second metal layer 122, wherein the ceramic layer 110 is an aluminum oxynitride (AlON) layer.

[0037] In some embodiments, the thickness of the ceramic layer 110 ranges from 10 to 100 micrometers.

[0038] In some embodiments, both the first metal layer 121 and the second metal layer 122 are copper layers.

[0039] In some embodiments, the thickness of the first metal layer 121 ranges from 150 to 200 micrometers.

[0040] Die 200 is used to form power semiconductor devices, including discrete devices and power integrated circuits (Power ICs). Discrete devices include bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), thyristors, etc. Die 200 is fixed to a first metal layer 121 by a fixing layer 10. The fixing layer 10 is a conductive adhesive or an insulating adhesive, and may also be a solder / sintered metal layer. Signal terminals 300 are fixed to the first metal layer 121 by soldering or sintering processes, with their ends extending beyond the edge of the first metal layer 121. Signal terminals 300 are separated from die 200. The upper surface of die 200 is connected to a predetermined position on the first metal layer 121 by bonding wires 20. The first metal layer 121 has a predetermined pattern for forming the connection circuit between die 200 and signal terminals 300. Needle-shaped tabs 30 are located on the upper surface of die 200 and can be used for heat dissipation or as test pins during chip testing.

[0041] When the die 200 is working, the heat generated by the die 200 can be transferred sequentially along the fixing layer 10, the first metal layer 121, the ceramic layer 110 (AlON layer), and the second metal layer 122 to the lower structure, such as to the heat sink 11, and then transferred by the heat sink 11 to the heat sink, thereby transferring the heat to the external environment of the package structure.

[0042] Compared to the three conventional ceramic materials Al2O3, AlN, and Si3N4, AlON has a lower dielectric constant. After optimization, the dielectric constant of AlON can reach half or even lower than that of conventional ceramic materials. Moreover, AlON has higher strength than Al2O3 and AlN.

[0043] Because AlON has a lower dielectric constant than conventional ceramic materials, the thickness of the ceramic layer can be further reduced while meeting electrical insulation requirements and product operational stability. The thickness of the AlON layer can be as low as 10 to 100 micrometers, thereby reducing the thermal resistance of the entire package heat dissipation path. This allows the heat generated by the power die to be conducted to the external environment more efficiently, greatly improving the reliability and lifespan of power module products, and promoting the thinning and lightening of packaged power modules.

[0044] In addition, compared with aluminum, copper has better heat dissipation performance, which further improves the overall heat dissipation performance of the ceramic insulating substrate composed of Cu+AlON+Cu.

[0045] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A ceramic insulating substrate, characterized by, comprise a first metal layer, a second metal layer, and a ceramic layer sandwiched between the first metal layer and the second metal layer, wherein the ceramic layer is an aluminum oxynitride layer.

2. The ceramic insulating substrate according to claim 1, characterized by The first metal layer and the second metal layer are both copper layers.

3. The ceramic insulating substrate according to claim 1 or 2, characterized by The ceramic layer has a thickness in a range of 10 to 100 micrometers.

4. The ceramic insulating substrate according to claim 1 or 2, characterized by The first metal layer has a thickness of 150 to 200 micrometers.

5. A package structure, characterized by, comprise: a ceramic insulating substrate; a die fixed on the ceramic insulating substrate; and a signal terminal fixed on the ceramic insulating substrate and separated from the die, wherein the ceramic insulating substrate comprises a first metal layer, a second metal layer, and a ceramic layer sandwiched between the first metal layer and the second metal layer, the ceramic layer is an aluminum oxynitride layer.

6. The package structure of claim 5, wherein, The die is used to form a power semiconductor device.

7. The package structure of claim 5, wherein, The first metal layer and the second metal layer are both copper layers.

8. The package structure of any one of claims 5 to 7, wherein, The ceramic layer has a thickness in a range of 10 to 100 micrometers.

9. The package structure of any one of claims 5 to 7, wherein, The first metal layer has a thickness of 150 to 200 micrometers.

Images