ESD protection circuit and chip

Abstract

The utility model discloses an ESD (Electro-Static Discharge) protection circuit and a chip. The ESD protection circuit comprises a plurality of transistors; the input end of each transistor is connected with an electrostatic discharge pin of a chip, and the output end of each transistor is connected with a ground end, so that current flowing into the input end of each transistor is discharged to the ground end through the output end of the corresponding transistor. According to the ESD protection circuit, the current circulation path can be shortened, and the generation of a long U-shaped current path is avoided, so that the conduction uniformity of the ESD protection circuit is improved, the conduction capability and the voltage resistance capability of the ESD protection circuit are improved, and the related performance of a corresponding chip is improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to an ESD protection circuit and chip. Background Technology

[0002] In the electronics industry, static electricity is one of the main causes of damage to electronic devices. ESD (electrostatic discharge) protection circuits can discharge static electricity at the pins of chips, thus preventing damage to chips and other electronic devices to a certain extent. Therefore, ESD protection is widely used in various fields that require stable operation of electronic equipment, especially in the electronics, IT and communications, and automotive industries.

[0003] The inventors discovered during their research on ESD protection circuits that traditional ESD protection circuits suffer from insufficient conduction uniformity. Utility Model Content

[0004] In view of this, this application provides an ESD protection circuit and chip to solve the problem of insufficient conduction uniformity in traditional ESD protection circuits.

[0005] This application provides an ESD protection circuit, which includes a plurality of transistors;

[0006] The input terminal of each transistor is connected to the electrostatic discharge pin of the chip, and the output terminal is connected to the ground terminal, so as to discharge the current flowing into the input terminal of the transistor to the ground terminal through the corresponding output terminal of the transistor.

[0007] Optionally, each of the transistors further includes a control terminal; the control terminal is used to receive a signal that turns on the corresponding transistor.

[0008] Optionally, the transistor includes an NMOS transistor; the drain of the NMOS transistor is the input terminal, connected to the electrostatic discharge pin of the chip, the source is the output terminal, connected to ground, and the gate is the control terminal, used to receive a low-level signal.

[0009] Optionally, the transistor includes a GG NMOS transistor; the drain of the GG NMOS transistor is connected to the electrostatic discharge pin of the chip, and the gate, source and substrate are all connected to ground.

[0010] Optionally, the number of transistors ranges from 25 to 35.

[0011] Optionally, the number of transistors is 30.

[0012] This application also provides a chip, which includes any of the above-described ESD protection circuits.

[0013] In the ESD protection circuit and chip described in this application, the input terminal of each transistor is connected to the electrostatic discharge pin of the chip, and the output terminal is connected to the ground terminal. Each transistor can directly discharge the current and / or charge at the electrostatic discharge pin to the ground terminal through the corresponding transistor, without having to input from the input terminal of the first transistor in the electrostatic discharge path, flow through each transistor in the electrostatic discharge path in sequence, and finally output from the output terminal of the last transistor in the electrostatic discharge path to the ground terminal. This can shorten the current flow path, avoid the generation of a long U-shaped current path, thereby improving the uniformity of ESD protection circuit conduction, improving the ESD protection circuit's conduction capability and voltage resistance capability, and enhancing the relevant performance of the corresponding chip. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the ESD protection circuit structure during the research process;

[0016] Figure 2 This is a schematic diagram of the current flow in the ESD protection circuit during the research process;

[0017] Figure 3 This is a schematic diagram of an ESD protection circuit structure according to an embodiment of this application;

[0018] Figure 4 This is a schematic diagram of an ESD protection circuit structure according to another embodiment of this application;

[0019] Figure 5 This is a schematic diagram of a GG NMOS transistor according to an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of the current flow in an ESD protection circuit according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0022] The inventors studied ESD protection circuits and discovered that they include multiple electrostatic discharge paths, each of which may include multiple transistors connected in sequence, such as the reference... Figure 1 As shown, transistors Q1 and Q2 are the first transistors in the left and right electrostatic discharge paths, respectively. Figure 1 The protection mechanism of the ESD protection circuit shown includes: when the drain voltage is very small, the reverse leakage current of the diode between the drain and the PSUB (substrate) is also very small. When the voltage increases to Vt1, the reverse diode between the drain and the substrate undergoes avalanche breakdown and carrier multiplication, thus increasing the current flowing to ground through the substrate. When the voltage to the left of R4 or R6 reaches 0.7V, Q1 or Q2 turns on first, entering the ESD protection mode. R0 to R10 are the substrate parasitic resistances, and all NPN transistors can be parasitic lateral BJTs (bipolar junction transistors) of GGNMOS. In each electrostatic discharge path, the input terminal of the first transistor can be connected to the electrostatic discharge pin, and the output terminal of the last transistor is connected to ground. This allows the charge at the electrostatic discharge pin to flow from the input terminal of the first transistor through the entire corresponding electrostatic discharge path and finally discharge from the output terminal of the last transistor to ground, thereby achieving electrostatic direction. Figure 1 The electrostatic discharge path shown has a U-shaped current path during discharge, as illustrated in the reference diagram. Figure 2 As shown, Figure 2 The direction indicated by "China Construction Investment" represents the direction of current. This current path has the problems of long path length and insufficient conduction uniformity, which can easily affect the performance of the chip.

[0023] The first aspect of this application provides an ESD protection circuit, which is disposed within a chip that requires electrostatic discharge protection.

[0024] refer to Figure 3 As shown, the above ESD protection circuit includes multiple transistors, for example... Figure 3 The ESD protection circuit shown includes multiple transistors, such as transistor 1, transistor 2, ..., transistor (n-1) and transistor n; where n is the number of transistors in the ESD protection circuit, and n≥2. The input terminal of each transistor is connected to the electrostatic discharge pin PAD of the chip, and the output terminal is connected to ground GND. This allows the current and / or charge flowing from the electrostatic discharge pin PAD into the input terminal of each transistor to be directly discharged to ground GND through the corresponding transistor output terminal, without needing to enter from the input terminal of the first transistor in the electrostatic discharge path, flow sequentially through each transistor in the electrostatic discharge path, and finally output to ground GND from the output terminal of the last transistor in the electrostatic discharge path. This shortens the current flow path, avoids generating a long U-shaped current path, thereby improving the uniformity of ESD protection circuit conduction, enhancing the ESD protection circuit's conduction capability, and improving the relevant performance of the corresponding chip.

[0025] Optionally, the number of transistors ranges from 25 to 35. For example, the number of transistors in the ESD protection circuit can be 25, 28, 30, 32, or 35, etc., to ensure that the ESD protection circuit corresponding to the electrostatic discharge pin PAD has sufficient electrostatic discharge capability. Preferably, the number of transistors is 30, to make the ESD protection circuit corresponding to the electrostatic discharge pin PAD more stable and reliable.

[0026] In some embodiments, each of the transistors further includes a control terminal ( Figure 3 (Not shown in the diagram), for example, if the transistor is a MOSFET, the control terminal can be the gate of the corresponding MOSFET. The control terminal is used to receive a signal that turns on the corresponding transistor, so that when the current and / or charge at the electrostatic discharge pin PAD flows into the input terminal of the transistor, the corresponding transistor turns on, and the current and / or charge at the electrostatic discharge pin PAD can flow into the ground terminal GND through the corresponding transistor. Optionally, the control terminal of the transistor can be connected to a low-level signal or ground terminal GND, so that when the current and / or charge at the electrostatic discharge pin PAD flows into the input terminal of the transistor, the corresponding transistor turns on.

[0027] In some examples, reference Figure 4 As shown, the transistor includes NMOS transistors, such as multiple NMOS transistors including N1, N2, ..., N(n-1) and Nn. The drain of the NMOS transistor is the input terminal, connected to the electrostatic discharge pin PAD of the chip; the source of the NMOS transistor is the output terminal, connected to ground GND; the gate of the NMOS transistor is the control terminal, used to receive a low-level signal; optionally, the gate of the NMOS transistor is connected to ground GND.

[0028] In some embodiments, the transistor includes a GG NMOS transistor; Reference Figure 5 As shown, the drain of the GG NMOS transistor is connected to the electrostatic discharge pin PAD of the chip, and the gate, source, and substrate are all connected to ground GND. Optionally, the substrate of the GG NMOS transistor includes a P-substrate.

[0029] The layout diagrams of the ESD protection circuits provided in the various embodiments of this application in the corresponding chips can be referred to. Figure 6 As shown, the arrows indicate the direction of current or charge flow. Figure 6As shown, the current and / or charge flowing from the electrostatic discharge pin PAD into the input terminals of each transistor is directly discharged to the ground GND through the corresponding transistor output terminal, without needing to be input from the input terminal of the first transistor in the electrostatic discharge path. Instead, the current flows sequentially through each transistor in the electrostatic discharge path and is finally output to the ground GND from the output terminal of the last transistor in the electrostatic discharge path. This shortens the current flow path, avoids the generation of a long U-shaped current path, thereby improving the uniformity of ESD protection circuit conduction, enhancing the ESD protection circuit's conduction capability and voltage withstand capability, and improving the relevant performance of the corresponding chip.

[0030] In the above ESD protection circuit, the input terminal of each transistor is connected to the electrostatic discharge pin PAD of the chip, and the output terminal is connected to the ground GND. Each transistor can directly discharge the current and / or charge at the electrostatic discharge pin PAD to the ground GND through the corresponding transistor, without having to input it from the input terminal of the first transistor in the electrostatic discharge path, and then sequentially flow through each transistor in the electrostatic discharge path, finally outputting to the ground GND from the output terminal of the last transistor in the electrostatic discharge path. This can shorten the current flow path, avoid generating a long U-shaped current path, thereby improving the uniformity of the ESD protection circuit conduction, enhancing the ESD protection circuit's conduction capability and voltage withstand capability, and improving the relevant performance of the corresponding chip.

[0031] A second aspect of this application provides a chip that includes at least one ESD protection circuit as described in any of the above embodiments. Specifically, the ESD protection circuit can be located at a pin within the chip that requires electrostatic discharge protection (such as an electrostatic discharge pin).

[0032] Optionally, each pin requiring electrostatic discharge protection can be equipped with a corresponding ESD protection circuit.

[0033] The chip described above includes the ESD protection circuit described in any of the above embodiments and has all the beneficial effects of the ESD protection circuit described in any of the above embodiments, which will not be repeated here.

[0034] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0035] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0036] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0037] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. An ESD protection circuit, characterized by, The ESD protection circuit comprises a plurality of transistors; An input end of each transistor is connected to an electrostatic discharge pin of a chip, and an output end is connected to a ground end, so as to discharge the current flowing into the input end of the transistor to the ground end through the corresponding output end of the transistor.

2. The ESD protection circuit of claim 1, wherein, Each transistor further comprises a control end for inputting a signal for turning on the corresponding transistor.

3. The ESD protection circuit of claim 2, wherein, The transistor comprises an NMOS transistor. The drain of the NMOS transistor is the input end connected to the electrostatic discharge pin of the chip, the source is the output end connected to the ground end, and the gate is the control end for inputting a low-level signal.

4. The ESD protection circuit of claim 1, wherein, The transistor comprises a GG NMOS transistor. The drain of the GG NMOS transistor is connected to the electrostatic discharge pin of the chip, and the gate, the source and the substrate are all connected to the ground end.

5. The ESD protection circuit of claim 1, wherein, The number of the transistors ranges from 25 to 35.

6. The ESD protection circuit of claim 5, wherein, The number of the transistors is 30.

7. A chip, characterized by The chip comprises at least one ESD protection circuit as claimed in any one of claims 1 to 6.

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