Surge voltage suppression control circuit and electrical equipment

Abstract

The utility model provides a surge voltage suppression control circuit and electrical equipment, which comprises a power supply circuit, a switch circuit, a multi-stage surge suppression circuit and a post-stage circuit which are connected in sequence, the multi-stage surge suppression circuit comprises a first-stage suppression circuit to an Nth-stage suppression circuit which are connected in series, and N is a positive integer greater than or equal to 2. Each stage of suppression circuit comprises an MOS tube, a surge suppression trigger circuit and a sampling circuit; for the first-stage suppression circuit, the source electrode of the MOS tube is connected with one output end of the sampling circuit, the first end of the surge suppression trigger circuit and the drain electrode of the MOS tube are connected with the positive voltage end of the power supply circuit, and the second end, the third end and the fourth end of the surge suppression trigger circuit are connected with the other output end of the sampling circuit, the grid electrode of the MOS tube and the input end of the sampling circuit respectively. According to the technical scheme, the problem that high-voltage surge suppression cannot be achieved due to the fact that the dissipation power of the MOS tube is too large in the prior art can be solved.

Description

TECHNICAL FIELD

[0001] The utility model mainly relates to the direct current source protection technical field especially, relates to a kind of surge voltage suppression control circuit and electrical equipment. BACKGROUND

[0002] In existing electrical equipment, in order to solve the problem of surge voltage, a MOS tube and a surge suppression trigger circuit are generally connected between the positive voltage end and the negative voltage end of the power supply circuit. The surge suppression trigger circuit continuously monitors the supply voltage, and if a surge voltage is generated, the output voltage is adjusted to a clamping voltage, and the remaining voltage is applied to the MOS tube. However, this can cause the dissipation power of the MOS tube to be too large, and in the case of high voltage surge, it can exceed the safe operating area of the MOS tube, causing damage to the MOS tube. SUMMARY

[0003] The utility model solves the technical problem of providing a surge voltage suppression control circuit and electrical equipment to overcome the problem of excessive dissipation power of the MOS tube in the prior art, which cannot achieve high voltage surge suppression.

[0004] In a first aspect, the utility model provides a surge voltage suppression control circuit, which includes a power supply circuit, a switching circuit, a multi-stage surge suppression circuit and a post-stage circuit connected in sequence. The multi-stage surge suppression circuit includes a first-stage suppression circuit to an Nth-stage suppression circuit connected in series, where N is a positive integer greater than or equal to 2. Each suppression circuit includes a MOS tube, a surge suppression trigger circuit and a sampling circuit. Wherein,

[0005] For the first-stage suppression circuit, the source of the MOS tube is connected to an output of the sampling circuit, the first end of the surge suppression trigger circuit and the drain of the MOS tube are connected together with the positive voltage end of the power supply circuit, the second end, the third end and the fourth end are respectively connected to another output of the sampling circuit, the gate of the MOS tube and the input of the sampling circuit.

[0006] In some embodiments, for the second-stage suppression circuit to the Nth-stage suppression circuit, the source of the MOS tube is connected to an output of the sampling circuit, the first end of the surge suppression trigger circuit and the drain of the MOS tube are connected together with the corresponding output of the previous-stage suppression circuit, the second end, the third end and the fourth end are respectively connected to the corresponding another output of the previous-stage suppression circuit, the gate of the MOS tube and the input of the sampling circuit.

[0007] In some embodiments, the voltage at the output of the power supply circuit is configured to be 80V / 50ms.

[0008] In some embodiments, the clamping voltage of each stage of the suppression circuit is inversely proportional to the corresponding circuit depth.

[0009] In some embodiments, the MOS transistor is configured to be sequentially turned on according to a set trigger timing.

[0010] In some embodiments, the post-stage circuit comprises a first inductor, a second inductor, a switching element, a post-stage resistor and a post-stage capacitor.

[0011] The switching element is connected between the first inductor and the post-stage resistor, the second inductor is connected in parallel to the post-stage resistor, the positive pole of the post-stage capacitor is connected to the first inductor, and the negative pole of the post-stage capacitor is connected to the post-stage resistor away from one end of the switching element.

[0012] In some embodiments, the surge suppression trigger circuit comprises a master chip, a first resistor, a second resistor, a first capacitor, a second capacitor, a first sub-circuit and a second sub-circuit.

[0013] The first capacitor is connected between the first end and the second end of the master chip, the second capacitor is connected between the first resistor and the third end of the master chip, the first resistor is connected between the fourth end of the master chip and the first sub-circuit, the first sub-circuit is connected between the fifth end and the sixth end of the master chip, the second sub-circuit is connected between the seventh end and the eighth end of the master chip, the ninth end of the master chip is grounded, one end of the second resistor is connected together with the first end and the eighth end of the master chip, and the other end of the second resistor is grounded.

[0014] In some embodiments, the first sub-circuit comprises a first transistor, a third resistor, a fourth resistor, a fourth capacitor and a first diode.

[0015] The first end, the second end and the third end of the first transistor are connected to the third resistor, the first resistor and the sixth end of the master chip respectively, the fifth end of the master chip is connected to the third resistor and the fourth resistor, the first diode is connected in parallel to the fourth resistor, the fourth capacitor is connected in series to the fourth resistor, and one end of the fourth capacitor is grounded.

[0016] In some embodiments, the second sub-circuit comprises a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor and a second diode.

[0017] One end of the seventh resistor is connected with the fifth resistor, the other end of the seventh resistor is grounded, the sixth resistor and the fourth capacitor are connected in series and between the seventh end of the master control chip and the eighth end of the master control chip, one end of the third capacitor is connected with the negative electrode of the second diode, the other end of the third capacitor is connected with the positive electrode of the second diode, and the positive electrode of the second diode is connected with the eighth end of the master control chip.

[0018] In a second aspect, the application provides an electrical appliance, comprising the surge voltage suppression control circuit according to any one of the first aspect.

[0019] Compared with the prior art, the utility model has the following advantages:

[0020] The utility model provides a kind of surge voltage suppression control circuit and electrical equipment, to overcome the problem that the dissipation power of MOS tube is too large in prior art, cannot realize high voltage surge suppression.In the technical scheme, multiple surge suppression circuits are arranged between switching circuit and post-circuit, the first to Nth surge suppression circuit in multiple surge suppression circuits are connected in series, and each suppression circuit includes MOS tube, surge suppression trigger circuit and sampling circuit, when surge voltage occurs, N sampling circuits therein can work at different clamping voltages, and N MOS tubes collectively share overall residual voltage, so that the problem of the dissipation power of single MOS tube being too large is overcome, effectively avoiding the damage of MOS tube, while clamping voltage is flexibly controllable, suitable for high reliability DC power supply occasions under high voltage surge condition. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute apart of this application, illustrate embodiments of the application, and together with the description serve to explain the principles of the application. In the drawings:

[0022] Figure 1 The schematic diagram of the first surge voltage suppression control circuit is shown;

[0023] Figure 2 The schematic diagram of an exemplary post-circuit is shown;

[0024] Figure 3 The schematic diagram of an exemplary surge suppression trigger circuit is shown;

[0025] Figure 4 The schematic diagram of the second surge voltage suppression control circuit is shown;

[0026] Figure 5 The schematic diagram of the third surge voltage suppression control circuit is shown. DETAILED DESCRIPTION

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those skilled in the art, the present application can also be applied to other similar scenarios without creative labor on the basis of the drawings. Unless it is obvious from the language environment or otherwise stated, the same reference numbers in the drawings represent the same structure or operation.

[0028] Figure 1 A schematic diagram of a first surge voltage suppression control circuit is shown; Figure 2 A schematic diagram of an exemplary post-stage circuit is shown; Figure 3 A schematic diagram of an exemplary surge suppression trigger circuit is shown; Figure 4 A schematic diagram of a second surge voltage suppression control circuit is shown; Figure 5 A schematic diagram of a third surge voltage suppression control circuit is shown.

[0029] Embodiment one

[0030] As shown in Figure 1 , a first surge voltage suppression control circuit is provided, including a power supply circuit 10, a switching circuit 20, a multi-stage surge suppression circuit 30 and a post-stage circuit 40 connected in sequence, wherein the multi-stage surge suppression circuit includes a first stage suppression circuit 31 and a second stage suppression circuit 32 connected in series. The first stage suppression circuit 31 and the second stage suppression circuit 32 each include a MOS tube 311, a surge suppression trigger circuit 312 and a sampling circuit 313.

[0031] With reference to Figure 1 , for the first stage suppression circuit 31, the source of the MOS tube 311 is connected to an output end of the sampling circuit 313, the first end 1 of the surge suppression trigger circuit 312 and the drain of the MOS tube 311 are connected together with the positive voltage end of the power supply circuit, the second end 2, the third end 3 and the fourth end 4 are respectively connected to another output end of the sampling circuit 313, the gate of the MOS tube 311 and the input end of the sampling circuit 313.

[0032] For the second stage suppression circuit 32, the source of the MOS tube 311 is connected to an output end of the sampling circuit 313, the first end 1 of the surge suppression trigger circuit 312 and the drain of the MOS tube 311 are connected together with the corresponding output end of the first stage suppression circuit 31, the second end 2, the third end 3 and the fourth end 4 are respectively connected to the corresponding another output end of the first stage suppression circuit 31, the gate of the MOS tube 311 and the input end of the sampling circuit 313.

[0033] In some embodiments, the MOS tube 311 is configured to be sequentially turned on according to a set trigger timing. For example, the MOS tube 311 in the first stage suppression circuit 31 is first turned on, and then the MOS tube 311 in the second stage suppression circuit 32 is turned on. It should be understood that the specific trigger timing can be set according to actual needs, and the present application is not limited in this regard.

[0034] When the first surge voltage suppression control circuit starts to work, if the switch circuit 20 inputs normal voltage to the first stage suppression circuit 31, no clamping is performed in the first stage suppression circuit 31 and the second stage suppression circuit 32, and only the turn-on loss of the two MOS tubes 311 in the circuit. If the switch circuit 20 inputs a surge voltage to the first stage suppression circuit 31, the first stage suppression circuit 31 and the second stage suppression circuit 32 adjust the voltage between the two output terminals of the corresponding sampling circuit 313 to the clamping voltage through the surge suppression trigger circuit 312, that is, adjust the output voltage of the first stage suppression circuit 31 and the second stage suppression circuit 32 to the clamping voltage.

[0035] For example, it is assumed that the voltage at the output terminal of the power supply circuit 10 is configured to be 80V / 50ms, and the clamping voltage of the second stage suppression circuit 32 is configured to be 38V. Since the first stage suppression circuit 31 and the second stage suppression circuit 32 are connected in series, the bearing voltage of each of the two MOS tubes 311 in the first stage suppression circuit 31 and the second stage suppression circuit 32 is 21V. Compared with the prior art, the embodiment can reduce the dissipation power of each MOS tube 311 to reduce the risk of failure under the same voltage configuration, or can suppress a larger surge voltage and improve the reliability of the circuit under the same MOS tube configuration.

[0036] Reference Figure 2 The latter stage circuit 40 includes a first inductor L1, a second inductor L2, a switching element K, a latter stage resistor R, and a latter stage capacitor C. The switching element K is connected between the first inductor L1 and the latter stage resistor R, the second inductor L2 is connected in parallel with the latter stage resistor R, the positive electrode of the latter stage capacitor C is connected to the first inductor L1, and the negative electrode of the latter stage capacitor C is connected to the latter stage resistor R away from one end of the switching element K.

[0037] Reference Figure 3 The surge suppression trigger circuit 312 includes a master control chip U1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first sub-circuit 3121, and a second sub-circuit 3122.

[0038] As shown in Figure 3 , the first end of the master control chip U1 is the VSS end, the second end is the TIMER end, the third end is the SD end, the fourth end is the VDD end, the fifth end is the GATE end, the sixth end is the OUT end, the seventh end is the FB end, and the eighth end is the BASE end.

[0039] The first capacitor C1 is connected between the first end and the second end of the master chip U1, the second capacitor C2 is connected between the first resistor R1 and the third end of the master chip U1, the first resistor R1 is connected between the fourth end of the master chip U1 and the first sub-circuit 3121, the first sub-circuit 3121 is connected between the fifth end and the sixth end of the master chip U1, the second sub-circuit 3122 is connected between the seventh end and the eighth end of the master chip U1, the ninth end of the master chip U1 is grounded, one end of the second resistor R2 is connected with the first end and the eighth end of the master chip U1, and the other end of the second resistor R2 is grounded.

[0040] The first sub-circuit 3121 comprises a first transistor Q1, a third resistor R3, a fourth resistor R4, a fourth capacitor C4 and a first diode D1; the first end, the second end and the third end of the first transistor Q1 are connected with the third resistor R3, the first resistor R1 and the sixth end of the master chip U1 respectively, the fifth end of the master chip U1 is connected with the third resistor R3 and the fourth resistor R4, the first diode D1 is connected with the fourth resistor R4 in parallel, the fourth capacitor C4 is connected with the fourth resistor R4 in series, and one end of the fourth capacitor C4 is grounded.

[0041] The second sub-circuit 3122 comprises a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a second diode D2; the fifth resistor R5 is connected between the seventh end of the master chip U1 and the fifth capacitor C5, one end of the fifth capacitor C5 is grounded, one end of the seventh resistor R7 is connected with the fifth resistor R5, the other end of the seventh resistor R7 is grounded, the sixth resistor R6 and the fourth capacitor C4 are connected in series and then connected between the seventh end of the master chip U1 and the eighth end of the master chip U1, one end of the third capacitor C3 is connected with the negative electrode of the second diode D2, the other end of the third capacitor C3 is connected with the positive electrode of the second diode D2, and the positive electrode of the second diode D2 is connected with the eighth end of the master chip U1.

[0042] In the specific implementation, other circuits available for monitoring the surge voltage can also be used as the surge suppression trigger circuit, and no limitation is made in this regard.

[0043] Embodiment two

[0044] As shown in Figure 4 , a second surge voltage suppression control circuit is provided. The second surge voltage suppression control circuit differs from the first surge voltage suppression control circuit in that it further comprises a third stage suppression circuit 33.

[0045] For the third stage suppression circuit 33, the source of the MOS transistor 311 is connected to an output of the sampling circuit 313, the first end 1 of the surge suppression trigger circuit 312 and the drain of the MOS transistor 311 are connected together with a corresponding output of the second stage suppression circuit 32, the second end 2, the third end 3 and the fourth end 4 are connected to a corresponding another output of the second stage suppression circuit 32, the gate of the MOS transistor 311 and the input of the sampling circuit 313 respectively.

[0046] When the second kind of surge voltage suppression control circuit starts to work, if the switch circuit 20 inputs normal voltage to the first stage suppression circuit 31, no clamping is performed in the first stage suppression circuit 31, the second stage suppression circuit 32 and the third stage suppression circuit 33, and only the conduction loss of the two MOS transistors 311 in the circuit is generated. If the switch circuit 20 inputs surge voltage to the first stage suppression circuit 31, the first stage suppression circuit 31, the second stage suppression circuit 32 and the third stage suppression circuit 33 adjust the voltage between the two outputs of the corresponding sampling circuit 313 to the clamping voltage through the surge suppression trigger circuit 312, that is, adjust the output voltage of the first stage suppression circuit 31, the second stage suppression circuit 32 and the third stage suppression circuit 33 to the clamping voltage.

[0047] For example, assuming that the voltage of the output end of the power supply circuit 10 is configured as 80V / 50ms, and the clamping voltage of the third stage suppression circuit 33 is configured as 38V, since the first stage suppression circuit 31, the second stage suppression circuit 32 and the third stage suppression circuit 33 are connected in series, the bearing voltage of each of the three MOS transistors 311 in the first stage suppression circuit 31, the second stage suppression circuit 32 and the third stage suppression circuit 33 is 12V. Compared with the prior art, the embodiment can reduce the dissipation power of each MOS transistor to reduce the failure risk under the same voltage configuration, or can suppress a larger surge voltage to improve the reliability of the circuit under the same MOS transistor configuration.

[0048] Embodiment Three

[0049] As shown in Figure 5 , a third kind of surge voltage suppression control circuit is provided. The third kind of surge voltage suppression control circuit is different from the first kind of surge voltage suppression control circuit in that the second stage suppression circuit 32 is replaced by N-1 suppression circuits 34 connected in series, where N is a positive integer greater than or equal to 2, and each suppression circuit 34 comprises a MOS transistor 311, a surge suppression trigger circuit 312 and a sampling circuit 313.

[0050] For each suppression circuit 34, the source of MOS transistor 311 is connected to an output of sampling circuit 313, the first end 1 of surge suppression trigger circuit 312 and the drain of MOS transistor 311 are connected together with the positive voltage end of power supply circuit, the second end 2, the third end 3 and the fourth end 4 are respectively connected to the other output of sampling circuit 313, the gate of MOS transistor 311 and the input of sampling circuit 313.

[0051] When the third surge voltage suppression control circuit starts to work, if the switch circuit 20 inputs normal voltage to the first stage suppression circuit 31, no clamping is performed in the first stage suppression circuit 31 and all the suppression circuits 34, and only the conduction loss of N MOS transistors 311 in the circuit.

[0052] For example, assuming that the voltage of the output end of power supply circuit 10 is configured as 80V / 50ms, and the clamping voltage of the last suppression circuit 34 is configured as 38V, since the first stage suppression circuit 31 and N-1 suppression circuits 34 are connected in series, the bearing voltage of each of the corresponding N MOS transistors 311 is Compared with the prior art, the embodiment can reduce the dissipation power of each MOS transistor to reduce the risk of failure under the same voltage configuration, or can suppress a larger surge voltage to improve the reliability of the circuit under the same MOS transistor configuration.

[0053] In some embodiments, the clamping voltage of each stage suppression circuit 34 can be inversely proportional to the corresponding circuit depth. For example, the clamping voltage of the first stage suppression circuit is set to 58V, the clamping voltage of the second stage suppression circuit 32 is set to 36V, and so on. It should be understood that the clamping voltage of each stage suppression circuit can be specifically set according to actual needs, and is not limited.

[0054] Embodiment four

[0055] The utility model further provides a kind of electrical equipment, comprising: the surge voltage suppression control circuit of any one of embodiment one, embodiment two and embodiment three.

[0056] The above has been described for basic concept, apparently, the utility model disclosed above is merely as example for those skilled in the art, and does not constitute the limitation of the present application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are suggested in the present application, so such modifications, improvements, corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0057] Also, the use of "a" or "an" or "the" are intended to include "one or more" and any singular form "a" or "an" or "the" is intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood by those within the art that, in general, terms used herein, and especially

[0058] Some embodiments use numerical descriptors to describe components, quantities of attributes. It should be understood that such numerical descriptors used in the description of embodiments are, in some examples, modified by the words "about," "approximately," or "generally." Unless otherwise stated, "about," "approximately," or "generally" indicates that a value is within ±20% of the stated number. Accordingly, numerical values used in the specification and claims of some embodiments are approximations which can vary depending upon the desired properties sought to be obtained by the individual embodiment. In some embodiments, numerical values are approximations that allow a level of error for the measurements that are expected in the manufacturing or processing of the respective components, or by variations in manufacturing or processing. In some embodiments, numerical values are approximations that are the best, within a manufacturing or processing context, to represent the quality of the numerical value, e.g., accounting for an expected deviation in measurements, or accounting for measurement error in manufacturing or processing. Although the numerical ranges and parameters setting forth the broadest scope of some embodiments of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, can contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0059] While the application has been described with reference to the currently preferred embodiments, those skilled in the art will recognize that changes can be made within the spirit of the application, and it is intended to include all such changes as fall within the scope of the appended claims.

Claims

1. A surge voltage suppression control circuit, comprising a power supply circuit, a switching circuit, a multi-stage surge suppression circuit, and a subsequent stage circuit connected in sequence, characterized in that, The multi-stage surge suppression circuit comprises a first-stage suppression circuit to an Nth-stage suppression circuit in series, N being a positive integer greater than or equal to 2, each stage of the suppression circuit comprising a MOS tube, a surge suppression trigger circuit and a sampling circuit, wherein for the first-stage suppression circuit, a source of the MOS tube is connected to an output of the sampling circuit, a first end of the surge suppression trigger circuit and a drain of the MOS tube are connected together with a positive voltage end of the power supply circuit, a second end, a third end and a fourth end are respectively connected to another output of the sampling circuit, a gate of the MOS tube and an input of the sampling circuit.

2. The surge voltage suppression control circuit of claim 1, wherein, for the second-stage suppression circuit to the Nth-stage suppression circuit, a source of the MOS tube is connected to an output of the sampling circuit, a first end of the surge suppression trigger circuit and a drain of the MOS tube are connected together with a corresponding output of the suppression circuit of the previous stage, a second end, a third end and a fourth end are respectively connected to a corresponding another output of the suppression circuit of the previous stage, a gate of the MOS tube and an input of the sampling circuit.

3. The surge voltage suppression control circuit of claim 2, wherein, A voltage of an output end of the power supply circuit is configured as 80V / 50ms.

4. The surge voltage suppression control circuit of claim 3, wherein, A clamping voltage of each stage of the suppression circuit is inversely proportional to a corresponding circuit depth thereof.

5. Surge voltage suppression control circuit according to any of claims 1-4, characterized in that, The MOS tube is configured to be sequentially turned on according to a set trigger timing.

6. A surge voltage suppression control circuit as claimed in any one of claims 1-4, characterized in that, The post-stage circuit comprises a first inductor, a second inductor, a switching element, a post-stage resistor and a post-stage capacitor. The switching element is connected between the first inductor and the post-stage resistor, the second inductor is connected in parallel to the post-stage resistor, a positive pole of the post-stage capacitor is connected to the first inductor, and a negative pole of the post-stage capacitor is connected to the post-stage resistor away from one end of the switching element.

7. The surge voltage suppression control circuit of any one of claims 1-4, wherein, The surge suppression trigger circuit comprises a master control chip, a first resistor, a second resistor, a first capacitor, a second capacitor, a first sub-circuit and a second sub-circuit. The first capacitor is connected between a first end and a second end of the master control chip, the second capacitor is connected between the first resistor and a third end of the master control chip, the first resistor is connected between a fourth end of the master control chip and the first sub-circuit, the first sub-circuit is connected between a fifth end and a sixth end of the master control chip, the second sub-circuit is connected between a seventh end and an eighth end of the master control chip, a ninth end of the master control chip is grounded, one end of the second resistor is connected together with the first end and the eighth end of the master control chip, and the other end of the second resistor is grounded.

8. The surge voltage suppression control circuit of claim 7, wherein, The first sub-circuit comprises a first transistor, a third resistor, a fourth resistor, a fourth capacitor and a first diode. A first end, a second end and a third end of the first transistor are respectively connected to the third resistor, the first resistor and the sixth end of the master control chip, the fifth end of the master control chip is connected to the third resistor and the fourth resistor, the first diode is connected in parallel to the fourth resistor, the fourth capacitor is connected in series to the fourth resistor, and one end of the fourth capacitor is grounded.

9. The surge voltage suppression control circuit of claim 8, wherein, The second sub-circuit comprises a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor and a second diode. The fifth resistor is connected between the seventh terminal of the master control chip and the fifth capacitor, one end of the fifth capacitor is grounded, one end of the seventh resistor is connected to the fifth resistor, the other end of the seventh resistor is grounded, the sixth resistor and the fourth capacitor are connected in series and then connected between the seventh terminal of the master control chip and the eighth terminal of the master control chip, one end of the third capacitor is connected to the negative electrode of the second diode, the other end of the third capacitor is connected to the positive electrode of the second diode, and the positive electrode of the second diode is connected to the eighth terminal of the master control chip.

10. An electrical appliance characterized by Comprising: The surge voltage suppression control circuit of any one of claims 1 to 9.

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