Power amplification circuit
By designing a complementary circuit composed of NPN and PNP transistors and a bias adjustment circuit, the problem of power amplifier performance degradation at high temperatures was solved, the circuit was able to operate stably at high temperatures, the current remained constant, and the circuit performance was improved.
Patent Information
- Application Number
- CN202520074253.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-01-13
AI Technical Summary
Power amplifiers degrade in performance at high temperatures. The PN junction voltage of transistors decreases, leading to increased operating current, decreased circuit gain, and performance degradation.
A power amplifier circuit was designed, including an input stage, an amplification stage, and an output stage. A complementary circuit composed of NPN and PNP transistors was used, and temperature compensation was achieved through a bias adjustment circuit to ensure that the operating current of the output stage circuit remained constant.
Maintaining stable circuit performance at high temperatures and preventing a significant increase in operating current improves the reliability and stability of the circuit.
Smart Images
Figure CN223744685U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power amplification, and particularly relates to a power amplification circuit. BACKGROUND
[0002] A power amplifier is a commonly used electronic amplifier and an important device in a radio frequency module product. The main purpose of the power amplifier is to increase the power amplitude of a given input signal, so that the power of the input signal is increased, thereby driving the load level of the subsequent device. The performance of the power amplifier at high temperature will be deteriorated to a certain extent compared with the performance at normal temperature. The PN junction voltage of a triode in the power amplifier will decrease with the increase of temperature, and the corresponding working current will become larger, resulting in the decrease of circuit gain and the degradation of circuit performance. The present application provides a power amplification circuit, which is suitable for providing temperature compensation for the power amplifier, avoiding the substantial increase of working current of the power amplifier at high temperature, and improving the circuit performance. SUMMARY
[0003] Therefore, the present application provides a power amplification circuit.
[0004] According to an aspect of the present application, a power amplification circuit is provided, which comprises an input stage circuit, an amplification stage circuit and an output stage circuit.
[0005] The input stage circuit comprises a first triode Q1 and a second triode Q2. The base of the first triode Q1 is adapted to input a square wave signal, and the base of the second triode Q2 is electrically connected to a feedback loop to input an output voltage feedback signal. The emitter of the first triode Q1 is electrically connected to the emitter of the second triode Q2 and connected to the negative electrode of a power supply through a resistor R3.
[0006] The amplification stage circuit comprises a third triode Q3 and a fourth triode Q4. The collector of the first triode Q1 is electrically connected to the base of the third triode Q3, and the collector of the third triode Q3 is electrically connected to the collector of the fourth triode Q4. The emitter of the third triode Q3 is connected to a +15V voltage.
[0007] The output stage circuit comprises a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8; the collector of the third transistor Q3 is electrically connected with the base of the fifth transistor Q5; the emitter of the fifth transistor Q5 is electrically connected with the base of the eighth transistor Q8, and the emitter of the fifth transistor Q5 is electrically connected with the emitter of the sixth transistor Q6 through the resistor R8; the collector of the fifth transistor Q5 and the collector of the eighth transistor Q8 are connected with +15V voltage; the emitter of the eighth transistor Q8 outputs voltage through the resistor R10; the emitter of the fourth transistor Q4 is electrically connected with the base of the sixth transistor Q6; the emitter of the sixth transistor Q6 is electrically connected with the base of the seventh transistor Q7, and the collector of the sixth transistor Q6 and the collector of the seventh transistor Q7 are connected with -15V voltage; the emitter of the seventh transistor Q7 outputs voltage through the resistor R11;
[0008] The amplification stage circuit further comprises a variable resistor VR1, a resistor R6 and a capacitor C8; the collector of the third transistor Q3 is electrically connected with one end of the variable resistor VR1 and the collector of the fourth transistor Q4; the other end of the variable resistor VR1 is connected with the resistor R6 in series; the base of the fourth transistor Q4 is electrically connected on the circuit between the variable resistor VR1 and the resistor R6; one end of the capacitor C8 is electrically connected with the collector of the fourth transistor Q4, and the other end of the capacitor C8 is electrically connected with the emitter of the fourth transistor Q4;
[0009] The first transistor Q1, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5 and the eighth transistor Q8 are all NPN type transistors, and the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7 are all PNP type transistors.
[0010] In a possible implementation, the input stage circuit further comprises a capacitor C1.
[0011] The capacitor C1 is connected in series on the circuit of the base of the first transistor Q1 inputting the square wave signal.
[0012] In a possible implementation, the input stage circuit further comprises a resistor R1.
[0013] One end of the resistor R1 is electrically connected with the base of the first transistor Q1, and the other end of the resistor R1 is grounded.
[0014] In a possible implementation, the amplification stage circuit further comprises a capacitor C7.
[0015] One pole of the capacitor C7 is electrically connected with the base of the third transistor Q3, and the other pole of the capacitor C7 is electrically connected with the collector of the third transistor Q3.
[0016] In a possible implementation, the feedback loop comprises the resistor R4, the resistor R9 and the capacitor C6; one end of the resistor R4 is electrically connected to the base of the second transistor Q2, and the other end of the resistor R4 is grounded through the capacitor C6; one end of the resistor R9 is electrically connected to the base of the second transistor Q2, and the other end of the resistor R9 is electrically connected to the emitter of the eighth transistor Q8 and the emitter of the seventh transistor Q7.
[0017] In a possible implementation, the feedback loop further comprises the capacitor C9.
[0018] The capacitor C9 is connected in parallel with the resistor R9.
[0019] In a possible implementation, the output stage circuit further comprises the capacitor C10 and the resistor R12.
[0020] One pole of the capacitor C10 is electrically connected to the output end of the resistor R10 and the output end of the resistor R11, and the other pole of the capacitor C10 is electrically connected to one end of the resistor R12; the other end of the resistor R12 is grounded.
[0021] Beneficial effects: the input stage circuit is suitable for performing first voltage amplification on a square wave signal; the amplification stage circuit is suitable for performing second voltage amplification on a voltage signal; the output stage circuit is suitable for performing twice current amplification on a voltage signal and outputting; the bias adjustment circuit is composed of the fourth transistor Q4, the variable resistor VR1, the resistor R6 and the capacitor C8; the fourth transistor Q4 can generate a stable bias voltage to provide a bias current for the output stage circuit, so as to ensure that the output stage circuit works in a linear region and the distortion of an output signal is minimum. At the same time, the voltage V Q4 of the bias adjustment circuit composed of the fourth transistor Q4, the variable resistor VR1 and the resistor R6 will decrease with the increase of temperature; and the working current of the output stage circuit will increase with the increase of temperature; at this time, the decrease of the voltage V Q4 of the bias adjustment circuit can offset the increase of the current of the output stage circuit, so as to make the current of the entire output stage circuit tend to be constant; thereby, a temperature compensation process is realized, and the working current of the power amplification circuit does not appear to be greatly increased at high temperature, so as to improve the performance of the circuit, and the present application can stably work at normal temperature and high temperature.
[0022] Other features and aspects of the present application will become apparent from the following detailed description of the example embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0023] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate example embodiments, features, and aspects of the present application and serve to explain the principles of the present application.
[0024] Figure 1 FIG. 1 shows a circuit diagram of a power amplification circuit according to an embodiment of the present application;
[0025] Figure 2 Fig. 1 shows a structural diagram of a power amplification circuit according to an embodiment of the present application;
[0026] Figure 3 Fig. 4 shows a circuit diagram of a well logging signal transmission circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0027] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings represent the same or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
[0028] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like indicate the orientation or positional relationship shown in the drawings, and are used only for the convenience of describing the present application or simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.
[0029] In addition, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0030] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.
[0031] In addition, in order to better illustrate the present application, numerous specific details are given in the specific embodiments below. Those skilled in the art should understand that the present application can also be implemented without some specific details. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail in order to highlight the main idea of the present application.
[0032] Figure 1 Fig. 1 shows a structural diagram of a power amplification circuit according to an embodiment of the present application; Figure 1As shown, a power amplifier circuit includes: an input stage circuit, an amplifier stage circuit and an output stage circuit; the input stage circuit includes: a first transistor Q1, a second transistor Q2; the base of the first transistor Q1 is adapted to input a square wave signal, the base of the second transistor Q2 is electrically connected to a feedback loop to input an output voltage feedback signal; the emitter of the first transistor Q1 is electrically connected to the emitter of the second transistor Q2 and is connected to the negative electrode of the power supply through a resistor R3; the amplifier stage circuit includes: a third transistor Q3 and a fourth transistor Q4; the collector of the first transistor Q1 is electrically connected to the base of the third transistor Q3, and the collector of the third transistor Q3 is electrically connected to the collector of the fourth transistor Q4; the emitter of the third transistor Q3 is connected to a +15V voltage; the output stage circuit includes: a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8; the collector of the third transistor Q3 is electrically connected to the base of the fifth transistor Q5; the emitter of the fifth transistor Q5 is electrically connected to the base of the eighth transistor Q8, and the emitter of the fifth transistor Q5 is electrically connected to the emitter of the sixth transistor Q6 through a resistor R8; the collector of the fifth transistor Q5 and the collector of the eighth transistor Q8 are both connected to a +15V voltage; the emitter of the eighth transistor Q8 outputs a voltage through a resistor R10; the emitter of the fourth transistor Q4 is electrically connected to the base of the sixth transistor Q6; the emitter of the sixth transistor Q6 is electrically connected to the base of the seventh transistor Q7, and the collector of the sixth transistor Q6 and the collector of the seventh transistor Q7 are both connected to a -15V voltage; the emitter of the seventh transistor Q7 outputs a voltage through a resistor R11; the amplifier stage circuit further includes: a variable resistor VR1, a resistor R6 and a capacitor C8; the collector of the third transistor Q3 is electrically connected to one end of the variable resistor VR1; the other end of the variable resistor VR1 is connected in series with the resistor R6; the base of the fourth transistor Q4 is electrically connected to the circuit between the variable resistor VR1 and the resistor R6; one end of the capacitor C8 is electrically connected to the collector of the fourth transistor Q4, and the other end of the capacitor C8 is electrically connected to the emitter of the fourth transistor Q4; the first transistor Q1, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5 and the eighth transistor Q8 are all NPN type transistors, and the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7 are all PNP type transistors.
[0033] Here, it needs to be explained that the input stage circuit is suitable for the first amplification of the voltage of the square wave signal. The input stage circuit is composed of the first transistor Q1 and the second transistor Q2. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected through the resistor R3 to the negative pole of the power supply, and share a resistor R3 (20K) to V-15V; the collector of the first transistor Q1 is connected to the resistor R2 (3K) to V+15V; the collector of the second transistor Q2 is connected to V+15V to form a differential amplification circuit. The input square wave signal is sent to the base of the first transistor Q1, and the output voltage feedback signal is sent to the base of the second transistor Q2; the amplified voltage is sent to the base of the third transistor Q3 through the resistor R2 for the second voltage amplification.
[0034] The amplification stage circuit includes the third transistor Q3 and the fourth transistor Q4. The amplified signal of the input stage circuit is sent to the base of the third transistor Q3, and after the inverted amplification output of the third transistor Q3, it is sent to the output stage circuit. This stage circuit only performs the second voltage amplification, and the current amplification is performed by the subsequent output stage circuit. The signal v o with an amplitude of about 10V and a current i o of 1-2mA.
[0035] The output stage circuit is composed of the fifth transistor Q5 and the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8. The amplified signal of the third transistor Q3 is sent to the base of the fifth transistor Q5 and the sixth transistor Q6 for the first current amplification, in which the fifth transistor Q5 is responsible for the current amplification of the positive half cycle, and the sixth transistor Q6 is responsible for the current amplification of the negative half cycle. The fifth transistor Q5 and the sixth transistor Q6 perform the first current amplification on the voltage signal, and the output voltage v o with an amplitude of about 10V and a current i o of 100mA.
[0036] The amplified current of the fifth transistor Q5 and the sixth transistor Q6 serves as the driving current to push the seventh transistor Q7 and the eighth transistor Q8 to further amplify and output to the transformer B103. The seventh transistor Q7 and the sixth transistor Q6 perform the second current amplification on the output voltage signal, and the eighth transistor Q8 performs the second current amplification on the voltage signal output by the fifth transistor Q5. The output voltage v o with an amplitude of about 10V and a maximum output current i o of 2A; the entire circuit realizes the power amplification of the square wave signal through two voltage amplifications and two current amplifications on the electrical signal.
[0037] In summary, the application is designed as an OTL power amplifier circuit, and the output stage circuit is composed of an NPN transistor and a PNP transistor to form a complementary circuit, wherein the NPN transistor is responsible for the positive half cycle output, and the PNP transistor is responsible for the negative half cycle output. The output stage circuit is composed of two Darlington amplifiers in series, and the voltage signal of the amplifier circuit is amplified twice in turn and output to the load behind.
[0038] Further, the input stage circuit is described as follows: the first transistor Q1 and the second transistor Q2 have similar performances and jointly form a differential amplifier; the base of the first transistor Q1 is adapted to input a square wave signal, and the base of the second transistor Q2 is electrically connected with a feedback loop and is adapted to return the output electrical signal to the base of the second transistor Q2; (the two signals can be any waveform, and the differential amplifier outputs the difference between the two signals); the emitter of the first transistor Q1 is electrically connected with the emitter of the second transistor Q2 and returns to the negative pole of the power supply through the resistor R3; in this way, the second transistor Q2 raises the emitter potential of the first transistor Q1, and the electrical signal input at the base of the first transistor Q1 is offset, so that the amplification factor is reduced. At the same time, due to the symmetry of the differential amplifier, it has a strong inhibitory effect on the common-mode signal; in an ideal case, the common-mode output is zero, that is, the common-mode signal will not be amplified, which makes the input stage circuit have a significant advantage in suppressing power supply noise, ground loop interference, etc., has good electrical symmetry, and can effectively suppress the occurrence of zero drift phenomenon.
[0039] Further, the input stage circuit further comprises a feedback loop; the feedback loop comprises a resistor R4, a resistor R9 and a capacitor C6; one end of the resistor R4 is electrically connected with the base of the second transistor Q2, and the other end of the resistor R4 is grounded through the capacitor C6; one end of the resistor R9 is electrically connected with the base of the second transistor Q2, and the other end of the resistor R9 is electrically connected with the emitter of the eighth transistor Q8 and the emitter of the seventh transistor Q7.
[0040] In a possible implementation, the feedback loop further comprises a capacitor C9; the capacitor C9 is connected in parallel with the resistor R9, and the capacitor C9 is used to suppress high-frequency signals.
[0041] DC voltage feedback: the voltage drift of the output stage circuit is controlled by DC voltage negative feedback, and the change of the DC voltage is fed back by the resistor R9. When the DC voltage of the output stage circuit deviates from 0V, the voltage transformation at the output end is sent to the base of the second transistor Q2 through the resistor R9. By comparing with 0V, the output reverse differential signal is amplified and then makes the output voltage reverse adjustment to minimize the deviation.
[0042] AC voltage feedback: resistance R9, resistance R4 form a voltage divider, the output AC voltage is attenuated by 5 times and sent to the base of the second transistor Q2 and the input signal of the base of the first transistor Q1 are compared, and the deviation signal is amplified and output, thereby reducing distortion and suppressing noise.
[0043] In a possible implementation, the input stage circuit further comprises: a capacitor C1; the capacitor C1 is connected in series with the base of the first transistor Q1 to access the square wave signal. The capacitor C1 is suitable for filtering the accessed electrical signal.
[0044] In a possible implementation, the input stage circuit further comprises: a resistor R1; one end of the resistor R1 is electrically connected to the base of the first transistor Q1, and the other end of the resistor R1 is grounded.
[0045] In a possible implementation, the input stage circuit further comprises: a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5; one end of the capacitor C2 is electrically connected to the positive electrode of the power supply, and the other end of the capacitor C2 is grounded; one end of the capacitor C3 is electrically connected to the positive electrode of the power supply, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is electrically connected to the negative electrode of the power supply, and the other end of the capacitor C4 is grounded; one end of the capacitor C5 is electrically connected to the negative electrode of the power supply, and the other end of the capacitor C5 is grounded. The capacitor C2, the capacitor C3, the capacitor C4, and the capacitor C5 are filter capacitors of the power supply loop. When the power amplifier outputs the power supply signal, the signal current is provided by the power supply loop, and the capacitor C2, the capacitor C3, the capacitor C4, and the capacitor C5 can provide instantaneous current to reduce the DC voltage fluctuation of the power supply.
[0046] The amplification stage circuit is described as follows: the collector of the first transistor Q1 is electrically connected to the base of the third transistor Q3, the emitter of the third transistor Q3 is electrically connected to the positive electrode of the power supply through the resistor R5 to access the +15V voltage, the collector of the third transistor Q3 is electrically connected to one end of the variable resistor VR1, and the collector of the third transistor Q3 is electrically connected to the collector of the fourth transistor Q4; at the same time, the collector of the third transistor Q3 is electrically connected to the base of the fifth transistor Q5, and the third transistor Q3 is suitable for performing second voltage amplification on the electrical signal sent by the first transistor Q1 and then outputting the electrical signal to the output stage circuit.
[0047] In a possible implementation, the amplification stage circuit further comprises: a capacitor C7; one pole of the capacitor C7 is electrically connected to the base of the third transistor Q3, and the other pole of the capacitor C7 is electrically connected to the collector of the third transistor Q3. It should be noted that the capacitor C7 plays a role of high-frequency negative feedback to avoid high-frequency self-oscillation of the power amplifier.
[0048] The amplification stage circuit further comprises a bias adjustment circuit of the output stage: the bias adjustment circuit comprises a variable resistor VR1, a resistor R6 and a capacitor C8; one end of the variable resistor VR1 is electrically connected to the collector of a third transistor Q3, the other end of the variable resistor VR1 is electrically connected to one end of the resistor R6, the base of a fourth transistor Q4 is electrically connected to the circuit between the variable resistor VR1 and the resistor R6, and the RW end of the variable resistor VR1 is electrically connected to the base of the fourth transistor Q4; one end of the resistor R6 is electrically connected to the variable resistor VR1, the other end of the resistor R6 is electrically connected to one end of a resistor R7, and the other end of the resistor R7 is electrically connected to the negative electrode of the power supply. One end of the capacitor C8 is electrically connected to the collector of the fourth transistor Q4, and the other end of the capacitor C8 is electrically connected to the emitter of the fourth transistor Q4.
[0049] The working principle of the bias adjustment circuit is as follows: the variable resistor VR1 and the resistor R6 form a voltage dividing circuit, which cooperates with the fourth transistor Q4 to become a voltage stabilizing circuit; adjusting the resistance of the variable resistor VR1 can change the stabilized voltage, and the variable resistor VR1 can change between 0.7-4V (the output stage bias voltage is 0.7*4≈2.8V). The voltage (V be is the base-emitter on voltage of the fourth transistor Q4, and the base-emitter on voltage of the fourth transistor Q4 is 0.7V by default). For example: if VR1=700Ω; The capacitor C8 is short-circuited to alternating current, which can reduce the alternating current distortion introduced by the fourth transistor Q4 bias adjustment circuit, and ensure that the output stage circuit works in the linear region, and the distortion of the output signal is minimized. At the same time, the change of the voltage V Q4 of the fourth transistor Q4 will cause the change of the static working current of the output stage circuit, and the static working current I i of the output stage is adjusted by adjusting the resistance of the variable resistor VR1 during debugging.
[0050] In addition, when the ambient temperature rises, the on voltage of the transistor will decrease, which will produce a temperature drift current. At the same time, the voltage V Q4 of the fourth transistor Q4 will also decrease with the increase of temperature; the decrease of the voltage of the fourth transistor Q4 will cause the decrease of the static working current of the output stage circuit; the following change process will occur: temperature rises↑→the current I i of the output stage circuit (Q5, Q6, Q7, Q8) rises↑→the voltage V Q4 of the fourth transistor Q4 decreases↓→the current I i of the output stage circuit (Q5, Q6, Q7, Q8) decreases↓→the current I i of the output stage circuit (Q5, Q6, Q7, Q8) tends to be constant; that is, the voltage V Q4The decrease of the output stage circuit can offset the static current rise of the output stage circuit caused by the temperature rise, so that the current of the output stage circuit tends to be constant; thereby realizing the temperature compensation process, so that the application can work stably at normal temperature and high temperature, and the application is suitable for power amplification with a frequency below 200K, and has the advantages of simple circuit structure, adaptability to high temperature environment, small size, large output power and stable work.
[0051] The output stage circuit is described as follows: the base of the sixth transistor Q6 is electrically connected with the emitter of the fourth transistor Q4 to input an electrical signal, the collector of the sixth transistor Q6 is electrically connected with the negative pole of the power supply to input a voltage of -15V, the emitter of the sixth transistor Q6 is electrically connected with the base of the seventh transistor Q7 to output an amplified electrical signal to the seventh transistor Q7, the collector of the seventh transistor Q7 is electrically connected with the negative pole of the power supply to input a voltage of -15V, and the emitter of the seventh transistor Q7 is electrically connected with the resistor R11 to output a second amplified electrical signal; it should be noted that since the sixth transistor Q6 and the seventh transistor Q7 are both PNP type transistors, the sixth transistor Q6 can amplify the current in the negative half cycle of the square wave signal for the first time, and the seventh transistor Q7 can amplify the current in the negative half cycle of the square wave signal for the second time, and finally the emitter of the seventh transistor Q7 outputs a voltage through the resistor R11.
[0052] The base of the fifth transistor Q5 is electrically connected with the collector of the third transistor Q3, the collector of the fifth transistor Q5 is electrically connected with the positive pole of the power supply to input a voltage of +15V, the emitter of the fifth transistor Q5 is electrically connected with the base of the eighth transistor Q8 to output a first amplified electrical signal to the eighth transistor Q8, the collector of the eighth transistor Q8 is electrically connected with the positive pole of the power supply to input a voltage of +15V, and the emitter of the eighth transistor Q8 is electrically connected with the resistor R10 to output a second amplified electrical signal; it should be noted that since the fifth transistor Q5 and the eighth transistor Q8 are both NPN type transistors, the fifth transistor Q5 can amplify the current in the positive half cycle of the square wave signal for the first time, and the eighth transistor Q8 can amplify the current in the positive half cycle of the square wave signal for the second time, and finally the emitter of the eighth transistor Q8 outputs a voltage through the resistor R10.
[0053] Further, the current amplification factor is as follows:
[0054] Positive half cycle β+ = β Q5 *β Q8 ; negative half cycle β- = β Q6 *β Q7 .
[0055] In order to avoid crossover distortion, an initial bias current I iAdjusting the variable resistor VR1 can adjust the output stage bias current. The bias voltage is distributed as follows:
[0056] V Q5b -V Q6b = 2.8V
[0057] V Q5e -V Q6e = 1.4V
[0058] V Q8b -V Q7b = 1.4V
[0059] V Q8e -V Q7e = 0V
[0060] In a possible implementation, the output stage circuit further comprises: a capacitor C10 and a resistor R12; one pole of the capacitor C10 is electrically connected with an output end of the resistor R11 and an output end of the resistor R10, and the other pole of the capacitor C10 is electrically connected with one end of the resistor R12; the other end of the resistor R12 is grounded. It should be noted that the capacitor C10 and the resistor R12 together constitute a high-frequency absorption circuit, which can absorb high-frequency signals when the circuit generates high-frequency oscillation, thereby inhibiting the generation of high-frequency signals.
[0061] In a possible implementation, the output stage circuit further comprises: a transformer B103; the output end of the resistor R11 and the output end of the resistor R10 are electrically connected with a primary winding of the transformer B103 to output the amplified electrical signal to the transformer B103, and the capacitor C11 and the capacitor C12 are connected in series on a circuit of the emitter of the eighth transistor Q8 and the emitter of the seventh transistor Q7 connected with the transformer B103. It should be noted that the voltage and current output by the output stage circuit are reduced by the capacitor C11, the capacitor C12 and the transformer B103, and then driving voltage and current are provided for the subsequent circuit.
[0062] Further, the first transistor Q1 is of the model BC846A; the second transistor Q2 is of the model BC846A; the third transistor Q3 is of the model BC856A; the fourth transistor Q4 is of the model BC846A; the fifth transistor Q5 is of the model 2SC2383; the sixth transistor Q6 is of the model 2SA1013; the seventh transistor Q7 is of the model 2SA1469S; and the eighth transistor is of the model 2SC3746S.
[0063] In the technical field of dual-induction eight-lateral logging instruments, the logging signal can be power-amplified and output to provide a test electrical signal for the main electrode (1# electrode) or the barrier electrode (4# electrode) of the eight lateral. The actual application of the present application is shown in Figure 3 , in Figure 3The present application is responsible for the final output; analog switch U 401b , analog switch U 401C The output signal after chopping the logging signal is sent to the power amplifier circuit through the capacitor C425 for amplification and output to the AP electrode for power supply. The logging signal is switched by the analog switch to form a weak signal (0.6V), which is output by the power amplifier circuit of the present application about 2-3V, and then sent to the barrier electrode after being stepped down by the transformer B103 (25:1).
[0064] The above has described various embodiments of the present application, the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical applications, or improvements to the technology in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.
Claims
1. A power amplification circuit, characterized by, The application relates to a circuit for generating a square wave signal, which comprises an input stage circuit, an amplification stage circuit and an output stage circuit. The input stage circuit comprises a first transistor Q1 and a second transistor Q2; the base of the first transistor Q1 is adapted to input a square wave signal, and the base of the second transistor Q2 is electrically connected to a feedback loop to input an output voltage feedback signal; the emitter of the first transistor Q1 is electrically connected to the emitter of the second transistor Q2 and connected to the negative pole of a power supply through a resistor R3. The amplification stage circuit comprises a third transistor Q3 and a fourth transistor Q4; the collector of the first transistor Q1 is electrically connected to the base of the third transistor Q3, the collector of the third transistor Q3 is electrically connected to the collector of the fourth transistor Q4; and the emitter of the third transistor Q3 is connected to a +15V voltage. The output stage circuit comprises a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8; the collector of the third transistor Q3 is electrically connected to the base of the fifth transistor Q5; the emitter of the fifth transistor Q5 is electrically connected to the base of the eighth transistor Q8, and the emitter of the fifth transistor Q5 is electrically connected to the emitter of the sixth transistor Q6 through a resistor R8; the collector of the fifth transistor Q5 and the collector of the eighth transistor Q8 are both connected to a +15V voltage; the emitter of the eighth transistor Q8 outputs a voltage through a resistor R10; the emitter of the fourth transistor Q4 is electrically connected to the base of the sixth transistor Q6; the emitter of the sixth transistor Q6 is electrically connected to the base of the seventh transistor Q7, and the collector of the sixth transistor Q6 and the collector of the seventh transistor Q7 are both connected to a -15V voltage; the emitter of the seventh transistor Q7 outputs a voltage through a resistor R11. The amplification stage circuit further comprises a bias adjustment circuit; the bias adjustment circuit comprises a variable resistor VR1, a resistor R6 and a capacitor C8; the collector of the third transistor Q3 is electrically connected to one end of the variable resistor VR1, and the other end of the variable resistor VR1 is connected in series with the resistor R6; the base of the fourth transistor Q4 is electrically connected to the circuit between the variable resistor VR1 and the resistor R6; one end of the capacitor C8 is electrically connected to the collector of the fourth transistor Q4, and the other end of the capacitor C8 is electrically connected to the emitter of the fourth transistor Q4. The first transistor Q1, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5 and the eighth transistor Q8 are all NPN type transistors, and the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7 are all PNP type transistors. The input stage circuit further comprises a capacitor C1.
2. A power amplification circuit according to claim 1, wherein The capacitor C1 is connected in series to the circuit in which the base of the first transistor Q1 inputs a square wave signal. The input stage circuit further comprises a resistor R1.
3. A power amplifier circuit as claimed in claim 2, characterized in that One end of the resistor R1 is electrically connected to the base of the first transistor Q1, and the other end of the resistor R1 is grounded. The amplification stage circuit further comprises a capacitor C7.
4. The power amplification circuit of claim 1, wherein One pole of the capacitor C7 is electrically connected with the base of the third triode Q3, and the other pole of the capacitor C7 is electrically connected with the collector of the third triode Q3.
5. The power amplification circuit of claim 1, wherein The feedback loop comprises the resistance R4, the resistance R9 and the capacitor C6; one end of the resistance R4 is electrically connected with the base of the second triode Q2, and the other end of the resistance R4 is grounded through the capacitor C6; one end of the resistance R9 is electrically connected with the base of the second triode Q2, and the other end of the resistance R9 is electrically connected with the emitter of the eighth triode Q8 and the emitter of the seventh triode Q7.
6. A power amplification circuit according to claim 5, wherein The feedback loop further comprises the capacitor C9. The capacitor C9 is connected in parallel with the resistance R9.
7. The power amplification circuit of claim 1, wherein The output stage circuit further comprises the capacitor C10 and the resistance R12. One pole of the capacitor C10 is electrically connected with the output end of the resistance R10 and the output end of the resistance R11, and the other pole of the capacitor C10 is electrically connected with one end of the resistance R12; the other end of the resistance R12 is grounded.