Semiconductor device

Abstract

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, the first insulation structure is a composite structure, and the gaps and / or gaps are arranged in the plurality of insulation layers contained in the first insulation structure, so that the efficiency and the reliability of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technology field especially relates to a semiconductor device. BACKGROUND

[0002] Dynamic random access memory (DRAM) belongs to a kind of volatile memory, including the array area (array area) being formed by multiple memory cells and the peripheral area (peripheral area) being formed by control circuit.It is formed by one transistor and one capacitor being electrically connected with the transistor in each memory cell, the storage or release of charge in the capacitor is controlled by the transistor, to achieve the purpose of storing data.Control circuit can be addressed to each memory cell to control the access of the data of each memory cell through word line (WL) and bit line (BL) being electrically connected with each memory cell across array area.However, due to the limitation of process technology, there are still many defects in the existing dynamic random access memory, and the performance and reliability of related memory components need to be further improved and effectively improved. SUMMARY

[0003] The utility model aims at providing a kind of semiconductor device, improve the performance and reliability of semiconductor device.

[0004] To solve the above technical problems, the utility model provides a kind of semiconductor device, at least can include: substrate;

[0005] Multiple first insulation structures are arranged on the substrate, and the first insulation structure includes first insulation layer and second insulation layer, wherein at least one first insulation structure includes first gap and second gap in the first insulation layer and the second insulation layer respectively;

[0006] Multiple first contact structures are located between adjacent first insulation structures.

[0007] Optionally, the first insulation layer and the second insulation layer of at least one first insulation structure define a gap, and the width of the gap in the horizontal direction can be greater than the width of the first gap in the first insulation layer in the horizontal direction.

[0008] Optionally, the gap contacts the first gap and / or the second gap.

[0009] Optionally, the top surface of the gap can be higher than the top surface of the first contact structure.

[0010] Optionally, the semiconductor device can further comprise:

[0011] a plurality of word line structures, disposed in the substrate and spaced apart from each other, and located in the first insulating structure, at least one of the word line structures comprises an insulating cap layer having a third gap, and the first insulating layer extends into the insulating cap layer in a vertical direction and directly contacts the insulating cap layer.

[0012] Optionally, the first insulating structure can further comprise: a third insulating layer located on both outer sidewalls of the first insulating layer.

[0013] Optionally, the third insulating layer of at least one of the first insulating structures is further located between the first insulating layer and the second insulating layer, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

[0014] Optionally, the first gap of the first insulating layer is aligned with the second gap in the second insulating layer in the same vertical direction.

[0015] Optionally, the first gap in the first insulating layer is in communication with the second gap in the second insulating layer.

[0016] Optionally, the third gap of the insulating cap layer of at least one of the word line structures is aligned with the first gap in the first insulating layer and / or the second gap in the second insulating layer in the same vertical direction.

[0017] Optionally, the second insulating layer can further extend to cover part of the sidewalls of the third insulating layer located on both outer sidewalls of the first insulating layer.

[0018] Optionally, the semiconductor device can further comprise:

[0019] a plurality of second contact structures located on the first contact structures and extending to cover part of the top surface of the first insulating structure in a horizontal direction.

[0020] Optionally, the semiconductor device can further comprise:

[0021] a plurality of second insulating structures located between adjacent second contact structures and directly contacting the first insulating structure through the second contact structures.

[0022] Optionally, at least one of the second insulating structures directly contacts the gap in the first insulating structure.

[0023] Optionally, at least one of the second insulating structures directly contacts the second gap in the second insulating layer of the first insulating structure.

[0024] In the utility model, multiple first insulation structures at least include first insulation layer and second insulation layer, wherein first insulation layer and second insulation layer of at least one first insulation structure are respectively provided with a gap, such as first gap in first insulation layer and second gap in second insulation layer, and first insulation layer and second insulation layer of at least one first insulation structure define a gap, that is, by setting first insulation structure as composite structure and containing multiple insulation layers with gap and / or gap in the multiple insulation layers, the new structure of first insulation structure and the semiconductor device containing the new structure also improve the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and serve to explain the principles of the application, but do not limit the application. In the drawings:

[0026] Figures 1-14 The structure schematic diagram of the semiconductor device provided in an embodiment of the utility model in the preparation process.

[0027] In the drawings, reference signs are:

[0028] 100-base, 110-trench isolation, 120-word line structure, 121-gate dielectric layer, 122-work function layer, 123-conductive layer, 124-insulating cap layer, 124.1-gap in insulating cap layer (third gap), 130-isolation layer, 140-sacrificial layer, 101-via, 151-first insulation layer, 102-gap in first insulation layer (first gap), 103-recess, 103'-gap defined by first insulation layer and second insulation layer, 104-gap defined by third insulation layer and first insulation layer, 152-third insulation layer, 105-gap in third insulation layer, 106-first contact recess, 160-first contact material layer, 161-first contact structure, 153-second insulation layer, 107-gap in second insulation layer (second gap), 162-silicide layer, 163-second contact structure, 171-first insulation structure, 172-second insulation structure, 180-capacitor, 181-lower electrode, 182-capacitor dielectric, 183-upper electrode, BL-bit line structure, ACT-active region.

[0029] In the drawings, the same components use the same reference signs, and the drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0030] In order to make the technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the present application will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0031] The present application will be described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the present application will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. It should be understood that the meanings of "on", "above" and "above" in the present application should be interpreted in the broadest way, so that "on" not only means "on" with no intervening characteristics or layers (i.e. directly on something), but also includes the meaning of "on" with intervening characteristics or layers.

[0032] For the convenience of understanding, the horizontal direction and the vertical direction are defined in the following, wherein the horizontal direction is the direction parallel to the surface of the substrate 100; the vertical direction is the direction perpendicular to the surface of the substrate 100.

[0033] Please refer to Figure 13 , which is a cross-sectional schematic diagram of a semiconductor device in the first embodiment of the present application. The semiconductor device of the present application can be used to manufacture dynamic random access memory (DRAM), and the present application can also be applied to other types of memory without departing from the spirit of the present application.

[0034] As Figure 13As shown, the semiconductor device includes a substrate 100, a plurality of word line structures 120, a plurality of first contact structures 161, a silicide layer 162, a plurality of second contact structures 163, a plurality of first insulating structures 171, a plurality of second insulating structures 172, and a plurality of capacitors 180. The substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate formed of other suitable materials, without limitation. The substrate 100 further includes a plurality of trench isolations 110 formed therein to define a plurality of active regions (not shown) extending in the same direction (not shown) within the substrate 100. In one embodiment, the trench isolations 110 can be elongated and arranged in a horizontal direction in sequence. The trench isolations 110 can include a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride doped with nitrogen, low-k dielectric material such as fluorosilicate glass, carbon-doped silicon oxide, spin-on silicon glass, porous low-k dielectric material, organic polymer dielectric material, or combinations thereof, without limitation. The plurality of word line structures 120 are formed within the plurality of trench isolations 110 and can be elongated in a vertical direction and arranged in a horizontal direction in sequence. The word line structures 120 can include a gate dielectric layer 121 (e.g., high-k), a work function layer 122 (e.g., titanium nitride), a conductive layer 123 (e.g., tungsten), and an insulating cap layer 124 (e.g., oxide or nitride), without limitation. At least one of the word line structures 120 can further include a third aperture 124.1 in the insulating cap layer 124, without limitation.

[0035] The first insulating structures 171 are arranged on the substrate 100 in a horizontal direction and have a strip shape extending in a vertical direction. Each of the first insulating structures 171 includes at least a first insulating layer 151 and a second insulating layer 153. In an embodiment, the first insulating layer 151 and the second insulating layer 153 are arranged in a vertical direction in a top-bottom relationship. Specifically, the second insulating layer 153 is arranged on the top of the first insulating layer 151 and embedded in the first insulating layer 151. The second insulating layer 153 further extends to cover a portion of the height of the two outer sidewalls of the first insulating layer 151, such as the upper portion of the two outer sidewalls of the first insulating layer 151. In this way, the top surface of the second insulating layer 153 in each of the first insulating structures 171 is flush with the top surface of the first insulating layer 151 on both sides of the first insulating structure 171. In addition, at least one of the first insulating structures 171 further includes a first gap 102 in the first insulating layer 151 and a second gap 107 in the second insulating layer 153.

[0036] It should be noted that, in the embodiment of the present application, the first gap 102 in the first insulating layer 151 has a relatively long extension in the vertical direction, while the second gap 107 in the second insulating layer 153 is not limited in this way. Specifically, the bottom of the second gap 107 can be at the same horizontal level as the bottom of the second insulating layer 153, or can be higher than the bottom of the second insulating layer 153 in the vertical direction. In addition, the length of the second insulating layer 153 in the vertical direction can be different in different first insulating structures 171. Specifically, the bottom of the second insulating layer 153 in some of the first insulating structures 171 directly contacts the first gap 102 in the first insulating layer 151 in the first insulating structure 171, while the bottom of the second insulating layer 153 in other first insulating structures 171 does not directly contact the first gap 102 in the first insulating layer 151 in the first insulating structure 171. Specifically, the first insulating layer 151 and the second insulating layer 153 in some of the first insulating structures 171 define a gap at the interface between the first insulating layer 151 and the second insulating layer 153. Figure 13The first and second insulating layers 151, 153 define a void in the region identified by reference numeral 103'. Preferably, the void defined by the first and second insulating layers 151, 153 has a width in the horizontal direction that is greater than the width of the first slit 102 in the first insulating layer 151, and the top surface of the void defined by the first and second insulating layers 151, 153 is higher than the top surface of the first contact structure 161, but the bottom of the void defined by the first and second insulating layers 151, 153 can be higher than, lower than, or equal to the top surface of the first contact structure 161, but not limited thereto. Furthermore, the first slit 102 in the first insulating layer 151 and the second slit 107 in the second insulating layer 153 in the same first insulating structure 171 can be aligned in the same vertical direction (i.e., the vertical direction), and the first slit 102 in the first insulating layer 151 and / or the second slit 107 in the second insulating layer 153 in the same first insulating structure 171 and the third slit 124.1 in the word line structure 120 aligned with the first insulating structure 171 can also be aligned in the same vertical direction, but not limited thereto.

[0037] In an embodiment, at least some of the first insulating structures 171 further comprise a third insulating layer 152; specifically, the third insulating layer 152 can be located on the two outer sidewalls of the first insulating layer 151 in a first insulating structure 171, or the third insulating layer 152 can be located between the first insulating layer 151 and the second insulating layer 153 in a first insulating structure 171 and extend to cover the two outer sidewalls of the first insulating layer 151. In this arrangement, the portion of the second insulating layer 153 that covers the two outer sidewalls of the first insulating layer 151 is essentially located on the two outer sidewalls of the third insulating layer 152; and the third insulating layer 152 and the first insulating layer 151 in the same first insulating structure 171 can also define a void as identified by reference numeral 104 in the region directly contacting the first slit 102 in the first insulating layer 151. Of course, in other embodiments, the third insulating layer 152 in the same first insulating structure 171 can also directly contact the first slit 102 in the first insulating layer 151 without defining a void (not shown). Similarly, the void defined by the third insulating layer 152 and the first insulating layer 151 can also have a width in the horizontal direction that is greater than the width of the first slit 102 in the first insulating layer 151, and the top surface of the void defined by the third insulating layer 152 and the first insulating layer 151 can also be higher than the top surface of the first contact structure 161, but the bottom of the void is not limited, i.e., can be higher than, lower than, or equal to the top surface of the first contact structure 161, but not limited thereto. Figure 13 In an embodiment, at least some of the first insulating structures 171 further comprise a third insulating layer 152; specifically, the third insulating layer 152 can be located on the two outer sidewalls of the first insulating layer 151 in a first insulating structure 171, or the third insulating layer 152 can be located between the first insulating layer 151 and the second insulating layer 153 in a first insulating structure 171 and extend to cover the two outer sidewalls of the first insulating layer 151. In this arrangement, the portion of the second insulating layer 153 that covers the two outer sidewalls of the first insulating layer 151 is essentially located on the two outer sidewalls of the third insulating layer 152; and the third insulating layer 152 and the first insulating layer 151 in the same first insulating structure 171 can also define a void as identified by reference numeral 104 in the region directly contacting the first slit 102 in the first insulating layer 151. Of course, in other embodiments, the third insulating layer 152 in the same first insulating structure 171 can also directly contact the first slit 102 in the first insulating layer 151 without defining a void (not shown). Similarly, the void defined by the third insulating layer 152 and the first insulating layer 151 can also have a width in the horizontal direction that is greater than the width of the first slit 102 in the first insulating layer 151, and the top surface of the void defined by the third insulating layer 152 and the first insulating layer 151 can also be higher than the top surface of the first contact structure 161, but the bottom of the void is not limited, i.e., can be higher than, lower than, or equal to the top surface of the first contact structure 161, but not limited thereto.

[0038] It should be understood that the materials of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152 can all be insulating materials, such as silicon oxide, silicon nitride, etc., and the materials of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152 can be the same or different, but are preferably different insulating materials.

[0039] Further, the plurality of first contact structures 161 are respectively arranged in the horizontal direction and separated from each other between adjacent first insulating structures 171, and the top surface of each first contact structure 161 is lower than the top surface of any first insulating structure 171 located on both sides thereof; the silicide layer 162 is located on the top surface of the first contact structure 161, and the plurality of second contact structures 163 are respectively on the first contact structures 161 and extend in the horizontal direction to cover part of the top surface of the corresponding first insulating structure 171. The plurality of second insulating structures 172 are respectively located between adjacent second contact structures 163 and directly contact the first insulating structures 171 through the second contact structures 163. In the embodiment of the present application, the extension lengths of the plurality of second insulating structures 172 in the vertical direction can be different, so that part of the second insulating structures 172 can directly contact the gap in the corresponding first insulating structure 171 in the vertical direction, i.e., part of the second insulating structures 172 can directly contact the gap (the position identified by reference numeral 103' in the drawing) defined by the first insulating layer 151 and the second insulating layer 153 in the corresponding first insulating structure 171, as shown in FIG. 3; or, it can also directly contact the gap (not shown) defined by the first insulating layer 151 and the third insulating layer 152 in the corresponding first insulating structure 171 (the position identified by reference numeral 104 in the drawing); or, part of the second insulating structures 172 directly contact the second gap 107 in the second insulating layer 153 in the corresponding first insulating structure 171, but this is not limited thereto. Figure 13

[0040] ​In one embodiment, the material of the first contact structure 161 can include crystalline silicon, poly silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable silicon-containing semiconductor material, but is not limited thereto. For example, the material of the first contact structure 161 can be phosphorus-doped silicon (SiP). The second contact structure 163 can be a single-layer structure or a multi-layer structure, and the material thereof can include conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and is preferably titanium nitride (TiN), and can also be a metal material such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the foregoing, and is preferably tungsten (W), but is not limited thereto. The material of the second insulating structure 172 can be an insulating material such as nitride, silicon oxide, or the like, but is not limited thereto.

[0041] In addition, the plurality of capacitors 180 are respectively located on the second contact structure 163. Specifically, the capacitor 180 can include a lower electrode 181, a capacitor dielectric layer 182, and an upper electrode 183. The lower electrode 181 is disposed on the second contact structure 163, the upper electrode 183 is disposed on the lower electrode 181, and the capacitor dielectric layer 182 is disposed between the upper electrode 181 and the lower electrode 183.

[0042] Those skilled in the art to which the present application pertains should easily understand that, on the premise of meeting the actual product requirements, the semiconductor device of the present application can also have other forms and is not limited to the foregoing. Further embodiments or variations of the semiconductor device of the present application will be described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts will not be described repeatedly. In addition, the same components in the embodiments of the present application are marked with the same reference numerals for the convenience of mutual comparison between the embodiments.

[0043] Please refer to Figure 14As shown, the illustrated is a sectional view of a semiconductor device in the second embodiment of the present application. The structure of the semiconductor device in this embodiment is substantially the same as that of the semiconductor device in the first embodiment, and the semiconductor device also includes a plurality of word line structures 120, a plurality of first contact structures 161, a silicide layer 162, a plurality of second contact structures 163, a plurality of first insulating structures 171, a plurality of second insulating structures 172, and a plurality of capacitors 180. At least one of the first insulating structures 171 includes a first insulating layer 151 and a second insulating layer 153, and at least one of the first insulating structures 171 includes a first insulating layer 151, a second insulating layer 153, and a third insulating layer 152. A first gap 102 is disposed in the first insulating layer 151, and a second gap 107 is disposed in the second insulating layer 153. The same parts are not described again. The main difference between the semiconductor device in this embodiment and the semiconductor device in the first embodiment is that the first gap 102 in the first insulating layer 151 of at least one of the first insulating structures 171 is in communication with the second gap 107 in the corresponding second insulating layer 153, and / or the first gap 102 in the first insulating layer 151 of at least one of the first insulating structures 171 is in direct contact with the gap 103' defined at the junction of the first insulating layer 151 and the corresponding second insulating layer 153, that is, the first gap 102, the gap 103', and the second gap 107 in one of the first insulating structures 171 are in communication, but not limited thereto.

[0044] Further, based on the same concept, the present application also provides a manufacturing method for manufacturing the semiconductor device, which can include the following steps:

[0045] Step S100, providing a substrate 100;

[0046] Step S200, forming a plurality of first insulating structures 171, which are arranged on the substrate 100 in a mutually separated manner, and the first insulating structures 171 include a first insulating layer 151 and a second insulating layer 153. At least one of the first insulating structures 171 includes a first gap 102 and a second gap 107 in the first insulating layer 151 and the second insulating layer 153, respectively.

[0047] Step S300, forming a plurality of first contact structures 161 between adjacent first insulating structures 171.

[0048] For the purpose of enabling the person of ordinary skill in the art to which the present application pertains to easily understand the method for manufacturing the semiconductor device in the present application, the method for manufacturing the semiconductor device in the present application will be further described in the following with reference to the structural schematic diagrams of the method for manufacturing the semiconductor device in the present application in the manufacturing process.

[0049] Please refer to Figures 1-14 The structural schematic diagram of the method for manufacturing the semiconductor device in the present application in the manufacturing process is shown. Figure 1 The structural schematic diagram of the method for manufacturing the semiconductor device in the present application in the manufacturing process is shown. Figures 2-14 The partial structure top view of the semiconductor device is shown in order to distinguish the position relationship of the different components and / or devices of the semiconductor device in the present application, Figures 2-14 The partial structure sectional view of the different components and / or devices of the semiconductor device in the manufacturing process is shown. Figure 1 The partial structure sectional view of the different components and / or devices of the semiconductor device in the manufacturing process is shown.

[0050] As shown in Figure 1 The semiconductor device in the present application can include a plurality of word line structures 120 and a plurality of bit line structures BL staggered with the word line structures 120, and a plurality of active regions ACT arranged in the substrate 100, and the AA cut line is located between any two adjacent bit line structures BL and the extension direction of the AA cut line is the same as the extension direction of any bit line structure BL, so that the bit line structure BL is not shown in the partial structure sectional view as shown in Figures 2-14 The partial structure sectional view is shown.

[0051] As shown in Figure 2As shown, the above step S100 is performed as follows: First, a substrate 100 (e.g., a silicon substrate) is provided, and then a plurality of trench isolations 110 and word line structures 120 located within the trench isolations 110 are formed in the substrate 100. In one embodiment, the process of forming the trench isolation 110 and the word line structure 120 may include: forming a plurality of trenches arranged sequentially in a horizontal direction in the substrate 100 using at least one of etching processes such as dry etching or wet etching; then filling the plurality of trenches with an insulating material (such as silicon oxide, silicon nitride, etc.) using at least one of deposition processes such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition to form the trench isolation 110; the plurality of trench isolations 110 define a plurality of active regions ACT in the substrate 100; then forming a gate dielectric layer 121 (such as a high dielectric constant), a work function layer 122 (such as titanium nitride), a conductive layer 123 (such as tungsten metal), and an insulating capping layer 124 (such as an oxide or nitride) with a third gap 124.1 inside the trench isolation 110 using a deposition process, thereby forming the word line structure 120. It should be understood that the third gap 124.1 may be located in the insulating cover layer 124 of each of the plurality of word line structures 120, or in the insulating cover layer 124 of some of the word line structures 120, but is not limited thereto.

[0052] Next, an isolation layer 130 may be formed on the surface of the substrate 100. In one embodiment, the isolation layer 130 may be a single-layer structure (e.g., Figure 2 (As shown), such as a silicon oxide layer or a silicon nitride layer, or a composite layer (not shown), such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but not limited thereto.

[0053] like Figure 3 As shown, following step S100, a sacrificial layer 140 of a certain thickness can be formed on the isolation layer 130 of the substrate 100 using at least one deposition process such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In one embodiment, the material of the sacrificial layer 140 may be a single-layer or multi-layer oxide material, such as silicon oxide, borophospho-silicate glass (BPSG), or other sacrificial materials, but is not limited thereto.

[0054] like Figure 4As shown, following step S100 above, an etching process such as dry etching can be used to form a plurality of through holes 101 arranged sequentially and spaced apart in the horizontal direction in the sacrificial layer 140; in one embodiment, the number of through holes 101 may be the same as the number of word line structures 120, and one pair of through holes 101 is located in one word line structure 120. It should be noted that in this embodiment of the present invention, each through hole 101 not only penetrates the sacrificial layer 140 in the vertical direction, but also further penetrates the isolation layer 130 below the sacrificial layer 140 and part of the height of the insulating capping layer 124 in the corresponding word line structure 120, so that the bottom of the through hole 101 exposes the remaining insulating capping layer 124. That is, the bottom surface of the through hole 101 is lower than the bottom surface of the substrate 100 or the isolation layer 130, thereby allowing the bottom of the first insulating layer 151 subsequently filled in the through hole 101 to directly contact the remaining insulating capping layer 124 in each word line structure 120, but this is not a limitation.

[0055] like Figure 5 As shown, in performing step S200 above: a first insulating layer 151 with a first gap 102 inside can be formed on the substrate 100 using a deposition process such as chemical vapor deposition. At this time, the material of the first insulating layer 151 with the first gap 102 not only fills each of the through-holes 101, but also extends laterally in the horizontal direction, covering the top surface of the sacrificial layer 140 exposed between adjacent through-holes 101. In one embodiment, the material of the first insulating layer 151 can be silicon oxide or silicon nitride, but is not limited thereto; the shape of the first gap 102 located within the first insulating layer 151 can be a grid-like gap extending in the vertical direction, and the length of the long side of the first gap 102 in the vertical direction is much greater than the length of its short side in the horizontal direction, for example, its long side can be N times the length of its short side, where N≥3. It should be understood that... Figure 5 The first insulating layer 151 located in each through hole 101 is provided with a first gap 102. In other embodiments, the first insulating layer 151 located in some of the through holes 101 may be provided with a first gap 102, that is, at least one of the first insulating layers 151 located in the through hole 101 is not provided with a first gap 102 (not shown), but this is not a limitation.

[0056] like Figure 6As shown, step S200 is performed by performing a back-etching process on the first insulating layer 151, which is laterally extended and covers the top surface of the exposed sacrificial layer 140 between adjacent through holes 101, for example, by performing a dry etching process, to remove the material of the first insulating layer 151 above the top surface of the sacrificial layer 140, and to partially remove the first insulating layer 151 located in one or more through holes 101, to form a recess 103 on the top of the first insulating layer 151 located in the through hole 101. In an embodiment, the bottom of the recess 103 located in a through hole 101 can be directly in contact with the first gap 102 in the remaining first insulating layer 151 in the through hole 101. Moreover, the bottoms of the recesses 103 on the top of the first insulating layer 151 in different through holes 101 can be located at different levels, i.e., the bottoms of the recesses 103 have a height difference in the vertical direction, and the height difference also causes the shapes of the recesses 103 between different recesses 103 to have a partial difference, but not limited thereto.

[0057] As shown in Figure 7 and Figure 8 , step S200 is performed by first removing the sacrificial layer 140 between adjacent through holes 101 to expose the two outer sidewalls of the first insulating layer 151 located in the through hole 101, as shown in Figure 7 ; and then forming a third insulating layer 152 on the substrate 100 to fill the recess 103 and the two outer sidewalls of the first insulating layer 151. In an embodiment, because the depths of the recesses 103 in different through holes 101 are different in the vertical direction, the third insulating layer 152 filled in different recesses 103 also has a gap in at least part of the third insulating layer 152 in the recess 103, as shown in Figure 8 , the area identified by reference numeral 105, and the gap between the third insulating layer 152 filled in part of the through hole 101 and the first insulating layer 151 located in the same through hole 101 defines a void, as shown in Figure 8 , the area identified by reference numeral 104. The bottoms of the gaps 105 in the third insulating layer 152 located in different recesses 103 can be located at the same level or at different levels, and the top surface and / or the bottom surface of the void 104 defined by the third insulating layer 152 and the first insulating layer 151 located in different through holes 101 can also be the same or different. In addition, the materials of the third insulating layer 152 and the first insulating layer 151 can both be insulating materials, such as silicon oxide or silicon nitride, but not limited thereto, and the materials of the two can be the same or different, but preferably different.

[0058] As shown in Figure 9 and Figure 10As shown, the step S300 is performed: then the etching process, such as dry etching process, is utilized to remove the isolation layer 130 and the partial height of the substrate 100 under the isolation layer 130, which is located opposite to the word line structure 120, in the vertical direction, to form a plurality of first contact recesses 106 for the subsequent preparation of the first contact structure 161, and then the deposition process is utilized to fill the first contact material layer 160 (such as single crystal silicon or polycrystalline silicon) in the first contact recesses 106; at this time, the first contact material layer 160 not only fills the first contact recesses 106, but also extends laterally to cover the top surface and sidewall of the first insulating layer 151 and the third insulating layer 152 in the horizontal direction, so as to bury the film layer structure on the substrate 100.

[0059] As shown in Figure 11 and Figure 12 the step S300 is performed: the first contact material layer 160, which laterally extends to cover the top surface and part of the sidewall of the first insulating layer 151 and the third insulating layer 152, is further removed by etching, so as to form the first contact structure 161, the top surface of which is lower than the top surface of the first insulating layer 151 or the top surface of the third insulating layer 152. During this etching removal process, the third insulating layer 152 located in the recess 103 is not shielded and is also removed by a partial height, and the third insulating layer 152 located in the recess 103 with different depths is also removed by different heights in this step, for example, the third insulating layer 152 in the recess 103 with a deeper vertical depth is also partially remained after this step, and the third insulating layer 152 in the recess 103 with a shallower vertical depth is completely removed, but not limited thereto. Then, the deposition process is further utilized to form the second insulating layer 153 (the material is, for example, silicon nitride) in the space left by the recess 103 and on the two sidewalls exposed by the third insulating layer 152, and the second insulating layer 153 in the space left by the recess 103 also has a gap, such as the second gap 107. At this time, the first insulating structure 171 composed of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152, or composed of the first insulating layer 151 and the third insulating layer 152, is formed.

[0060] It should be understood that, due to the different depths of different recesses 103 in the vertical direction (i.e., different extension lengths in the vertical direction), and the third insulating layer 152 formed in the recess 103 with a partial depth also has a gap at the interface with the corresponding first insulating layer 151, such as the area identified by reference numeral 103' in Figure 12 , but not limited thereto.

[0061] Also, when forming the second insulating layer 153 with the second slit 107 by this step, there will also exist the first slit 102 in the first insulating layer 151 in at least one of the plurality of first insulating structures 171 formed as shown Figure 14 communicates with the second slit 107 in the corresponding second insulating layer 153; and / or, the first slit 102 in the first insulating layer 151 in at least one of the plurality of first insulating structures 171 directly contacts the void 103' defined at the interface between the first insulating layer 151 and the corresponding second insulating layer 153, that is, the first slit 102, the void 103' and the second slit 107 in one first insulating structure 171 communicate with each other.

[0062] As shown in Figure 13 or Figure 14 After the above step S300, a silicide layer 162 is formed on the top surface of the first contact structure 161 by deposition and etching process, and then a plurality of second contact structures 163 (material such as titanium nitride and / or tungsten) are formed on the silicide layer 162 and horizontally separated between adjacent first insulating structures 171, and the second contact structures 163 also extend horizontally on part of the top surface of the corresponding first insulating structure 171; then, a plurality of second insulating structures 172 (material such as silicon oxide or silicon nitride) are formed between adjacent second contact structures 163 and directly contact the first insulating structure 171 through the second contact structures 163. In an embodiment, the second insulating structures 172 can have different vertical extension lengths, so that some of the second insulating structures 172 can vertically pass through the corresponding first insulating structure 171 and directly contact the void therein, that is, some of the second insulating structures 172 can directly contact the void (position identified by reference numeral 103') defined by the first insulating layer 151 and the second insulating layer 153 in the corresponding first insulating structure 171, as shown in Figure 13 or Figure 14 or, some of the second insulating structures 172 can directly contact the void (position identified by reference numeral 104) defined by the first insulating layer 151 and the third insulating layer 152 in the corresponding first insulating structure 171 (not shown); or, some of the second insulating structures 172 directly contact the second slit 107 in the second insulating layer 153 in the corresponding first insulating structure 171, but not limited thereto.

[0063] Next, a capacitor 180 is formed on the second contact structure 163. In one embodiment, the capacitor 180 can include a lower electrode 181, a capacitor dielectric layer 182, and an upper electrode 183. The materials of the lower electrode 181 and the upper electrode 183 can be conductive materials, such as doped silicon, tungsten, copper, titanium nitride, or others, without limitation, and the material of the capacitor dielectric layer 182 can be a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials, or other suitable dielectric materials, without limitation, and the material of the upper electrode 183 can include titanium nitride, tantalum nitride, SiGe, combinations of the above materials, or other suitable conductive materials, without limitation.

[0064] It should be understood that the "co-molded" in the present application refers to the similarity and relevance of the shapes of two or more shapes, and the continuous structural shape is constructed.

[0065] In summary, in the present application, the plurality of first insulation structures at least include a first insulation layer and a second insulation layer, wherein the first insulation layer and the second insulation layer of at least one first insulation structure are respectively provided with a gap, such as a first gap in the first insulation layer and a second gap in the second insulation layer, and the first insulation layer and the second insulation layer of at least one first insulation structure define a void, that is, by setting the first insulation structure as a composite structure and having a gap and / or void in the multiple insulation layers contained therein, a new structure of the first insulation structure and a semiconductor device for protecting the new structure can also improve the performance and reliability of the semiconductor device.

[0066] The above only describes the preferred embodiments of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application is included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate; a plurality of first insulating structures, disposed on the substrate and spaced apart from each other, and the first insulating structure comprises a first insulating layer and a second insulating layer, wherein at least one of the first insulating layer and the second insulating layer of the first insulating structure comprises a first gap and a second gap, respectively; a plurality of first contact structures, located between adjacent first insulating structures.

2. The semiconductor device of claim 1, wherein, The first insulating layer and the second insulating layer of at least one of the first insulating structures define a gap, and the width of the gap in the horizontal direction is greater than the width of the first gap in the first insulating layer in the horizontal direction.

3. The semiconductor device of claim 2, wherein, The gap contacts the first gap and / or the second gap.

4. The semiconductor device of claim 2, wherein, The top surface of the gap is higher than the top surface of the first contact structure.

5. The semiconductor device of claim 1, wherein, Further comprising: a plurality of word line structures, disposed in the substrate and spaced apart from each other, and at least one of the word line structures comprises an insulating cap layer having a third gap, and the first insulating layer extends into the insulating cap layer in the vertical direction and directly contacts the insulating cap layer.

6. The semiconductor device of claim 1, wherein, The first insulating structure further comprises: a third insulating layer, located on the two outer sidewalls of the first insulating layer.

7. The semiconductor device of claim 6, wherein, The third insulating layer of at least one of the first insulating structures is also located between the first insulating layer and the second insulating layer, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

8. The semiconductor device of claim 1, wherein, The first gap in the first insulating layer is aligned with the second gap in the second insulating layer in the same vertical direction.

9. The semiconductor device of claim 8, wherein, The first gap in the first insulating layer is in communication with the second gap in the second insulating layer.

10. The semiconductor device of claim 5, wherein, The third gap of the insulating cap layer of at least one of the word line structures is aligned with the first gap in the first insulating layer and / or the second gap in the second insulating layer in the same vertical direction.

11. The semiconductor device of claim 7, wherein, The second insulating layer further extends to cover part of the sidewall of the third insulating layer located on the two outer sidewalls of the first insulating layer.

12. The semiconductor device of claim 11, wherein, Further comprising: a plurality of second contact structures, located on the first contact structures and extending to cover part of the top surface of the first insulating structure in the horizontal direction.

13. The semiconductor device of claim 12, wherein, Further comprising: a plurality of second insulating structures, located between adjacent second contact structures and directly contacting the first insulating structure through the second contact structures.

14. The semiconductor device of claim 13, wherein, At least one of the second insulating structures directly contacts the gap in the first insulating structure.

15. The semiconductor device of claim 13, wherein, At least one of the second insulating structures directly contacts the second gap in the second insulating layer of the first insulating structure.

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