Input / output transmitter of serializer / deserializer, serializer / deserializer and switch system

Abstract

The utility model discloses an input / output transmitter of a serializer / deserializer, the serializer / deserializer and a switch system. The input and output transmitter of the serializer / deserializer comprises a transmitter and a first number of delay control circuits, the transmitter comprises a second number of channels, the second number is equal to the sum of the first number and 1, each delay control circuit is connected with one channel in the transmitter in a one-to-one mode, each delay control circuit comprises a resistor and a capacitor, and the resistor and the capacitor are connected in a one-to-one mode. The first end of the resistor is connected with the first end of the capacitor and the enabling end of one channel. According to the scheme provided by the embodiment of the invention, the problem that the voltage drop of the Serdes chip end is too large when the Serdes IO power supply is powered on due to the load effect can be effectively solved, and the occurrence rate that the voltage drop of the Serdes chip end is too large when the Serdes IO power supply is powered on due to the load effect is reduced; the probability that the chip end voltage is kept above the normal working threshold value is greatly improved, so that the normal working probability of the switch system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switch chip, in particular to an input and output transmitter of a serializer / deserializer, a serializer / deserializer and a switch system. BACKGROUND

[0002] Switching Chip is a hardware component used to realize network switching function, which is the core part of network switch and is responsible for high-speed data packet forwarding and switching. In computer networks, Switching Chip plays a key role in determining the performance and function of the switch, and is widely used in various network devices such as Ethernet switch, router and network switching device in data center.

[0003] In the application scenario of power-on of the high-speed serial / parallel interface Serdes IO of the switch chip, if all channels of the switch are connected at the same time, the load effect will cause the voltage at the Serdes chip end to drop below the normal working threshold, thereby causing the switch to fail to work.

[0004] The above statements are only used to provide background technical information related to the present application, and do not necessarily constitute the prior art. CONTENT OF THE INVENTION

[0005] The purpose of the present application is to provide an input and output transmitter of a serializer / deserializer, a serializer / deserializer and a switch system. In order to have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not a general review, nor does it determine the key / important components or delineate the protection scope of these embodiments. Its only purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0006] According to one aspect of the embodiments of the present application, an input and output transmitter of a serializer / deserializer is provided, comprising a transmitter and a first number of delay control circuits; the transmitter comprises a second number of channels, the second number being equal to the sum of the first number and 1; each delay control circuit is connected one-to-one with a channel in the transmitter.

[0007] The delay control circuit comprises a resistor and a capacitor, and the first end of the resistor is connected to the first end of the capacitor and the enable end of a channel, respectively.

[0008] In some embodiments of the present application, the transmitter comprises 8 channels, and each delay control circuit is used to control the transmission signal time of the channel connected thereto.

[0009] In some embodiments of the present application, the power-on time of the eight channels is 0, 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively, T represents the time length required for the channel current to change from the idle state to the working state; the capacitance charging time constant of the delay control circuit connected to the channel with the power-on time of 2T, 4T, 6T, 8T, 10T, 12T and 14T is 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively.

[0010] According to another aspect of the embodiments of the present application, a serializer / deserializer is provided, which comprises the input / output transmitter of any of the embodiments of the present application.

[0011] According to another aspect of the embodiments of the present application, a switch system is provided, which comprises a switch chip, and the switch chip comprises the serializer / deserializer of any of the embodiments of the present application.

[0012] One of the aspects of the embodiments of the present application provides a technical solution which can include the following beneficial effects:

[0013] The input / output transmitter of the serializer / deserializer provided by the embodiments of the present application comprises a transmitter and a first number of delay control circuits, the transmitter comprises a second number of channels, the second number is equal to the sum of the first number and 1, each delay control circuit is connected to one channel in the transmitter in one-to-one manner, the delay control circuit comprises a resistor and a capacitor, and the first end of the resistor is connected to the first end of the capacitor and the enable end of one channel, which can effectively solve the problem of excessive voltage drop at the chip end of the Serdes during power-on due to the load effect of the Serdes IO power supply, reduce the incidence of excessive voltage drop at the chip end of the Serdes during power-on due to the load effect of the Serdes IO power supply, greatly improve the probability that the chip end voltage remains above the threshold value for normal operation, and thus improve the probability of normal operation of the switch system.

[0014] The above description is only a summary of the technical solutions of the embodiments of the present application, in order to more clearly understand the technical means of the embodiments of the present application, the embodiments can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0016] Figure 1 Serdes IO transmitter schematic diagram for related art (take 8-channel Serdes as an example).

[0017] Figure 2 Serdes IO transmitter schematic diagram for an embodiment of the present application (take 8-channel Serdes as an example).

[0018] Figure 3 Equivalent circuit diagram of Serdes IO delay control module for an embodiment of the present application.

[0019] Figure 4 Power supply network PDN schematic diagram for Serdes IO power supply

[0020] Figure 5 Current schematic diagram of a single channel of a Serdes module in related art (8-channel current waveforms are superimposed together, current unit: milliampere) when 8 channels are simultaneously switched from idle state to working state.

[0021] Figure 6 Total current schematic diagram of 8 channels of a Serdes module in related art (current unit: ampere) when 8 channels are simultaneously switched from idle state to working state.

[0022] Figure 7 Voltage waveform diagram obtained at the Serdes chip end when a Serdes module is simultaneously switched from idle state to working state in related art.

[0023] Figure 8 Current schematic diagram of a single channel of a Serdes module in an embodiment of the present application (current unit: milliampere) when 8 channels are switched from idle state to working state in stages.

[0024] Figure 9 Total current schematic diagram of 8 channels of a Serdes module in an embodiment of the present application (current unit: ampere) when 8 channels are switched from idle state to working state in stages.

[0025] Figure 10 Voltage waveform diagram obtained at the Serdes chip end when a Serdes module is switched from idle state to working state in stages in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purposes, technical solutions and advantages of the present application clearer, further explanations will be given below in conjunction with the drawings and embodiments. It should be understood that the embodiments described herein are only used to explain the present application and not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0027] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present application. It should also be understood that terms such as those defined in a general dictionary have meanings consistent with those in the context of the prior art and should not be interpreted in an idealized or overly formal sense unless specifically defined as such herein.

[0028] Name abbreviation of professional term meaning:

[0029] PDN: abbreviation of Power Delivery Network, i.e. power supply network.

[0030] Serdes: abbreviation of Serielizer / De-Serializer, i.e. serializer / deserializer, which is an interface circuit in high-speed data communication.

[0031] IO: input / output.

[0032] Reference Figure 1 As shown, Figure 1 is a schematic diagram of a Serdes IO transmitter in the related art (taking an 8-channel Serdes as an example). In the related art, a 56Gbps Serdes module contains 8 channels. A 12.8T bandwidth capacity switch uses 32 Serdes modules. If all 32x8 = 256 channels are connected at the same time, the load effect will cause the voltage at the Serdes chip end to drop below the normal working threshold, thereby causing the switch system to fail to work. Since a high-capacity switch has more Serdes modules, the above-mentioned situation is particularly prone to occur in a high-capacity switch.

[0033] To solve the problems in the prior art, the embodiment of the present application provides an input and output transmitter of a serializer / deserializer, which comprises a transmitter and a first number of delay control circuits. The transmitter comprises a second number of channels, and the second number is equal to the sum of the first number and 1. Each delay control circuit is connected to one channel of the transmitter in one-to-one mode. The delay control circuit comprises a resistor and a capacitor. The first end of the resistor is connected to the first end of the capacitor and the enable end of one channel. The scheme provided in the embodiment of the present application can effectively solve the problem of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, reduce the incidence of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, and greatly improve the probability that the chip end voltage is kept above the threshold value for normal operation, thereby improving the probability of normal operation of the switch system.

[0034] An input and output transmitter of a serializer / deserializer, a serializer / deserializer and a switch system according to the embodiment of the present application are described below with reference to the accompanying drawings.

[0035] Reference Figure 2 An embodiment of the present application provides an input and output transmitter of a serializer / deserializer, which comprises a transmitter and a first number of delay control circuits. The transmitter comprises a second number of channels, and the second number is equal to the sum of the first number and 1. Each delay control circuit is connected to one channel of the transmitter in one-to-one mode. Reference Figure 3 As shown in the figure, the delay control circuit comprises a resistor R and a capacitor C. The first end of the resistor R is connected to the first end of the capacitor C and the enable end of one channel. The second end of the resistor R is connected to the power supply VDD. The first end of the resistor R is connected to the enable port of the Serdes IO transmitter. The second end of the capacitor C is grounded.

[0036] Exemplarily, reference Figure 2 As shown in the figure, the transmitter comprises eight channels, i.e., the second number is eight and the first number is seven. Each delay control circuit is used to control the transmission signal time of the channel connected thereto. As Figure 2 As shown in the figure, the first channel of the eight channels is not connected to a delay control circuit, and the other seven channels are each connected to a delay control circuit.

[0037] Exemplarily, the power-on times of the eight channels are 0, 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively, T represents the time length required for the channel current to change from an idle state to a working state; and the capacitor charging time constants of the delay control circuits connected to the channels with the power-on times of 2T, 4T, 6T, 8T, 10T, 12T and 14T correspond to 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively.

[0038] Another embodiment of the present application provides a serializer / deserializer, comprising the input / output transmitter of any embodiment of the present application. The serializer / deserializer can effectively solve the problem of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, reduce the incidence of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, greatly increase the probability that the chip end voltage remains above the threshold for normal operation, and thus improve the probability of normal operation of the switch system.

[0039] Another embodiment of the present application provides a switch system, comprising a switch chip, and the switch chip comprises the serializer / deserializer of any embodiment of the present application. The switch system can effectively solve the problem of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, reduce the incidence of excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply, greatly increase the probability that the chip end voltage remains above the threshold for normal operation, and thus improve the probability of normal operation of the switch system.

[0040] Exemplarily, the switch system further comprises a power supply network of the input / output power supply of the serializer / deserializer. As shown in Figure 4 Figure 4 The figure is a power supply network PDN diagram for the Serdes IO power supply, C_die represents the equivalent capacitance of the chip die, R_die represents the equivalent resistance of the chip die, C_PKG represents the terminated decoupling capacitance on the package substrate, L_PKG represents the equivalent inductance of the package substrate, C_PCB represents the terminated decoupling capacitance on the circuit board, L_PCB represents the equivalent inductance of the circuit board, and C_bulk represents the remote decoupling capacitance with a large capacitance value on the circuit board.

[0041] In the current switching event on the chip (ASIC), a high-speed switching current is generated on the chip, and the current is provided by the above-mentioned power supply network. Due to the non-ideal physical characteristics of the above-mentioned power supply network, i.e., the equivalent chip on-chip resistance R_die and the circuit board inductance L_PCB and the package substrate inductance L_PKG, an alternating voltage noise and a direct current voltage drop will be generated during the power-on process at the chip end. The alternating voltage noise and the direct current voltage drop will cause the chip end voltage to exceed the chip design range. Therefore, it is of great practical significance to reduce the excessive voltage drop at the chip end of the Serdes during power-on caused by the load effect of the Serdes IO power supply.

[0042] ​Unlike the 8-channel Serdes module in the related art, the embodiments of the present application can independently control the behavior of each channel of the Serdes module. According to the time T of the current transition from the idle state to the working state, the minimum time interval of 8-channel staggered excitation in a Serdes module is 2T. The excitation time of each channel is independently controlled to stagger with each other, and the time interval is not less than the minimum time interval 2T. Since each Serdes delay control module independently controls each Serdes transmitter channel, the resistance R and capacitance C values of each delay control module are different.

[0043] Taking the 8-channel Serdes module in the above embodiment as an example, the power-on time of the eight channels is 0, 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively. Therefore, the design of the resistance value R and the capacitance value C of the delay control module needs to meet R2·C2=2T, R3·C3=4T, R4·C4=6T, R5·C5=8T, R6·C6=10T, R7·C7=12T, R8·C8=14T.

[0044] Among them, the first channel does not need a delay control module. The start-up time of multiple different Serdes modules can be the same or different. Similarly, the Serdes module power-down sequence also operates in the same way, which can reduce the voltage climb caused by the load effect.

[0045] In the power supply network PDN of the Serdes IO power supply in the related art, because the circuit board and the package substrate have resistance and inductance, and the current required by the chip provided by the power supply will flow through the PCB circuit board and the package substrate, when the voltage is transmitted from the power supply to the chip end, the direct voltage drop and the alternating voltage drop will be generated, and all the voltage drops are superimposed together, which will cause the voltage reaching the chip end to be less than the original voltage of the power supply. If the voltage reaching the chip end does not meet the rated voltage of the chip Serdes working, the switch system cannot work.

[0046] As shown in Figure 5 and Figure 6 , Figure 5 is a single-channel current diagram of 8 channels of a Serdes module in the related art at the same time from the idle state to the working state (8-channel current waveforms are superimposed together, current unit: milliampere), Figure 6 is a total current diagram of 8 channels of a Serdes module in the related art at the same time from the idle state to the working state (current unit: ampere). A single-channel current and total current diagram of 8 channels of a Serdes module at the same time from the idle state to the working state. Because the current is excited at the same time, a large IR drop voltage drop will be generated at the chip end. As shown inFigure 7 As shown in the figure, the IO power supply with a voltage of 750 mV is reduced to 690 mV due to the load effect when reaching the Serdes chip end, and the voltage drop is up to 60 mV, which exceeds the acceptable voltage drop range of the Serdes module, thus causing the voltage at the chip end to be lower than the threshold for normal operation, resulting in the failure of the switch system. Meanwhile, it can be seen that, when the Serdes module is powered off, the voltage produces a climbing peak of 775 mV due to the load effect, which exceeds the voltage source of 750 mV, and is also not conducive to the long-term stable operation of the switch chip.

[0047] As shown in the figure, Figure 8 and Figure 9 As shown in the figure, Figure 8 In an embodiment of the present application, the current diagram of a single channel of an 8-channel Serdes module in the process of changing from an idle state to a working state (current unit: mA), Figure 9 In an embodiment of the present application, the total current diagram of 8 channels of an 8-channel Serdes module in the process of changing from an idle state to a working state (current unit: A). In this way, the large voltage drop caused by the large current started at the same time is changed into the peak stacking of multiple small voltage drops caused by multiple small currents started at different times, and the peak stacking of multiple small voltage drops does not cause a large total voltage drop, thus effectively solving the problem of excessive voltage drop at the Serdes chip end when the Serdes IO power supply is powered on due to the load effect, greatly improving the probability of keeping the voltage at the chip end above the threshold for normal operation, and improving the probability of normal operation of the switch system.

[0048] As shown in the figure, Figure 10 As shown in the figure, the IO power supply with a voltage of 750 mV is reduced to 690 mV due to the load effect when reaching the Serdes chip end, and the voltage drop is up to 60 mV, which exceeds the acceptable voltage drop range of the Serdes module, thus causing the voltage at the chip end to be lower than the threshold for normal operation, resulting in the failure of the switch system. Meanwhile, it can be seen that, when the Serdes module is powered off, the voltage produces a climbing peak of 775 mV due to the load effect, which exceeds the voltage source of 750 mV, and is also not conducive to the long-term stable operation of the switch chip.

[0049] The above description of various embodiments tends to emphasize the differences between various embodiments, and the same or similar parts can be referred to each other, and will not be described herein for the sake of brevity.

[0050] It should be pointed out that the above examples only express the embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An input / output transmitter for a serializer / deserializer, comprising: The input / output transmitter comprises a transmitter and a first number of delay control circuits; the transmitter comprises a second number of channels, the second number being equal to the sum of the first number and 1; each of the delay control circuits is connected to one channel of the transmitter in one-to-one correspondence; The delay control circuit comprises a resistor and a capacitor, and a first end of the resistor is connected to a first end of the capacitor and an enable end of one channel respectively.

2. The input-output transmitter of claim 1, wherein, The transmitter comprises eight channels, and each of the delay control circuits is used to control the transmission signal time of the channel connected thereto.

3. The input-output transmitter of claim 2, wherein, The power-on times of the eight channels are 0, 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively, T representing the time length required for the channel current to change from an idle state to an active state; the capacitor charging time constants of the delay control circuits connected to the channels with the power-on times of 2T, 4T, 6T, 8T, 10T, 12T and 14T are 2T, 4T, 6T, 8T, 10T, 12T and 14T respectively.

4. A serializer / deserializer, comprising: The input / output transmitter comprises any one of claims 1-3.

5. A switch system, characterized by The switch chip comprises a serializer / deserializer according to claim 4.

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