Charge-discharge cycle voltage controllable circuit for tested capacitor

Abstract

The utility model discloses a charge-discharge cycle voltage controllable circuit for a tested capacitor, and relates to the technical field of tested capacitor testing. Comprising a direct-current power supply, a charging and discharging loop, a tested capacitor, a PWM control loop and an MCU control circuit. The MCU control circuit is connected with the PWM control loop and is in communication connection with the direct-current power supply, the direct-current power supply is connected with the charging and discharging loop, the charging and discharging loop is connected with the tested capacitor, and the PWM control circuit is respectively connected with the charging and discharging loop and the tested capacitor; the MCU control circuit is used for controlling the charging and discharging loop through the PWM control loop to realize cyclic control of charging and discharging of the tested capacitor, and the MCU control circuit is also used for controlling the discharging voltage of the tested capacitor and controlling the output voltage of the direct current input power supply, so that the discharging voltage of the charging capacitor is adjustable.

Description

Technical Field

[0001] This utility model relates to the field of capacitor testing technology, specifically a circuit for controllable voltage during the charging and discharging cycle of a capacitor under test. Background Technology

[0002] With the upgrading and development of electronic products, the requirements for the capacitors under test in circuits are also getting higher and higher. Therefore, it is necessary to test the charging and discharging capabilities of the capacitors under test in different applications to improve the reliability of the capacitors under test.

[0003] Existing capacitor charge / discharge test circuits and national standards all involve charging from 0V to the rated voltage and then discharging from the rated voltage back to 0V, cycling through these cycles to test the charge / discharge capability.

[0004] However, in some applications, the discharge voltage needs to be >0V. Existing capacitor charging and discharging circuits cannot control the discharge voltage of the capacitor under test or modulate the pulse width and period, thus failing to meet the requirements of some special applications. Utility Model Content

[0005] The purpose of this invention is to provide a controllable voltage circuit for the charging and discharging cycle of a capacitor under test, which can effectively solve the problems in the background art.

[0006] The technical solution to achieve the above objective is: a controllable voltage circuit for the charging and discharging cycle of a capacitor under test, characterized in that it includes a DC power supply, a charging and discharging circuit, the capacitor under test, a PWM control loop, and an MCU control circuit;

[0007] The MCU control circuit is connected to the PWM control loop and communicates with the DC power supply. The DC power supply is connected to the charging and discharging circuit, which is connected to the capacitor under test. The PWM control circuit is connected to both the charging and discharging circuit and the capacitor under test.

[0008] The MCU control circuit is used to control the charging and discharging circuit through the PWM control loop, so as to realize the cyclic control of charging and discharging of the capacitor under test. The MCU control circuit is also used to control the discharge voltage of the capacitor under test and the output voltage of the DC input power supply.

[0009] Furthermore, the MCU control circuit includes a microcontroller, a digital-to-analog converter chip, an isolated RS-485 / RS-422 transceiver, NOT gate U1A, NOT gate U2B, resistors R3 and R4, and capacitors C1, C2, and C4.

[0010] The output terminal 1 of the microcontroller is connected to pin 1 of NOT gate U1A, pin 2 of NOT gate U1A is connected to one end of resistor R3, the output terminal 2 of the microcontroller is connected to pin 3 of NOT gate U2B, pin 4 of NOT gate U2B is connected to one end of resistor R4, and the other ends of resistors R3 and R4 are connected to the PWM control loop.

[0011] The microcontroller's UART2_TX pin is connected to pin 6 of the isolated RS-485 / RS-422 transceiver; the microcontroller's UART2_EN pin is connected to pins 4 and 5 of the isolated RS-485 / RS-422 transceiver; the microcontroller's UART2_RX pin is connected to pin 3 of the isolated RS-485 / RS-422 transceiver; the microcontroller's CS8532D pin is connected to pin 5 of the digital-to-analog converter chip; the microcontroller's SPI2-MOSI pin is connected to pin 7 of the digital-to-analog converter chip; and the microcontroller's SPI2-SCLK pin is connected to pin 6 of the digital-to-analog converter chip.

[0012] Pin 1 of the isolated RS-485 / RS-422 transceiver is grounded via capacitor C1 and connected to a 3.3V DC power supply. Pins 2, 7, and 8 of the isolated RS-485 / RS-422 transceiver are all grounded. Pins 9 and 15 of the isolated RS-485 / RS-422 transceiver are connected in parallel. Pins 12 and 13 of the isolated RS-485 / RS-422 transceiver are connected to the communication terminal of the DC power supply. Capacitor C2 is connected in parallel between pins 15 and 16 of the isolated RS-485 / RS-422 transceiver.

[0013] Pin 2 of the digital-to-analog converter chip is connected to an external reference voltage of 2.5V. One end of pin 1 of the digital-to-analog converter chip is connected to the power supply voltage of 5V and one end of capacitor C4. The other end of capacitor C4 and pin 8 of the digital-to-analog converter chip are grounded. Pin 4 of the digital-to-analog converter chip is connected to the PWM control loop.

[0014] Furthermore, the PWM control loop includes an IGBT driver, resistors R5, R6, R7, R8, R9, R10, operational amplifier U4A, and transistor Q1;

[0015] Input terminal 1 of the IGBT driver is connected to the other end of resistor R3 in the MCU control circuit, input terminal 2 of the IGBT driver is connected to the other end of resistor R4 in the MCU control circuit, and the output terminal of the IGBT driver is connected to the charging and discharging circuit.

[0016] Pin 2 of op-amp U4A is connected to one end of resistor R7. The other end of resistor R7 is connected to one end of resistors R5 and R6 respectively. Pin 3 of op-amp U4A is connected to one end of resistors R9 and R10 respectively. The other end of resistor R5 is connected to the positive terminal U0+ of the capacitor under test. The other end of resistor R6 is grounded. The other end of resistor R9 is connected to pin 4 of the digital-to-analog converter chip. The other end of resistor R10 is connected to ground. Pin 6 of op-amp U4A is connected to resistor R8. The other end of resistor R8 is connected to the base of transistor Q1. The collector of transistor Q1 is connected to input terminal 2 of the IGBT driver. The emitter of transistor Q1 is grounded.

[0017] Furthermore, the charging / discharging circuit 2 includes IGBT1, IGBT2, charging resistor R1, and charging resistor R2; the output terminal 1 of the IGBT driver is connected to the gate G of IGBT1, the output terminal 2 of the IGBT driver is connected to the gate G of IGBT2, the positive terminal of the DC power supply output is connected to one end of the charging resistor R1, the negative terminal of the DC power supply output is connected to the negative terminal of the capacitor under test, the other end of the charging resistor R1 is connected to the source D of IGBT1, the drain S of IGBT1 is connected to the source D of IGBT2 and the positive terminal U0+ of the capacitor under test, respectively, the drain S of IGBT2 is connected to one end of the discharging resistor R2, and the other end of the discharging resistor R2 is connected to the negative terminal of the capacitor under test.

[0018] This invention uses an STM32F103RCT6 microcontroller to control and output two sets of PWM waveforms (pulse width and period can be set), which are then driven by an M57962 circuit to control the opening and closing of the IGBT, thereby realizing the cyclic control of charging and discharging of the capacitor under test.

[0019] Simultaneously, utilizing the principle of operational amplifier comparator, when the voltage across the capacitor under test is collected through resistor voltage division and is lower than the discharge voltage set by the microcontroller (STM32F103RCT6) through the digital-to-analog converter chip (DAC8532), transistor Q1 is turned on, pulling down the voltage of PWM22 and thus turning off IGBT2, stopping the capacitor under test from discharging, thereby realizing the control of the discharge voltage of the charging capacitor. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the principle of the utility model;

[0021] Figure 2 This is the circuit diagram of this utility model;

[0022] Figure 3 These are the PWM1 and PWM2 waveforms output by the microcontroller.

[0023] Figure 4 The PWM11 and PWM22 waveforms are for the input of the IGBT driver.

[0024] Figure 5 This is an analysis diagram of the actual output voltage waveform of the capacitor under test in this utility model. Detailed Implementation

[0025] like Figure 1 As shown, this utility model discloses a controllable voltage circuit for the charging and discharging cycle of a capacitor under test, specifically including a DC power supply 1, a charging and discharging circuit 2, a capacitor under test 3, a PWM control loop 4, and an MCU control circuit 5.

[0026] like Figure 2As shown, the MCU control circuit 5 includes a microcontroller 7 (STM32F103RCT6), a digital-to-analog converter chip 8 (DAC8532), an isolated RS-485 / RS-422 transceiver 9 (CA-IS3092W485), NOT gate U1A (CD4069), NOT gate U2B (CD4069), resistors R3 and R4, and capacitors C1, C2, and C4; the PWM control loop 4 includes an IGBT driver 10 (M57962), resistors R5, R6, R7, R8, R9, and R10, operational amplifier U4A (OP07), and transistor Q1; the charging / discharging loop 2 includes IGBT1, IGBT2, charging resistor R1, and charging resistor R2.

[0027] Output pin 1 of microcontroller 7 is connected to pin 1 of NOT gate U1A. Pin 2 of NOT gate U1A is connected to one end of resistor R3, and the other end of resistor R3 is connected to input pin 1 of IGBT driver 10. Output pin 2 of microcontroller 7 is connected to pin 3 of NOT gate U2B. Pin 4 of NOT gate U2B is connected to one end of resistor R4, and the other end of resistor R4 is connected to input pin 2 of IGBT driver 10. UART2_TX pin of microcontroller 7 is connected to pin 6 of isolated RS-485 / RS-422 transceiver. UART2_EN pin of microcontroller 7 is connected to pins 4 and 5 of isolated RS-485 / RS-422 transceiver. UART2_RX pin of microcontroller 7 is connected to isolated RS-485 / RS-422... Pin 3 of the transceiver is connected to pin 5 of the digital-to-analog converter chip 8 via pin CS8532D of microcontroller 7. Pin 7 of the microcontroller is connected to pin 7 of the digital-to-analog converter chip 8 via pin SPI2-MOSI. Pin 6 of the microcontroller 7 is connected to pin SPI2-SCLK of the microcontroller 7 via pin 6 of the digital-to-analog converter chip 8.

[0028] Pin 1 of the isolated RS-485 / RS-422 transceiver 9 is grounded via capacitor C1 and connected to a 3.3V DC power supply. Pins 2, 7, and 8 of the isolated RS-485 / RS-422 transceiver 9 are all grounded. Pins 9 and 15 of the isolated RS-485 / RS-422 transceiver 9 are connected in parallel. Pins 12 and 13 of the isolated RS-485 / RS-422 transceiver 9 are connected to the communication terminal of DC power supply 1. Capacitor C2 is connected in parallel between pins 15 and 16 of the isolated RS-485 / RS-422 transceiver 9.

[0029] Pin 2 of the digital-to-analog converter chip is connected to an external reference voltage of 2.5V. One end of pin 1 of the digital-to-analog converter chip is connected to the power supply voltage of 5V and one end of capacitor C4. The other end of capacitor C4 and pin 8 of the digital-to-analog converter chip are grounded.

[0030] Pin 2 of op-amp U4A is connected to one end of resistor R7. The other end of resistor R7 is connected to one end of resistors R5 and R6 respectively. Pin 3 of op-amp U4A is connected to one end of resistors R9 and R10 respectively. The other end of resistor R5 is connected to the positive terminal (U0+) of the capacitor under test. The other end of resistor R6 is grounded (the negative terminal of the capacitor under test). The other end of resistor R9 is connected to pin 4 of digital-to-analog converter chip 8. The other end of resistor R10 is connected to ground. Pin 6 of op-amp U4A is connected to resistor R8. The other end of resistor R8 is connected to the base of transistor Q1. The collector of transistor Q1 is connected to input terminal 2 of IGBT driver. The emitter of transistor Q1 is grounded.

[0031] The output terminal 1 of IGBT driver 10 is connected to the gate G of IGBT1, the output terminal 2 of IGBT driver 10 is connected to the gate G of IGBT2, the positive terminal of the output terminal of DC power supply 1 is connected to one end of charging resistor R1, the negative terminal of the output terminal of DC power supply 1 is connected to the negative terminal (ground) of the capacitor under test, the other end of charging resistor R1 is connected to the source D of IGBT1, the drain S of IGBT1 is connected to the source D of IGBT2 and the positive terminal (U0+) of the capacitor under test 3 respectively, the drain (S) of IGBT2 is connected to one end of discharge resistor R2, and the other end of discharge resistor R2 is connected to the negative terminal (ground) of the capacitor under test 3.

[0032] First, two sets of PWM1 and PWM2 waveforms with adjustable pulse width and period and opposite waveforms are generated through the output terminals 1 and 2 of the microcontroller 7 (e.g., ...). Figure 3 Furthermore, the high and low levels output by outputs 1 and 2 of microcontroller 7 are reversed. After passing through NOT gates U1A and U2B, the voltage is inverted, increasing the drive voltage and current, and generating PWM11 and PWM22 waveforms (e.g., Figure 4 (As shown).

[0033] When output terminal 1 of microcontroller 7 is low, it is inverted by NOT gate U1A to become high. This signal is then amplified and isolated by IGBT driver 10, turning on IGBT 1, and the capacitor under test 3 is in a charging state. When output terminal 2 of microcontroller 7 is low, it is inverted by NOT gate U2B to become high. This signal is then amplified and isolated by IGBT driver 10, turning on IGBT 2, and the capacitor under test 3 is in a discharging state. By cycling through the high and low levels output from output terminals 1 and 2 of microcontroller 7, and by setting the pulse width and duration of PWM1 and PWM2 waveforms, the charging and discharging cycle of the capacitor under test can be achieved. Figure 5 This is an analysis diagram of the actual output voltage waveform of the capacitor under test in this utility model.

[0034] When the capacitor under test 3 is in the discharge state, the output terminal 2 of the IGBT driver 10 is at a high level. The sampling voltage U- (voltage divider of resistors R5 and R6) across the capacitor under test 3 is compared with the set voltage U+ (set by the microcontroller program) generated by the digital-to-analog converter chip 8. Using the principle of operational amplifier U4A, when voltage U- < voltage U+ at time t1 (t2, t3, ...), operational amplifier U4 outputs a high level, transistor Q1 is turned on, and the output terminal 2 of the IGBT driver changes from a high level to a low level. Then IGBT2 is turned off, and the capacitor under test stops discharging.

[0035] When the capacitor under test 3 is in the charging state, regardless of whether the op-amp U4 outputs a high level or a low level, the output terminal 2 of the IGBT driver 10 is always low, and IGBT2 will not be turned on, which will not affect its normal operation. Figure 4 (As shown).

Claims

1. A voltage controllable circuit for charge-discharge cycle of a measured capacitance, characterized by: The direct current power supply, the charge-discharge circuit, the measured capacitor, the PWM control loop and the MCU control circuit are connected in series. The MCU control circuit is connected with the PWM control loop and the direct current power supply, the direct current power supply is connected with the charge-discharge circuit, the charge-discharge circuit is connected with the measured capacitor, and the PWM control circuit is connected with the charge-discharge circuit and the measured capacitor. The MCU control circuit is used for controlling the charge-discharge circuit through the PWM control loop to realize the cycle control of the charging and discharging of the measured capacitor, and is also used for controlling the discharging voltage of the measured capacitor and the output voltage of the direct current power supply.

2. The voltage controllable circuit for charge and discharge cycle of a measured capacitance according to claim 1, wherein: The MCU control circuit comprises a single-chip microcomputer, a digital-analog conversion chip, an isolated RS-485 / RS-422 transceiver, a NOT gate U1A, a NOT gate U2B, resistors R3 and R4, and capacitors C1, C2 and C4. The output end 1 of the single-chip microcomputer is connected with the pin 1 of the NOT gate U1A, the pin 2 of the NOT gate U1A is connected with one end of the resistor R3, the output end 2 of the single-chip microcomputer is connected with the pin 3 of the NOT gate U2B, the pin 4 of the NOT gate U2B is connected with one end of the resistor R4, and the other ends of the resistors R3 and R4 are connected with the PWM control loop. The pin UART2_TX of the single-chip microcomputer is connected with the pin 6 of the isolated RS-485 / RS-422 transceiver, the pin UART2_EN of the single-chip microcomputer is connected with the pins 4 and 5 of the isolated RS-485 / RS-422 transceiver, the pin UART2_RX of the single-chip microcomputer is connected with the pin 3 of the isolated RS-485 / RS-422 transceiver, the pin CS8532D of the single-chip microcomputer is connected with the pin 5 of the digital-analog conversion chip, the pin SPI2-MOSI of the single-chip microcomputer is connected with the pin 7 of the digital-analog conversion chip, and the pin SPI2-SCLK of the single-chip microcomputer is connected with the pin 6 of the digital-analog conversion chip. The pin 1 of the isolated RS-485 / RS-422 transceiver is grounded through the capacitor C1 and connected with a 3.3V direct current power supply, the pins 2, 7 and 8 of the isolated RS-485 / RS-422 transceiver are grounded, the pins 9 and 15 of the isolated RS-485 / RS-422 transceiver are connected in parallel, the pins 12 and 13 of the isolated RS-485 / RS-422 transceiver are connected with the communication end of the direct current power supply in communication, and the capacitor C2 is connected in parallel between the pins 15 and 16 of the isolated RS-485 / RS-422 transceiver. The pin 2 of the digital-analog conversion chip is connected with an external reference voltage 2.5V, one end of the pin 1 of the digital-analog conversion chip is connected with a power supply voltage 5V and one end of the capacitor C4, the other end of the capacitor C4 and the pin 8 of the digital-analog conversion chip are grounded, and the pin 4 of the digital-analog conversion chip is connected with the PWM control loop.

3. The voltage-controllable circuit for charge-discharge cycle of a measured capacitance according to claim 2, wherein: The PWM control loop comprises an igbt driver, resistors R5, R6, R7, R8 and R9, a operational amplifier U4A and a triode Q1. The input end 1 of the igbt driver is connected with the other end of the resistor R3 in the MCU control circuit, the input end 2 of the igbt driver is connected with the other end of the resistor R4 in the MCU control circuit, and the output end of the igbt driver is connected with the charge-discharge circuit. One end of the 2-pin of the operational amplifier U4A is connected to the resistance R7, the other end of the resistance R7 is connected to one end of the resistance R5 and R6 respectively, the 3-pin of the operational amplifier U4 is connected to one end of the resistance R9 and R10 respectively, the other end of the resistance R5 is connected to the positive terminal U0+ of the measured capacitor, the other end of the resistance R6 is grounded, the other end of the resistance R9 is connected to the 4-pin of the digital-analog conversion chip, the other end of the resistance R10 is connected to the ground, the 6-pin of the operational amplifier U4 is connected to the resistance R8, the other end of the resistance R8 is connected to the base of the triode Q1, the collector of the triode Q1 is connected to the input terminal 2 of the igbt driver, the emitter of the triode Q1 is grounded.

4. The voltage controllable circuit for charge and discharge cycle of a measured capacitance according to claim 3, wherein: The charge-discharge circuit 2 includes IGBT1, IGBT2, charging resistance R1, charging resistance R2; the output terminal 1 of the igbt driver is connected to the gate G of IGBT1, the output terminal 2 of the igbt driver is connected to the gate G of IGBT2, the positive terminal of the DC power supply output is connected to one end of the charging resistance R1, the negative terminal of the DC power supply output is connected to the negative terminal of the measured capacitor, the other end of the charging resistance R1 is connected to the source D of IGBT1, the drain S of IGBT1 is connected to the source D of IGBT2 and the positive terminal U0+ of the measured capacitor respectively, the drain S of IGBT2 is connected to one end of the discharge resistance R2, the other end of the discharge resistance R2 is connected to the negative terminal of the measured capacitor.

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