Chip packaging structure and radio frequency module with same
By forming a stable cavity structure around the RF filter chip and using 3D printing technology and a dam design with polymer thermosetting epoxy material, the high material cost, poor heat resistance and reliability risks of existing packaging solutions are solved, achieving higher packaging reliability and precision.
Patent Information
- Application Number
- CN202520168912.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-23
AI Technical Summary
Existing RF filter chip packaging solutions suffer from high material costs, poor heat resistance, poor workability, and reliability risks, especially the reliability issues caused by insufficient metal bump support.
A dam design is adopted, and a stable cavity structure is formed around the filter chip through 3D printing process. High-polymer thermosetting epoxy material is used as the dam to ensure that the cavity structure under the filter chip is not damaged, combined with plastic encapsulation.
It reduces material costs, improves packaging reliability and heat resistance, enhances the chip's stress resistance, avoids metal bump cracks, and improves packaging stability and precision.
Smart Images

Figure CN223772024U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a chip packaging structure, and particularly relates to a radio frequency filter chip packaging structure and a radio frequency module with the same. BACKGROUND
[0002] Radio frequency filters are used to attenuate high frequency interference signals generated by high frequency electronic devices. With the increase of the working frequency of electronic devices, the frequency of electromagnetic interference is also increasing, and the interference frequency usually reaches several hundred MHz or even GHz. Such high frequency interference signals cause serious radiation interference problems.
[0003] One type of radio frequency filter is a surface acoustic wave (SAW) filter. SAW filters have been widely used in wireless communication systems to filter out signals outside a specific frequency. SAW filters have the characteristics of small size and high performance.
[0004] The working principle of a SAW filter is that sound waves are transmitted on the surface of an interdigital transducer (IDT) of the SAW filter. Therefore, a cavity structure must be ensured on the surface of the IDT, otherwise the transmission of sound waves will be affected, and the performance of the product will be affected. Therefore, the packaging of SAW filters has special requirements.
[0005] The conventional filter radio frequency module in the industry currently uses a black film covered packaging scheme. After the chip is surface mounted, it is directly formed into a full-cavity structure at the bottom of the filter chip and the non-filter chip by the film pasting method, and finally the packaging is completed by marking and cutting.
[0006] The chip packaging scheme of the existing black film covered packaging has the following disadvantages:
[0007] 1. High material cost;
[0008] 2. Poor material heat resistance, poor workability during rework in the mounting and use stage;
[0009] 3. Less metal bump support for the full-cavity structure, with a reliability risk. Utility model content
[0010] The dam design of the utility model forms a stable cavity structure for the filter chip, and the dam area is large and has strong stress bearing capacity, which can effectively solve the problem of metal bump cracking after the reliability test of the current filter chip.
[0011] In the radio frequency module packaging structure according to the utility model, a cavity is formed at the bottom of the filter chip, and the bottom of the non-filter chip is completely filled with plastic sealing material.
[0012] The dam according to the utility model is formed by a three-dimensional printing process.
[0013] One aspect of the present application provides a chip packaging structure, comprising: a substrate, a solder resist layer is disposed on the substrate, the solder resist layer has a plurality of solder resist openings for soldering; a chip, disposed on the substrate, and comprising a filter chip with a plurality of bumps, wherein the plurality of bumps are attached to the substrate through the solder resist openings; a dam, disposed around the filter chip; and a plastic encapsulation layer, formed on the substrate, for encapsulating the exposed solder resist layer, the chip, and the dam on the substrate, wherein the dam is disposed on the solder resist layer at the edge of the filter chip, and the width of the dam gradually decreases from the solder resist layer upward, wherein the dam, the solder resist layer at the edge of the filter chip, and the substrate below the filter chip form a cavity structure below the filter chip.
[0014] According to one aspect of the present application, the side surface of the solder resist layer at the edge of the filter chip is aligned with the interface between the dam and the filter chip in the vertical direction.
[0015] According to one aspect of the present application, the upper surface of the solder resist layer at the edge of the filter chip overlaps with the lower surface of the edge of the filter chip in the horizontal direction.
[0016] According to one aspect of the present application, a solder resist layer is disposed on the substrate between the plurality of bumps of the filter chip.
[0017] According to one aspect of the present application, a resonator is disposed on the filter chip between the plurality of bumps, and the resonator is opposite to the solder resist layer between the plurality of bumps.
[0018] According to one aspect of the present application, the chip further comprises a non-filter chip with a plurality of bumps, the plurality of bumps of the non-filter chip are attached to the substrate through the solder resist openings, and the non-filter chip is also encapsulated in the plastic encapsulation layer.
[0019] According to one aspect of the present application, the space below the non-filter chip is filled with plastic encapsulation material.
[0020] According to one aspect of the present application, the dam is formed by a three-dimensional printing process.
[0021] According to one aspect of the present application, the height of the dam is 100 microns, and the width of the dam is 30 microns.
[0022] According to one aspect of the present application, the material of the dam is a high-molecular thermosetting epoxy adhesive material.
[0023] Another aspect of the present application provides a radio frequency module having the chip packaging structure according to various embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 is a schematic diagram showing a design of a chip and a substrate according to the chip and substrate design concept of the present application.
[0025] Figure 2 is a schematic diagram showing a chip packaging structure according to a first embodiment of the present application.
[0026] Figure 3 is a schematic diagram showing a chip packaging structure according to a second embodiment of the present application.
[0027] Figure 4 is a flowchart showing a chip packaging process according to the chip and substrate design concept of the present application. DETAILED DESCRIPTION
[0028] Before undertaking the detailed description below, it can be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” “connect” and their derivatives refer to any direct or indirect communication or interaction between two or more elements, whether or not those elements are in physical contact with one another. The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompass both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and / or. The phrase “associated with,” as well as derivatives thereof, means to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, be proximate to, be bound to or with, have a property of, have relations with, or the like. The term “controller” means any device, system or part thereof that controls at least one operation. Such a controller can be implemented in hardware or any combination of hardware and software and / or firmware. The functionality associated with any particular controller can be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items can be used and only one item from the list can be needed. For example, “at least one of A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.
[0029] Definitions for other certain words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.
[0030] In this patent document, the application combination of modules and the division level of sub-modules are only for illustration, and the application combination of modules and the division level of sub-modules can have different manners without departing from the scope of the present disclosure.
[0031] Figure 1 This is a schematic diagram illustrating the design of a filter chip, a non-filter chip, and a substrate according to the present invention. Figure 2 This is a schematic diagram showing the chip packaging structure according to the first embodiment of the present invention. Figure 3 This is a schematic diagram illustrating a chip packaging structure according to a second embodiment of the present invention. The following references... Figures 1 to 3 This describes the chip packaging structure conceived according to the present invention.
[0032] like Figures 1 to 3 As shown, a solder resist layer with multiple solder resist openings is deposited on a substrate. The chip includes a filter chip and a non-filter chip, each with multiple bumps for soldering. The chip is flip-chip mounted onto the substrate via the multiple solder resist openings using a surface mount method. A dam is formed around the filter chip to ensure that the bottom of the filter has a cavity structure. A molding compound is formed on the substrate to encapsulate the exposed solder resist layer, chip, and dam on the substrate.
[0033] like Figure 2 and Figure 3 As shown, the dam is disposed on the solder mask layer at the edge of the filter chip, and the width of the dam gradually decreases upwards from the solder mask layer. Furthermore, the dam, the solder mask layer at the edge of the filter chip, and the substrate below the filter form a cavity structure beneath the filter. This top-narrow, bottom-wide structure of the dam makes its bottom more stable and able to withstand greater pressure, thereby ensuring that the cavity structure beneath the filter chip is not damaged. During molding, this dam structure effectively prevents plastic from flowing into the cavity structure beneath the filter chip, thus ensuring the performance of the filter chip. According to one embodiment of the present invention, the dam is formed by a 3D printing process. Compared with dispensing, 3D printing has lower cost, higher accuracy, and higher forming efficiency. According to one embodiment of the present invention, the dam has a height of approximately 100 micrometers and a width of approximately 30 micrometers. According to one embodiment of the present invention, the dam is made of a high-molecular-weight thermosetting epoxy resin.
[0034] like Figure 2 As shown, according to the first embodiment of this utility model, the side of the solder mask layer at the edge of the filter chip is aligned vertically with the interface between the dam and the filter chip. See also Figure 2 The dam is positioned close to the edge of the filter chip on the solder mask layer, and the solder mask layer does not extend below the filter chip, making the cavity structure below the filter chip large enough to ensure the performance of the filter chip.
[0035] Alternatively, such as Figure 3As shown, according to the second embodiment of this utility model, the upper surface of the solder resist layer at the edge of the filter chip overlaps with the lower surface of the edge of the filter chip in the horizontal direction. See also Figure 3 The dam is positioned close to the edge of the filter chip on the solder mask layer, and a portion of the solder mask layer extends below the filter chip. This makes the formation of the dam easier and the bond between the dam and the solder mask layer below the dam more stable, thereby ensuring that the cavity structure below the filter chip is not damaged.
[0036] like Figure 2 and Figure 3 As shown, a solder mask layer may be disposed on the substrate between multiple bumps of the filter chip, and a resonator may be disposed on the filter chip between the multiple bumps, with the resonator opposite to the solder mask layer between the multiple bumps.
[0037] like Figure 2 and Figure 3 As shown, the chip may further include a non-filter chip with multiple bumps, the bumps of which are mounted on the substrate through solder mask openings, and the non-filter chip is also encapsulated within a molding compound. The non-filter chip is filled with molding compound underneath.
[0038] The above is for reference only. Figures 1 to 3 The various implementation schemes of the described chip packaging structure can all be applied to the packaging structure of radio frequency modules.
[0039] Figure 4 This is a flowchart illustrating the chip packaging process according to the present invention.
[0040] The first step is to provide a substrate carrier (i.e., a substrate), and to provide at least one filter chip (e.g., a surface acoustic wave filter chip) and at least one non-filter chip.
[0041] The second step is to flip-mount the at least one filter chip and the at least one non-filter chip onto the substrate using a surface mount method.
[0042] The third step is to form a dam structure around the at least one filter chip using 3D printing to ensure that the bottom of the at least one filter chip is a cavity structure.
[0043] The fourth step involves a compression molding process, where molding compound is filled into the bottom of at least one non-filter chip. The bottom of the at least one filter chip remains empty due to a damming structure that prevents the molding compound from entering.
[0044] The fifth step involves laser marking and cutting processes to complete the chip packaging.
[0045] Based on the above references Figures 1 to 4 The description states that, after the filter and substrate are specially designed according to this invention, after the filter is soldered onto the substrate, a 3D printing method is used to surround the filter chip with a dam. This dam structure prevents external molding compound from entering the bottom of the filter, ensuring the cavity structure. The bottom of the non-filter chip can be filled with molding compound. This chip packaging solution replaces existing mainstream technologies such as integral film coating and wafer-level packaging.
[0046] This invention utilizes a 3D printing process to spray a damming material around a filter chip using a 3D printing station. The damming material is a high-polymer thermosetting epoxy adhesive. The process sequence is: lens alignment, printing, baking and curing, and visual inspection. The printing process involves the nozzle moving back and forth, layering adhesive to form the overall dam. The dam's height is approximately 100 micrometers, and its width is approximately 30 micrometers, offering significantly improved precision compared to conventional dispensing processes. The advantages of 3D printing include alignment accuracy within 1 micrometer, nozzle inner diameter that can be reduced to 20 micrometers, and linewidth accuracy that can be controlled within 5%. Applying 3D printing to semiconductor packaging processes greatly improves process precision.
[0047] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.
[0048] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined solely by the claims.
Claims
1. A chip package structure, characterized by The chip package structure comprises: a substrate on which a solder resist layer is disposed, the solder resist layer having a plurality of solder resist openings for soldering; a chip disposed on the substrate and comprising a filter chip with a plurality of bumps, wherein the plurality of bumps are mounted on the substrate through the solder resist openings; a dam disposed around the filter chip; and a plastic encapsulation layer formed on the substrate for encapsulating the exposed solder resist layer, the chip, and the dam on the substrate, wherein the dam is disposed on the solder resist layer at the edge of the filter chip, and the width of the dam gradually decreases from the solder resist layer upward, wherein the dam, the solder resist layer at the edge of the filter chip, and the substrate under the filter chip form a cavity structure under the filter chip.
2. The chip package structure of claim 1, wherein, the side surface of the solder resist layer at the edge of the filter chip is aligned with the interface between the dam and the filter chip in the vertical direction, or wherein the upper surface of the solder resist layer at the edge of the filter chip overlaps with the lower surface of the edge of the filter chip in the horizontal direction.
3. The chip package structure of claim 1 or 2, wherein, The solder resist layer is disposed on the substrate between the plurality of bumps of the filter chip.
4. The chip package structure of claim 3, wherein, A resonator is disposed on the filter chip between the plurality of bumps, the resonator being opposite to the solder resist layer between the plurality of bumps.
5. The chip package structure according to claim 1 or 2, wherein: wherein the chip further comprises a non-filter chip with a plurality of bumps, wherein the plurality of bumps of the non-filter chip are mounted on the substrate through the solder resist openings, wherein the non-filter chip is also encapsulated in the plastic encapsulation layer.
6. The chip package structure of claim 5, wherein, The space under the non-filter chip is filled with plastic encapsulation material.
7. The chip package structure of claim 1 or 2, wherein, The dam is formed by a three-dimensional printing process.
8. The chip package structure of claim 1 or 2, wherein, The dam has a height of 100 microns and a width of 30 microns.
9. The chip package structure as claimed in claim 1 or 2, characterized in that, The dam is made of a high-molecular thermosetting epoxy adhesive material.
10. A radio frequency module, characterized by The chip package structure according to any one of claims 1-9.