Common-drain double-MOSFET (metal oxide semiconductor field effect transistor) device
By placing MOSFET devices on the front and back sides of the wafer, the problems of large area, high impedance, and inflexible packaging in traditional designs are solved, enabling miniaturization and high-density integration of devices, reducing production costs, and improving packaging flexibility and applicability.
Patent Information
- Application Number
- CN202423222814.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2034-12-25
AI Technical Summary
Traditional common-drain dual MOSFET wafer designs suffer from problems such as large area, high impedance, and inflexible packaging, which limit their application in high-density integrated circuits and specific fields.
A novel common-drain dual MOSFET device is designed, with two MOSFETs placed on the front and back sides of the wafer, respectively. The device layout is optimized by using trench and contact hole structures to reduce the device size, and conductive metal materials are used for connection.
This reduces device area, lowers production costs, reduces soldering area, provides more possibilities for high-density integrated circuit design, and improves device packaging flexibility and applicability.
Smart Images
Figure CN223772423U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application belong to the field of semiconductor technology, and in particular relate to a common-drain dual MOSFET device. Background Technology
[0002] In the semiconductor field, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) wafers are the foundation for manufacturing various electronic devices. Common-drain dual-MOSFET wafers, as a special product, are often used in input / output protection and other applications.
[0003] Traditional common-drain dual MOSFET wafers have some limitations in design and manufacturing.
[0004] In terms of area, existing common-drain dual-MOSFET wafer designs are often bulky and occupy a large space, which not only increases production costs but also limits their application in high-density integrated circuits. Regarding impedance, higher impedance leads to increased energy loss, affecting device performance and efficiency. In terms of packageability, existing structures and designs are not flexible enough to meet diverse packaging requirements, especially in industrial and automotive applications with high packaging demands.
[0005] These issues severely limit the widespread application of common-drain dual-MOSFET wafers in modern electronic devices, posing challenges to related products in terms of performance, cost, and applicability. Therefore, a novel design is urgently needed to overcome these shortcomings. Summary of the Invention
[0006] In order to solve or alleviate the technical problems existing in the prior art, this application provides a common-drain dual MOSFET device.
[0007] This application provides a novel common-drain dual MOSFET device, comprising: a wafer;
[0008] The front side of the wafer is provided with a plurality of spaced first trenches, and the back side of the wafer is provided with second trenches that correspond one-to-one with the plurality of first trenches.
[0009] Both the first trench and the second trench contain gate polysilicon.
[0010] The wafer has a well region and an implantation region on its front and back sides, respectively. The implantation region on the front side of the wafer is located within the well region on the front side of the wafer. A portion of the first trenches only penetrate the well region on the front side of the wafer, while another portion of the first trenches sequentially penetrate both the implantation region and the well region on the front side of the wafer. The implantation region on the back side of the wafer is located within the well region on the back side of the wafer. A portion of the second trenches only penetrate the well region on the back side of the wafer, while another portion of the second trenches sequentially penetrate both the implantation region and the well region on the back side of the wafer. The well regions on the front side and the well regions on the back side of the wafer are positioned correspondingly, and the implantation regions on the front side and the implantation regions on the back side of the wafer are positioned correspondingly.
[0011] A first contact hole and a second contact hole are respectively provided in a portion of the first trench on the front side of the wafer and a portion of the second trench on the back side of the wafer. A third contact hole is provided between another portion of the first trenches. The third contact hole extends through the dielectric layer and the implantation area on the front side of the wafer to the well area on the front side of the wafer. A fourth contact hole is provided between another portion of the second trenches. The fourth contact hole extends through the dielectric layer and the implantation area on the back side of the wafer to the well area on the back side of the wafer.
[0012] The first contact hole, the second contact hole, the third contact hole, and the fourth contact hole are all filled with conductive metal;
[0013] A first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are deposited on the upper surfaces of the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole, respectively. The first metal layer and the third metal layer are spaced apart, and the second metal layer and the fourth metal layer are spaced apart.
[0014] In a preferred embodiment of this application, the wafer includes a substrate and a first epitaxial layer disposed on the front side of the substrate and a second epitaxial layer disposed on the back side of the substrate.
[0015] In a preferred embodiment of this application, the substrate, the first epitaxial layer, and the second epitaxial layer have the same doping type, and both are of the first doping type.
[0016] In a preferred embodiment of this application, both the well region on the front side of the wafer and the well region on the back side of the wafer are of the second doping type, and both the implantation region on the front side of the wafer and the implantation region on the back side of the wafer are of the second doping type.
[0017] Compared with existing technologies, the common-drain dual-MOSFET device provided in this application places the two MOSFETs on the front and back sides of the wafer respectively, significantly reducing the wafer area and thus lowering production costs. The reduced area also reduces the soldering area on the PCB board, providing more possibilities for the design of high-density integrated circuits. Attached Figure Description
[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0019] Figure 1 A structural diagram of a common-drain dual MOSFET device provided in an embodiment of this application is shown. Detailed Implementation
[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0021] like Figure 1 As shown, this application provides a novel common-drain dual MOSFET device, comprising: a wafer;
[0022] The front side of the wafer is provided with a plurality of spaced first trenches, and the back side of the wafer is provided with second trenches that correspond one-to-one with the plurality of first trenches.
[0023] Both the first trench and the second trench are provided with gate polysilicon 05; in this application, gate oxide layer 04 is also provided on the sidewalls of the first trench and the second trench.
[0024] The wafer has a well region and an implantation region on its front and back sides, respectively. The implantation region 07 on the front side of the wafer is located in the well region 06 on the front side of the wafer. Part of the first trench only penetrates the well region 06 on the front side of the wafer, while another part of the first trench sequentially penetrates the implantation region 07 and the well region 06 on the front side of the wafer. The implantation region 09 on the back side of the wafer is located in the well region 08 on the back side of the wafer. Part of the second trench only penetrates the well region 08 on the back side of the wafer, while another part of the second trench sequentially penetrates the implantation region 09 and the well region 08 on the back side of the wafer. The well regions 06 on the front side of the wafer and the well regions 08 on the back side of the wafer are positioned correspondingly, and the implantation regions 07 on the front side of the wafer and the implantation region 09 on the back side of the wafer are positioned correspondingly.
[0025] A first contact hole 10 and a second contact hole 12 are respectively provided in a portion of the first trench on the front side of the wafer and a portion of the second trench on the back side of the wafer. A third contact hole 11 is provided between another portion of the first trenches. The third contact hole 11 extends through the dielectric layer 14 and the implantation region 07 on the front side of the wafer to the well region 06 on the front side of the wafer. A fourth contact hole 13 is provided between another portion of the second trenches. The fourth contact hole 13 extends through the dielectric layer 15 and the implantation region 09 on the back side of the wafer to the well region 08 on the back side of the wafer.
[0026] The first contact hole 10, the second contact hole 12, the third contact hole 11 and the fourth contact hole 13 are all filled with conductive metal;
[0027] A first metal layer 16, a second metal layer 18, a third metal layer 17, and a fourth metal layer 19 are deposited on the upper surfaces of the first contact hole 10, the second contact hole 12, the third contact hole 11, and the fourth contact hole 13, respectively. The first metal layer 16 and the third metal layer 17 are spaced apart, and the second metal layer 18 and the fourth metal layer 19 are spaced apart.
[0028] In this embodiment of the application, the wafer includes a substrate 01, a first epitaxial layer 02 disposed on the front side of the substrate 01, and a second epitaxial layer 03 disposed on the back side of the substrate 01.
[0029] More preferably, the substrate 01, the first epitaxial layer 02 and the second epitaxial layer 03 have the same doping type, and both are of the first doping type.
[0030] In a preferred embodiment of this application, the well region 06 on the front side of the wafer and the well region 08 on the back side of the wafer are both of the second doping type, and the implantation region 07 on the front side of the wafer and the implantation region 09 on the back side of the wafer are both of the first doping type. Specifically, the second doping type is P-type, and the first doping type is N-type.
[0031] In addition, conductive metal 20, conductive metal 21, conductive metal 22 and conductive metal 23 need to be filled in the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 respectively in order to lead out the corresponding electrodes. In this application, the conductive metal is copper.
[0032] A first metal layer 24, a second metal layer 26, a third metal layer 25, and a fourth metal layer 27 are deposited on the upper surfaces of the first contact hole 16, the second contact hole 18, the third contact hole 17, and the fourth contact hole 19, respectively. The first metal layer 24 and the third metal layer 25 are spaced apart, and the second metal layer 26 and the fourth metal layer 27 are spaced apart. The gate electrode is led out through the first metal layer 24 and the second metal layer 26, and the source electrode is led out through the third metal layer 25 and the fourth metal layer 27.
[0033] The common-drain dual-MOSFET device provided in this application places the two MOSFETs on the front and back sides of the wafer, respectively, significantly reducing the wafer area and thus lowering production costs. The reduced area also leads to a corresponding reduction in the soldering area on the PCB, providing more possibilities for the design of high-density integrated circuits.
[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A common-drain dual MOSFET device, characterized by, The wafer comprises: a wafer; a plurality of spaced first grooves are arranged on the front surface of the wafer, and a plurality of second grooves corresponding to the first grooves are arranged on the back surface of the wafer; gate polysilicon is arranged in the first grooves and the second grooves; a well region and an implanted region are arranged on the front surface and the back surface of the wafer respectively, the implanted region on the front surface is arranged in the well region on the front surface, part of the first grooves only penetrate the well region on the front surface, and the other part of the first grooves penetrate the implanted region on the front surface and the well region on the front surface in sequence; the implanted region on the back surface is arranged in the well region on the back surface, part of the second grooves only penetrate the well region on the back surface, and the other part of the second grooves penetrate the implanted region on the back surface and the well region on the back surface in sequence; and the well region on the front surface and the well region on the back surface are arranged in position, and the implanted region on the front surface and the implanted region on the back surface are arranged in position; first contact holes and second contact holes are arranged in part of the first grooves on the front surface and part of the second grooves on the back surface respectively, third contact holes are arranged between the other part of the first grooves, the third contact holes extend to the well region on the front surface through the dielectric layer and the implanted region on the front surface, and fourth contact holes are arranged between the other part of the second grooves, the fourth contact holes extend to the well region on the back surface through the dielectric layer and the implanted region on the back surface; conductive metal is filled in the first contact holes, the second contact holes, the third contact holes and the fourth contact holes; first metal layers, second metal layers, third metal layers and fourth metal layers are deposited on the upper surfaces of the first contact holes, the second contact holes, the third contact holes and the fourth contact holes respectively, the first metal layers and the third metal layers are arranged in position, and the second metal layers and the fourth metal layers are arranged in position.
2. A common-drain double MOSFET device as claimed in claim 1, characterized in that, The wafer comprises a substrate, a first epitaxial layer arranged on the front surface of the substrate, and a second epitaxial layer arranged on the back surface of the substrate.
3. A common-drain double MOSFET device as claimed in claim 2, characterized in that The substrate, the first epitaxial layer and the second epitaxial layer have the same doping type, which is a first doping type.
4. A common-drain double MOSFET device as defined in claim 1, wherein, The well region on the front surface of the wafer and the well region on the back surface of the wafer are of a second doping type, and the implanted region on the front surface of the wafer and the implanted region on the back surface of the wafer are of the second doping type.