Semiconductor structure
By designing a connection structure in the semiconductor structure to electrically connect with the pixel structure, metal etching is avoided, the problem of debris splashing during the etching process of micro LED AR chips is solved, the product yield is improved and the process requirements are reduced.
Patent Information
- Application Number
- CN202520023155.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-06
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-06
AI Technical Summary
During the etching process of individual pixels in a micro LED AR chip, metal etching causes debris to fly out, damaging the chip and resulting in a low product yield.
Design a semiconductor structure in which the first electrode and the pixel structure are electrically connected through a connection structure. The area of the projection pattern of the connection structure on the passivation layer is smaller than the bottom area of the pixel structure to avoid etching the metal. The connection structure is formed first, and then the passivation layer and the first electrode are bonded.
This avoids the splashing of debris during metal etching, improves product yield, and reduces process requirements.
Smart Images
Figure CN223772443U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor design, and more particularly to a semiconductor structure. Background Technology
[0002] With the rapid development of AR micro-displays, the size of micro-LED AR chips is constantly shrinking, making traditional bump-to-bump bonding methods insufficient for precision requirements. Therefore, current micro-LED AR chip manufacturing generally employs a method of bonding first, then peeling off the substrate, and finally etching individual pixels into the micro-LED AR chip. However, etching individual pixels requires etching the metal bonding layer. Dry etching of metal can cause debris to fly off, damaging the micro-LED AR chip and resulting in low product yield. Utility Model Content
[0003] This invention provides a semiconductor structure that solves the problem in the prior art where debris generated during the etching of the metal bonding layer during pixel separation damages the micro LED AR chip.
[0004] To solve the above-mentioned technical problems, this utility model provides a semiconductor structure, comprising:
[0005] substrate;
[0006] A plurality of first electrodes are spaced apart on the substrate;
[0007] An insulating layer is located on the substrate, and the first electrode is located within and penetrates the insulating layer.
[0008] A passivation layer is located on the first electrode and the insulating layer;
[0009] A plurality of pixel structures spaced apart, the pixel structures being located on the passivation layer;
[0010] A plurality of spaced connection structures are provided, the connection structures being located within and penetrating the passivation layer, the first electrode and the pixel structure being electrically connected through at least one of the connection structures, the passivation layer and the connection structures being bonded to the insulating layer and the first electrode, and the area of the projection pattern of the connection structure on the passivation layer being smaller than the bottom surface area of the pixel structure.
[0011] Optionally, it further includes: a second electrode, the second electrode being located on the substrate, the second electrode being located outside the insulating layer and surrounding three sides of the insulating layer.
[0012] Optionally, the connection structure includes a metal reflective layer and a metal bonding layer. A first side of the metal reflective layer is connected to the pixel structure, a second side of the metal reflective layer is connected to the first side of the metal bonding layer, and the second side of the metal bonding layer is bonded to the first electrode or insulating layer.
[0013] Optionally, both the first electrode and the connection structure are convex structures.
[0014] Optionally, the diameter of the projected pattern of the first electrode on the insulating layer is larger than the diameter of the projected pattern of the connection structure on the passivation layer.
[0015] Optionally, the diameter of the projection pattern of the first electrode on the insulating layer is greater than twice the distance between the center points of the plurality of connection structures.
[0016] Optionally, the distance between the first electrodes is greater than the distance between the center points of the plurality of connection structures.
[0017] Optionally, the plurality of first electrodes are arranged in an array, and the plurality of connection structures are arranged in a complementary array.
[0018] Optionally, the pixel structure includes:
[0019] A transparent conductive layer is located on the passivation layer;
[0020] A P-type semiconductor layer is located on the transparent conductive layer;
[0021] A light-emitting layer, wherein the light-emitting layer is located on the P-type semiconductor layer;
[0022] An N-type semiconductor layer is located on the light-emitting layer.
[0023] Optionally, the first electrode is a P-type electrode and the second electrode is an N-type electrode.
[0024] Compared with the prior art, the present invention has the following beneficial effects:
[0025] In the semiconductor structure provided by this invention, the first electrode and the pixel structure are electrically connected through at least one connection structure. The area of the projection pattern of the connection structure on the passivation layer is smaller than the bottom area of the pixel structure. That is, during the formation of the semiconductor structure, several spaced-apart step-by-step connection structures are first formed, and then the passivation layer is bonded to the first electrode and the insulating layer, ensuring that the first electrode and the pixel structure are electrically connected through at least one connection structure. Therefore, when etching the pixel structure to separate the pixels, it is not necessary to etch the metal, thus avoiding debris splashing during metal etching, making the pixel structure less susceptible to damage, and thereby improving product yield.
[0026] Furthermore, since the diameter of the projected pattern of the first electrode on the insulating layer is larger than the diameter of the projected pattern of the connecting structure on the passivation layer, and the diameter of the projected pattern of the first electrode on the insulating layer is greater than twice the distance between the center points of the plurality of connecting structures, and the distance between the first electrodes is greater than the distance between the center points of the plurality of connecting structures, the arrangement density of the connecting structures is greater than the arrangement density of the first electrodes. This allows each first electrode to be electrically connected to at least one connecting structure. In other words, the first electrode does not need to be perfectly aligned one-to-one with the connecting structure, thereby reducing process requirements while ensuring product yield. Attached Figure Description
[0027] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure according to an embodiment of the present invention;
[0028] Figure 2 and Figure 3 yes Figure 1 Top view.
[0029] Figure label:
[0030] 1-Substrate;
[0031] 2-Insulating layer;
[0032] 3-First electrode;
[0033] 4-Passivation layer;
[0034] 5-Connection structure;
[0035] 501 - Metal bonding layer;
[0036] 502 - Metallic reflective layer;
[0037] 6-pixel structure;
[0038] 601 - Transparent conductive layer;
[0039] 602-P type semiconductor layer;
[0040] 603 - Emissive layer;
[0041] 604-N type semiconductor layer;
[0042] 7-Second Electrode
[0043] D1 - The diameter of the projected pattern of the connection structure on the passivation layer;
[0044] D2 - The diameter of the projection pattern of the first electrode on the insulating layer. Detailed Implementation
[0045] The embodiments of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model. The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0046] As described in the background art, in the process of etching individual pixels into a micro LED AR chip, it is necessary to etch the metal bonding layer. However, etching the metal will generate debris that can easily damage the micro LED AR chip, resulting in a low product yield.
[0047] In view of the above, the present invention creatively provides a semiconductor structure, comprising:
[0048] substrate;
[0049] A plurality of first electrodes are spaced apart on the substrate;
[0050] An insulating layer is located on the substrate, and the first electrode is located within and penetrates the insulating layer.
[0051] A passivation layer is located on the first electrode and the insulating layer;
[0052] A plurality of pixel structures spaced apart, the pixel structures being located on the passivation layer;
[0053] A plurality of spaced connection structures are provided, the connection structures being located within and penetrating the passivation layer, the first electrode and the pixel structure being electrically connected through at least one of the connection structures, the passivation layer and the connection structures being bonded to the insulating layer and the first electrode, and the area of the projection pattern of the connection structure on the passivation layer being smaller than the bottom surface area of the pixel structure.
[0054] Using this semiconductor structure eliminates the need for metal etching when separating pixels by etching the pixel structure, thus avoiding debris splashing during metal etching, making the pixel structure less susceptible to damage, and thereby improving product yield.
[0055] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.
[0056] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure according to an embodiment of the present invention. Figure 2 and Figure 3 yes Figure 1 A top view. It should be noted that, for ease of understanding, Figure 2 The substrate 1, the first electrode 3, the second electrode 7, and the insulating layer 2 are shown only schematically. Figure 3 The passivation layer 4 and the connection structure 5 are shown only schematically.
[0057] Please refer to Figure 1 The semiconductor structure includes: a substrate 1, a plurality of first electrodes 3, an insulating layer 2, a passivation layer 4, a plurality of pixel structures 6, and a plurality of connection structures 5.
[0058] The substrate 1 is a semiconductor material. For example, the substrate 1 can be a complementary metal oxide semiconductor substrate. Of course, there are many other types of substrate 1 to choose from, and this utility model does not limit them.
[0059] The plurality of first electrodes 3 and the insulating layer 2 are all located on the substrate 1. The first electrodes 3 are spaced apart in the insulating layer 2 and penetrate the insulating layer 2.
[0060] The passivation layer 4 is located on the first electrode 3 and the insulating layer 2.
[0061] The pixel structures 6 are spaced out on the passivation layer 4.
[0062] The connection structure 5 is located within and penetrates the passivation layer 4. The first electrode 3 and the pixel structure 6 are electrically connected through at least one of the connection structures 5. The passivation layer 4 and the connection structure 5 are bonded to the insulating layer 2 and the first electrode 3. Furthermore, the area of the projection pattern of the connection structure 5 on the passivation layer is smaller than the bottom area of the pixel structure 6.
[0063] In this embodiment, both the first electrode 3 and the connecting structure 5 are convex structures. The convex structure can be, for example, spherical, cylindrical, etc. Of course, there are many other choices for the convex structure, and those skilled in the art can choose according to the actual situation. This utility model does not limit this choice.
[0064] Specifically, after the connecting structure 5 is bonded to the two protrusion structures of the first electrode 3, the protrusion structures will undergo plastic deformation, so that the connecting structure 5 and the first electrode 3 are in close contact to form a firmly integrated conductive structure.
[0065] In this embodiment, please refer to Figure 2 as well as Figure 3 The diameter D2 of the projection pattern of the first electrode 3 on the insulating layer is greater than the diameter D1 of the projection pattern of the connection structure 5 on the passivation layer, and the diameter D2 of the projection pattern of the first electrode 3 on the insulating layer is greater than twice the distance between the center points of the plurality of connection structures 5.
[0066] Specifically, the diameter D2 of the projection pattern of the first electrode 3 on the insulating layer is larger than the diameter D1 of the projection pattern of the connecting structure 5 on the passivation layer, so that the first electrode 3 can be connected to at least one connecting structure 5. In addition, the diameter D2 of the projection pattern of the first electrode 3 on the insulating layer is greater than twice the distance between the center points of the plurality of connecting structures 5, which further ensures that the first electrode 3 can be connected to at least one of the connecting structures 5, thereby ensuring sufficient electrical connection and bonding strength between the first electrode 3 and the connecting structure 5.
[0067] Furthermore, the diameter D2 of the projection pattern of the first electrode 3 on the insulating layer is larger than the diameter D1 of the projection pattern of the connecting structure 5 on the passivation layer. This also means that when the areas of the passivation layer 4 and the insulating layer 2 are the same, the arrangement density of the first electrode 3 is less than the arrangement density of the connecting structure 5. As a result, the first electrode 3 and the connecting structure 5 do not need to be perfectly aligned one-to-one to achieve electrical connection between the first electrode 3 and the connecting structure 5, thereby reducing process requirements while ensuring product yield.
[0068] In this embodiment, please refer to Figure 2 as well as Figure 3 The distance between the first electrodes 3 is greater than the distance between the center points of the plurality of connection structures 5, so that when isolating pixels, sufficient isolation distance is ensured between pixels.
[0069] In this embodiment, please refer to Figure 2 as well as Figure 3 The plurality of first electrodes 3 are arranged in an array, and the plurality of connecting structures 5 are arranged in a complementary array. Of course, there are many other ways in which the first electrodes 3 and the connecting structures 5 can be arranged, and this utility model does not limit this.
[0070] In this embodiment, please continue to refer to Figure 1 The connection structure 5 includes a metal reflective layer 502 and a metal bonding layer 501.
[0071] Specifically, the first surface of the metal reflective layer 502 is connected to the pixel structure 6, the second surface of the metal reflective layer 502 is connected to the first surface of the metal bonding layer 501, and the second surface of the metal bonding layer 501 is bonded to the first electrode 3 or the insulating layer 2.
[0072] Specifically, the connection structure 5 connects the first electrode 3 and the pixel structure 6, enabling an electrical connection between the first electrode 3 and the pixel structure 6. The metal reflective layer 502 not only conducts electricity but also reflects the light generated by the pixel structure 6, allowing the light from the pixel structure 6 to exit from the top.
[0073] The metal reflective layer 502 can be made of silver, for example, and the metal bonding layer 501 can be made of a high-density metal material, such as tungsten. Of course, there are many other materials for the metal reflective layer 502 and the metal bonding layer 501, and this utility model does not limit them.
[0074] In this embodiment, please continue to refer to Figure 1 The pixel structure 6 includes: a transparent conductive layer 601, a P-type semiconductor layer 602, a light-emitting layer 603, and an N-type semiconductor layer 604.
[0075] Specifically, the transparent conductive layer 601 is located on the passivation layer 4, the P-type semiconductor layer 602 is located on the transparent conductive layer 601, the light-emitting layer 603 is located on the P-type semiconductor layer 602, and the N-type semiconductor layer 604 is located on the light-emitting layer 603.
[0076] The light-emitting layer 603 can be, for example, a multi-quantum well system, which is a system composed of multiple quantum wells. Of course, there are many other possible structures for the light-emitting layer 603, and this invention does not limit them.
[0077] The transparent conductive layer 601 can be made of, for example, indium tin oxide. Of course, there are many other materials that can be used for the transparent conductive layer 601, and this invention does not limit this to any particular material.
[0078] In this embodiment, the first electrode 3 is a P-type electrode, the second electrode 7 is an N-type electrode, and the materials of the P-type semiconductor layer 602 and the N-type semiconductor layer 604 are gallium nitride. Of course, there are many other materials that can be used for the P-type semiconductor layer 602 and the N-type semiconductor layer 604, and this invention does not limit this to any particular material.
[0079] Of course, there are many other options for the internal structure of the pixel structure 6, and this utility model does not limit them.
[0080] In one embodiment, please refer to Figure 1 as well as Figure 2 The semiconductor structure further includes a second electrode 7, which is located on the substrate 1 and is located outside the insulating layer 2 and surrounds three sides of the insulating layer 2.
[0081] In summary, in the semiconductor structure provided by this invention, the first electrode and the pixel structure are electrically connected through at least one connection structure. Furthermore, the projected area of the connection structure on the passivation layer is smaller than the bottom area of the pixel structure. That is, during the formation of the semiconductor structure, several spaced-apart step-by-step connection structures are first formed, and then the passivation layer is bonded to the first electrode and the insulating layer, ensuring that the first electrode and the pixel structure are electrically connected through at least one connection structure. Therefore, when etching the pixel structure to separate the pixels, it is not necessary to etch the metal, thus avoiding debris splashing during metal etching, making the pixel structure less susceptible to damage, and thereby improving product yield.
[0082] Furthermore, since the diameter of the projected pattern of the first electrode on the insulating layer is larger than the diameter of the projected pattern of the connecting structure on the passivation layer, and the diameter of the projected pattern of the first electrode on the insulating layer is greater than twice the distance between the center points of the plurality of connecting structures, and the distance between the first electrodes is greater than the distance between the center points of the plurality of connecting structures, the arrangement density of the connecting structures is greater than the arrangement density of the first electrodes. This allows each first electrode to be electrically connected to at least one connecting structure. In other words, the first electrode does not need to be perfectly aligned one-to-one with the connecting structure, thereby reducing process requirements while ensuring product yield.
[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized by, The application relates to a substrate, a plurality of first electrodes, an insulating layer, a passivation layer, a plurality of pixel structures, a plurality of connecting structures, a second electrode, a transparent conductive layer, a P-type semiconductor layer, a light-emitting layer and an N-type semiconductor layer. The application relates to a substrate, a plurality of first electrodes, an insulating layer, a passivation layer, a plurality of pixel structures, a plurality of connecting structures, a second electrode, a transparent conductive layer, a P-type semiconductor layer, a light-emitting layer and an N-type semiconductor layer. The first electrode and the connecting structure are both bump structures. The diameter of the projection of the first electrode on the insulating layer is greater than twice the distance between the centers of the connecting structures. The distance between the first electrodes is greater than the distance between the centers of the connecting structures. The first electrodes are arranged in an array, and the connecting structures are arranged in a complementary array. The pixel structure comprises a transparent conductive layer, a P-type semiconductor layer, a light-emitting layer and an N-type semiconductor layer.
2. The semiconductor structure of claim 1, wherein, The first electrode is a P-type electrode, the material of the P-type semiconductor layer is gallium nitride, the second electrode is an N-type electrode, and the material of the N-type semiconductor layer is gallium nitride. 3. The semiconductor structure of claim 1, wherein, 4. The semiconductor structure of claim 3, wherein, 5. The semiconductor structure of claim 4, wherein, 6. The semiconductor structure of claim 4, wherein, 7. The semiconductor structure of claim 1, wherein, 8. The semiconductor structure of claim 1, wherein, 9. The semiconductor structure of claim 2, wherein, 10. The semiconductor structure of claim 9, wherein,