LED chip assembly and display device

Abstract

The utility model provides an LED chip assembly and a display device. The LED chip assembly comprises: a driving substrate; a plurality of LED chips, wherein the plurality of LED chips are bonded on the driving substrate in an array manner; the common electrode layer covers the plurality of LED chips, so that the common electrode layer is electrically connected with the electrode of each LED chip; a plurality of first reflection retaining walls, and each first reflection retaining wall is arranged on the common electrode layer between two adjacent LED chips to form a metal grating; and a plurality of second reflection retaining walls, wherein each second reflection retaining wall is bonded on the first reflection retaining wall. According to the Micro-LED chip, the first reflection retaining wall and the second reflection retaining wall are arranged between the LED chips, so that a reflection grid structure is formed conveniently, the direction of light emitted from the side walls of the LED chips is changed, most of light can be emitted from the front faces, and therefore the light emitting efficiency of the Micro-LED chip is improved.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, and in particular to an LED chip assembly and display device. Background Technology

[0002] Micro-LED displays are a promising display technology with enormous potential applications in technologies such as virtual reality (VR) and augmented reality (AR). Compared to liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), Micro-LEDs offer superior characteristics such as high resolution, high brightness, low power consumption, fast response, high contrast, and long lifespan. Micro-LEDs have a wide range of applications, including optical neural networks, maskless digital lithography, visible light communication, wearable / implantable devices, and super-resolution imaging.

[0003] Micro-LEDs are typically fabricated using ICP etching to etch an epitaxial layer of a III-V semiconductor material into individual island-shaped light-emitting mesas (Mesa). Most of the light emitted from the Mesa sidewalls exits at a large angle, nearly perpendicular to the sidewalls. However, in AR and VR display applications, this large-angle emitted light is often blocked and attenuated, preventing it from reaching the human eye and thus reducing luminous efficiency and intensity. Utility Model Content

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide an LED chip component and display device, which aims to improve the luminous efficiency and luminous intensity of Micro-LEDs at large viewing angles in AR and VR display applications.

[0005] In a first aspect, this application provides an LED chip assembly, including: a driver substrate;

[0006] Multiple LED chips, and an array of the multiple LED chips are bonded to the driving substrate;

[0007] A common electrode layer covers the plurality of LED chips to be electrically connected to the electrodes of each LED chip;

[0008] Multiple first reflective barriers are provided, each of which is disposed on the common electrode layer between two adjacent LED chips to form a metal grid;

[0009] Multiple second reflective barriers, each of which is bonded to the first reflective barrier.

[0010] In one possible embodiment, the first reflective barrier is made of a metallic material.

[0011] In one possible embodiment, the first reflective barrier is rectangular in shape.

[0012] In one possible embodiment, the material of the second reflective barrier is a metallic material or a metallic alloy material.

[0013] In one possible embodiment, the second reflective barrier is in the shape of an isosceles trapezoid.

[0014] In one possible embodiment, the thickness of the first reflective barrier is less than the thickness of the second reflective barrier.

[0015] In one possible embodiment, the sum of the thickness of the first reflective barrier and the thickness of the second reflective barrier is less than or equal to the height of the LED chip.

[0016] In one possible embodiment, the LED chip has a vertical structure.

[0017] In one possible embodiment, the common electrode layer is a transparent conductive layer.

[0018] Secondly, this application also provides a display device, including: an LED chip assembly as described in any one of the first aspects.

[0019] Beneficial effects:

[0020] This application provides an LED chip assembly and display device, which involves bonding multiple LED chip arrays onto a driving substrate and setting a common electrode layer on the multiple LED chips. Then, a first reflective barrier and a second reflective barrier are sequentially set on the common electrode layer between adjacent LED chips to form a reflective grid structure, thereby changing the light direction emitted from the sidewalls of the LED chips and enabling most of the light to be emitted from the front, thereby improving the luminous efficiency of the Micro-LED chip. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an LED chip assembly provided in an embodiment of this application;

[0022] Figure 2 A schematic flowchart illustrating the LED chip assembly fabrication method provided in this application embodiment;

[0023] Figure 3 for Figure 2 The diagram shows the structure of the epitaxial wafer in the LED chip assembly fabrication method.

[0024] Figure 4 for Figure 2 A schematic diagram of the structure after the transparent conductive layer is deposited in the LED chip assembly fabrication method shown;

[0025] Figure 5 for Figure 2 A schematic diagram of the structure of the LED chip assembly after bonding to the driving substrate in the manufacturing method shown;

[0026] Figure 6 for Figure 2 A schematic diagram of the structure after electrode deposition in the LED chip assembly fabrication method shown;

[0027] Figure 7 for Figure 2 A schematic diagram of the patterning process structure in the LED chip component manufacturing method shown;

[0028] Figure 8 for Figure 2 The diagram shows the process structure for creating the passivation layer and opening holes in the LED chip assembly fabrication method.

[0029] Figure 9 for Figure 2 The diagram shows the process structure of depositing the common electrode layer in the LED chip assembly fabrication method.

[0030] Figure 10 for Figure 2 A schematic diagram of the process structure for sputtering the metal layer under the sputtering bumps in the LED chip assembly fabrication method shown;

[0031] Figure 11 for Figure 2 The diagram shows the structural structure of the process for forming the second reflective barrier in the LED chip assembly manufacturing method.

[0032] Figure 12 for Figure 2 The diagram shows the structural structure of the process for forming the first reflective barrier in the LED chip assembly manufacturing method. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.

[0036] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.

[0037] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.

[0038] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0039] refer to Figure 1 This is a schematic diagram of the structure of an LED chip assembly provided in an embodiment of this application. The LED chip assembly includes: a driving substrate 110, an LED chip 120, a common electrode layer 130, a first reflective barrier 140, and a second reflective barrier 150.

[0040] Among them, the driving substrate 110 is a CMOS (Complementary Metal Oxide Semiconductor) substrate.

[0041] Optionally, there may be multiple LED chips 120, and multiple LED chips 120 are arrayed and bonded on the aforementioned driving substrate 110. The specific number of LED chips 120 is determined by the size of the driving substrate 110 and the pixel density, and is not specifically limited here.

[0042] Optionally, the LED chip 120 is a micro LED. It includes red-emitting micro LEDs, green-emitting micro LEDs, and / or blue-emitting micro LEDs.

[0043] Optionally, the LED chip 120 has a vertical structure, that is, the LED chip 120 is a vertical chip.

[0044] In this embodiment, the layer structure of the LED chip 120 includes a bonding metal layer 122, a transparent conductive layer 121, a first semiconductor layer 123, an active layer 125, a second semiconductor layer 127, and an electrode 129, which are stacked sequentially. The first semiconductor layer 123 and the second semiconductor layer 127 are doped semiconductor layers of different types. The bonding metal layer 122 is used for gold-to-gold bonding with the metal layer on the driving substrate 110.

[0045] It is understandable that the material of the transparent conductive layer 121 can be a transparent material with low sheet resistance, such as ITO, IGO, or IZO.

[0046] It is understood that the LED chip 120 may also include other layer structures, such as a current spreading layer, an ohmic contact layer, a passivation layer, etc.

[0047] The first semiconductor layer 123 can be an N-doped semiconductor layer or a P-doped semiconductor layer, and the second semiconductor layer 127 can be a P-doped semiconductor layer or an N-doped semiconductor layer. The active layer 125 can be a multiple quantum well (MQW) structure. Specifically, the semiconductor layer can be a III-V group compound semiconductor material such as GaN, AlGaN, InGaN, AlInP, GaInP, or AlGaInP; the quantum well or quantum layer can be InGaN, AlGaN, InN, InAlN, or AlInGaN; and the quantum barrier alternately stacked with the quantum well layer can be GaN, AlN, AlGaN, AlInGaN, or InAlN; the multiple quantum well structure can include one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum hole); the wavelength emitted by the active layer 125 can be a wavelength in the blue light band, a wavelength in the green light band, or a wavelength in the red light band. This application does not specifically limit the wavelength emitted by the active layer 125.

[0048] Optionally, a common electrode layer 130 covers the electrodes 129 of each LED chip 120 to be electrically connected to the electrodes 129 of each LED chip. For example, if the LED chips 120 have a common N-electrode, the common electrode layer 130 covers the N-electrode of each LED chip 120 to interconnect the N-electrodes of the LED chips 120 together; conversely, if the LED chips 120 have a common P-electrode, the common electrode layer 130 covers the P-electrode of each LED chip 120.

[0049] Optionally, the common electrode layer 130 is a transparent conductive layer. Its material can be a transparent material with low sheet resistance, such as ITO, IGO, or IZO.

[0050] In this embodiment of the application, the first reflective barrier 140 is a convex under metal layer (UBM) structure, and its material can be Cr / Ni / Au, Ti / Ni / Au, Ti / Pt / Au and Ti-W / Au.

[0051] Optionally, the first reflective barrier 140 is made of Ti-W / Au material.

[0052] In this embodiment, there are multiple first reflective barriers 140, and each first reflective barrier 140 is disposed on the common electrode layer 130 between two adjacent LED chips 120 to form a metal grid.

[0053] It is understood that the first reflective barrier 140 can be formed by surface sputtering and wet etching processes, and no specific limitations are made here.

[0054] Optionally, the first reflective barrier 140 is rectangular in shape. For example, it can be a square or a rectangle.

[0055] It should be noted that the aforementioned first reflective barrier 140 is used for adhesion and diffusion blocking.

[0056] In this embodiment, the second reflective barrier 150 is bonded to the first reflective barrier 140.

[0057] Optionally, the number of the second reflective barriers 150 is equal to the number of the first reflective barriers 140.

[0058] Optionally, the material of the second reflective barrier 150 may be a metallic material or a metallic alloy material. No specific limitation is made here.

[0059] Optionally, the second reflective barrier 150 is in the shape of an isosceles trapezoid.

[0060] It is understandable that by creating a trapezoidal second reflective barrier 150 between adjacent LED chips 120, the light emitted from the sidewall of the chip can be mirrored, thereby improving the light extraction efficiency of a single pixel and improving the light emission angle of the entire chip.

[0061] Optionally, the thickness of the first reflective barrier 140 is less than the thickness of the second reflective barrier 150.

[0062] Optionally, the sum of the thickness of the first reflective barrier 140 and the thickness of the second reflective barrier 150 is less than or equal to the height of the LED chip 120.

[0063] In one possible embodiment, the width of the first reflective barrier 140 is smaller than the spacing between adjacent LED chips 120.

[0064] It is understood that the LED chip assembly provided in this embodiment involves bonding an array of multiple LED chips 120 onto the driving substrate 110, and forming a common electrode layer 130 on the multiple LED chips 120. Then, a first reflective barrier 140 and a second reflective barrier 150 are sequentially formed on the common electrode layer 130 between adjacent LED chips 120 to create a reflective grid structure. This changes the direction of light emitted from the sidewalls of the LED chips 120, allowing most of the light to be emitted from the front, thereby improving the luminous efficiency of the Micro-LED chip. Furthermore, since the metallic conductivity of the first reflective barrier 140 and the second reflective barrier 150 is superior to that of the common electrode layer 130, it helps to improve the common current spread and enhance the brightness uniformity of the chip region.

[0065] like Figure 2 As shown, based on the same inventive concept, this application also provides a method for manufacturing an LED chip assembly, the method comprising:

[0066] 101: Provide an epitaxial wafer.

[0067] The epitaxial wafer includes a substrate and functional layers sequentially stacked on the substrate.

[0068] For example, such as Figure 3 As shown in the embodiment of this application, the above-mentioned functional layer constitutes the main epitaxial layer structure of the LED chip. The above-mentioned functional layer may include a second semiconductor layer 127, an active layer 125 and a first semiconductor layer 123 stacked sequentially on the substrate 12.

[0069] 102: A transparent conductive layer is deposited on the functional layer.

[0070] For example, such as Figure 4 As shown, a P-side up epitaxial layer is used, and a transparent conductive layer 121 is deposited on the side of the functional layer away from the substrate. The material can be a transparent material with low substrate resistance such as ITO, IGO, or IZO, and an ohmic contact is formed with the epitaxial layer. For example, an ohmic contact is formed with the first semiconductor layer 123.

[0071] 103: A bonding metal layer is deposited on the transparent conductive layer, and the bonding metal layer is used to bond to the driving substrate.

[0072] For example, such as Figure 5 As shown, the epitaxial layer is transferred to the driving substrate 110 by metal bonding. The material of the bonding metal layer 122 can be Au, Al, Sn, In, Cu, Pt, etc.

[0073] Optionally, after bonding is completed, the substrate 12 on the epitaxial wafer is peeled off to expose the second semiconductor layer 127, wherein the peeling method may be wet etching.

[0074] 104: Electrode is deposited on the second semiconductor layer.

[0075] For example, such as Figure 6 As shown, an electrode 129 is deposited on the epitaxial surface. The material can be Au, Al, Ag, Cu, Ni, AuZn, AuBe, AuGe, AuGeNi, etc. (similar to conductive metals). Then, it is annealed at a temperature of 300-500℃ for 10-60s to form an ohmic contact between the electrode 129 and the second semiconductor layer 127.

[0076] 105: Pattern the functional layer and the bonding metal layer to form multiple independent LED chips.

[0077] For example, such as Figure 7 As shown, the functional layer and bonding metal of the epitaxial wafer are etched into independent island-like structures by ICP etching, forming multiple independent LED chips.

[0078] 106: A passivation layer is deposited on the LED chip, and ICP etching is used to etch open holes in the passivation layer of the LED chip to expose the electrodes on the LED chip.

[0079] For example, such as Figure 8 As shown, a passivation layer 10 is deposited on the epitaxial surface using PECVD; then, the passivation layer 10 on the LED chip surface is etched to create openings using ICP etching.

[0080] 107: Evaporation of a common electrode layer.

[0081] The common electrode layer covers the LED chip to interconnect the electrodes of each LED chip.

[0082] For example, such as Figure 9 As shown, a common electrode layer is deposited on the surface of the LED chip. The material can be a transparent material with low wafer resistance such as ITO, IGO, or IZO. The electrodes of the chip are interconnected using the common electrode layer. Then, the common electrode layer around the chip area is removed using wet etching.

[0083] 108: Sputter a metal layer under the bumps on the common electrode layer.

[0084] For example, such as Figure 10 As shown, the metal layer 13 (UBM) under the sputtered bumps on the wafer surface mainly serves as an adhesion and diffusion barrier. For Au bumps, commonly used UBMs are Cr / Ni / Au, Ti / Ni / Au, Ti / Pt / Au, and Ti-W / Au. This paper selects the Ti-W / Au structure.

[0085] 109: Spin-coat a layer of negative photoresist, and then use the negative photoresist to pattern the surface of the LED chip, exposing the gaps between the LED chips while the other areas are covered by photoresist.

[0086] 110: A second reflective barrier is electroplated at the gap between LED chips using an electroplating gold device.

[0087] For example, such as Figure 11 As shown, a second reflective barrier 150 is electroplated at the gap position of the LED chip using an electroplating gold device.

[0088] 111: Remove the negative photoresist and remove the metal layer under the bumps other than the second reflective barrier.

[0089] Alternatively, wet etching can be used to remove the metal layer under the bumps outside the second reflective barrier.

[0090] It is understandable that after removing the metal layer under the protrusion, the first reflective barrier 140 is formed under the second reflective barrier 150.

[0091] For example, such as Figure 12 As shown, after removing the metal layer under the bumps other than the second reflective barrier 150 by wet etching, the first reflective barrier 140 is formed under the second reflective barrier 150.

[0092] In one possible embodiment, the method further includes: depositing metal in the interface area as a wire bonding metal pad.

[0093] Optionally, the material of the metal pad includes Ti / Pt / Au, Ti / Al, etc.

[0094] Based on the same inventive concept, this application also provides a display device, which includes the LED chip assembly as described in the above embodiments.

[0095] Alternatively, the display device may be an AR display device, a VR display device, a smart wearable device, or a smartphone, etc.

[0096] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An LED chip assembly, characterized by, The LED chip assembly comprises: a driving substrate; a plurality of LED chips, the plurality of LED chips are arrayed and bonded on the driving substrate; a common electrode layer, the common electrode layer covers the plurality of LED chips to electrically connect with the electrodes of each of the LED chips; a plurality of first reflective barriers, each of the first reflective barriers is arranged on the common electrode layer between two adjacent LED chips to form a metal grid; a plurality of second reflective barriers, each of the second reflective barriers is bonded on the first reflective barrier.

2. The LED chip assembly of claim 1, wherein, The material of the first reflective barrier is metal material.

3. The LED chip assembly of claim 1 or 2, wherein, The shape of the first reflective barrier is rectangular.

4. The LED chip assembly of claim 1, wherein, The material of the second reflective barrier is metal material or metal alloy material.

5. The LED chip assembly of claim 4, wherein, The shape of the second reflective barrier is isosceles trapezoid.

6. The LED chip assembly of claim 5, wherein, The thickness of the first reflective barrier is less than the thickness of the second reflective barrier.

7. The LED chip assembly of claim 6, wherein, The sum of the thickness of the first reflective barrier and the thickness of the second reflective barrier is less than or equal to the height of the LED chip.

8. The LED chip assembly of claim 1 or 7, wherein, The LED chip is vertical structure.

9. The LED chip assembly of claim 1, wherein, The common electrode layer is transparent conductive layer.

10. A display device, characterized by comprising: The LED chip assembly comprises: the LED chip assembly according to any one of claims 1-9.

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