5G router circuit and router

Abstract

The utility model provides a 5G router circuit and a router, and relates to the technical field of communication. The 5G router circuit comprises a main chip, a 5G module circuit, a WIFI module circuit, a PCIE interface circuit and a network interface circuit, and the 5G module circuit is connected with the network interface circuit through the PCIE interface circuit to form a first channel through which the 5G module circuit is directly connected with the network interface circuit; the network interface circuit is connected with the main chip, the 5G module circuit is further connected with the main chip through an independent interface, and a second channel passing through the main chip is formed between the 5G module circuit and the network interface circuit; the WIFI module circuit is connected with the main chip through the PCIE interface circuit. Through the 5G router circuit, the data transmission efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a 5G router circuit and a router. BACKGROUND

[0002] The fifth generation mobile communication technology (5th Generation, 5G) is a new generation of wireless communication technology after 4G, which can provide higher network speed, lower delay and stronger connection capability, support more device connections and more efficient data transmission. The 5G router can connect multiple networks and ensure that data can be correctly transmitted from the source device to the target device.

[0003] At present, in the 5G router, the 5G module and the WIFI module are connected with the main chip through independent USB interfaces, and the data received through the 5G module or the WIFI module is transmitted to the main chip through the USB interface. The main chip selects a suitable network according to the network environment and other factors, such as 5G or WIFI, and transmits it to the target module corresponding to the selected network through the USB interface. The target module is the 5G module or the WIFI module, and the data is forwarded by the target module.

[0004] However, the existing 5G router has low data transmission efficiency. CONTENT OF THE INVENTION

[0005] The present application provides a 5G router circuit and a router to solve the problem of low data transmission efficiency of the existing 5G router.

[0006] In a first aspect, the present application provides a 5G router circuit, comprising: a main chip, a 5G module circuit, a WIFI module circuit, a PCIE interface circuit and a network interface circuit, wherein: the 5G module circuit is connected with the network interface circuit through the PCIE interface circuit, forming a first channel of the 5G module circuit and the network interface circuit directly connected; the network interface circuit is connected with the main chip, and the 5G module circuit is also connected with the main chip through an independent interface, forming a second channel between the 5G module circuit and the network interface circuit through the main chip; the WIFI module circuit is connected with the main chip through the PCIE interface circuit;

[0007] The 5G module circuit is configured to transmit the received mobile data to the network interface circuit through the first channel and the second channel in parallel for mobile data forwarding, and receive the data sent by the main chip through the independent interface for data sending.

[0008] The WIFI module circuit is configured to transmit received wireless data to the host chip through the PCIE interface and receive data transmitted by the host chip to send out data.

[0009] The host chip is configured to receive and process data transmitted by the 5G module circuit and the WIFI module circuit, and then transmit the processed data to the 5G module circuit or the WIFI module circuit corresponding to the selected network.

[0010] In a possible implementation, the PCIE interface circuit includes an interface conversion chip and an interface conversion chip clock circuit.

[0011] The interface conversion chip is configured to convert received mobile data from a PCIE interface signal into a physical layer signal and transmit the mobile data to the network interface circuit.

[0012] The interface conversion chip clock circuit is configured to generate, synchronize and distribute a clock signal to make the timing of the PCIE interface circuit correspond to the timing of the network interface circuit.

[0013] In a possible implementation, the interface conversion chip clock circuit includes a first crystal oscillator, a first capacitor and a second capacitor.

[0014] The ground pin of the first crystal oscillator is grounded.

[0015] The output pin of the first crystal oscillator is connected to the output pin of the interface conversion chip, and the output pin of the first crystal oscillator is also grounded through the second capacitor.

[0016] The input pin of the first crystal oscillator is connected to the input pin of the interface conversion chip, and the input pin of the first crystal oscillator is also grounded through the first capacitor.

[0017] In a possible implementation, the host chip includes a host chip clock circuit, and the host chip clock circuit is connected to the crystal input pin and the crystal output pin of the host chip.

[0018] The host chip clock circuit is configured to provide a clock signal to synchronize the operation of each circuit.

[0019] In a possible implementation, the host chip clock circuit includes a second crystal oscillator, a first resistor, a second resistor, a third capacitor and a fourth capacitor.

[0020] The ground pin of the second crystal oscillator is grounded.

[0021] The input pin of the second crystal oscillator is connected to the crystal input pin of the host chip through the first resistor, and the input pin of the second crystal oscillator is also grounded through the fourth capacitor.

[0022] The output pin of the second crystal oscillator is connected with the crystal output pin of the main chip through a second resistor, and the output pin of the second crystal oscillator is also grounded through a third capacitor.

[0023] In a possible implementation, the 5G module circuit includes a 5G signal antenna, and the WIFI module circuit includes a WIFI antenna, both of which are electrically connected with the main chip.

[0024] The 5G module circuit is configured to send and receive 5G signals through the 5G signal antenna.

[0025] The WIFI module circuit is configured to send and receive WIFI signals through the WIFI antenna.

[0026] In a possible implementation, the 5G router circuit further includes a power supply circuit and an indicator light circuit, wherein the power supply circuit is connected with the indicator light circuit.

[0027] The power supply circuit is configured to connect an external power supply, convert a voltage provided by the external power supply into different working voltages, and output the working voltages to each circuit in the 5G router circuit.

[0028] The indicator light circuit is configured to display working states of devices corresponding to the indicator light through the indicator light.

[0029] In a possible implementation, the indicator light circuit includes a state indicator light, an Ethernet indicator light, a 5G network indicator light, a 4G network indicator light, a WIFI indicator light, a fifth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor.

[0030] The power supply circuit is connected with an input end of the indicator light circuit, and the power supply circuit is connected with anodes of the state indicator light, the Ethernet indicator light, the 5G network indicator light, the 4G network indicator light, and the WIFI indicator light through the third resistor respectively, and the power supply circuit is grounded through the third resistor and the fifth capacitor in sequence.

[0031] A cathode of the state indicator light is connected with a clock signal pin of a JTAG interface on the main chip through the fourth resistor; a cathode of the Ethernet indicator light is connected with a data output pin of the JTAG interface on the main chip through the fifth resistor; a cathode of the 5G network indicator light is connected with a data input pin of the JTAG interface on the main chip through the sixth resistor; a cathode of the 4G network indicator light is connected with a third data sending pin of a serial communication interface on the main chip through the seventh resistor; and a cathode of the WIFI indicator light is connected with a third data receiving pin of the serial communication interface on the main chip through the eighth resistor.

[0032] In a possible implementation, the 5G router circuit further includes a key circuit, and the key circuit is electrically connected with the power supply circuit.

[0033] A key circuit is configured to detect a user's key input to realize control and interaction of the router.

[0034] In a possible implementation, the key circuit comprises an RST key circuit and a WPS key circuit.

[0035] The RST key circuit comprises an RST key, a ninth resistor, a tenth resistor, a sixth capacitor and a seventh capacitor.

[0036] One end of the RST key is grounded, and the other end is connected to the power supply circuit through the ninth resistor. One end of the RST key connected to the power supply circuit is connected to the reset pin of the main chip through the tenth resistor, and is grounded through the sixth capacitor and the seventh capacitor, respectively.

[0037] The WPS key circuit comprises a WPS key, an eleventh resistor, a twelfth resistor, an eighth capacitor and a ninth capacitor.

[0038] One end of the WPS key is grounded, and the other end is connected to the power supply circuit through the eleventh resistor. One end of the WPS key connected to the power supply circuit is connected to the test mode selection pin of the JTAG interface of the main chip through the twelfth resistor, and is grounded through the eighth capacitor and the ninth capacitor, respectively.

[0039] In a possible implementation, the 5G router circuit further comprises an I / O interface circuit.

[0040] The key circuit and the indicator light circuit are connected to the main chip through the I / O interface circuit.

[0041] In a possible implementation, the 5G router circuit further comprises a storage circuit.

[0042] Correspondingly, the power supply circuit comprises a storage power supply circuit, and the storage circuit is electrically connected to the storage power supply circuit.

[0043] In a possible implementation, the storage power supply circuit comprises a voltage stabilizer, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a thirteenth resistor and a fourteenth resistor.

[0044] The input pin of the voltage stabilizer receives an input voltage, and the input pin of the voltage stabilizer is grounded through the tenth capacitor and the eleventh capacitor, respectively.

[0045] The first output pin and the second output pin of the voltage stabilizer are connected in parallel to the storage circuit to provide a working voltage for the storage circuit; the first output pin and the second output pin are grounded through the twelfth capacitor, the thirteenth capacitor and the fourteenth capacitor, respectively; the first output pin and the second output pin are further connected to the input pin of the voltage stabilizer through the fourteenth resistor and grounded through the thirteenth resistor.

[0046] In a possible implementation, the 5G module circuit further includes a SIM card circuit, which is electrically connected with the main chip;

[0047] The SIM card circuit is configured to acquire and verify SIM card information, so that the device accesses the 5G network.

[0048] In a second aspect, the present application provides a router, which includes the 5G router circuit provided in the first aspect.

[0049] The 5G router circuit and the router provided by the present application are configured to set a main chip, a 5G module circuit, a WIFI module circuit, a PCIE interface circuit and a network interface circuit. The 5G module circuit is connected with the network interface circuit through the PCIE interface circuit, forming a first channel in which the 5G module circuit is directly connected with the network interface circuit. The network interface circuit is connected with the main chip, and the 5G module circuit is also connected with the main chip through an independent interface, forming a second channel in which the 5G module circuit and the network interface circuit pass through the main chip. The parallel operation of the two channels allows data to be distributed to different paths for simultaneous transmission, thereby avoiding the occurrence of bottlenecks. The first channel directly transmits data without the intervention of the main chip, thereby reducing the burden of the main chip and the delay in the data transmission process. The intervention of the main chip in the second channel allows the second channel to implement some complex network management functions, such as flow control, data encryption / decryption, error correction, etc. In addition, the WIFI module circuit transmits data to the main chip through the PCIE interface and receives data sent by the main chip for data sending. Through the PCIE interface, the data transmission between the WIFI module and the main chip is high-speed, which can quickly process a large amount of wireless data. In addition, the 5G and WIFI modules operate in parallel, so that different applications or devices can exchange data through the 5G and WIFI networks at the same time, thereby avoiding the congestion problem of a single channel and improving the data transmission speed and efficiency through the two parallel paths. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0051] Figure 1 A structure diagram of a 5G router circuit provided by an embodiment of the present application;

[0052] Figure 2 A structure diagram of a PCIE interface circuit provided by an embodiment of the present application;

[0053] Figure 3 A structural schematic diagram of a main chip clock circuit provided for an embodiment of the present application is shown in FIG. 1.

[0054] Figure 4 A structural schematic diagram of a U6A region of a main chip provided for an embodiment of the present application is shown in FIG. 2.

[0055] Figure 5 A structural schematic diagram of a U6B region of a main chip provided for an embodiment of the present application is shown in FIG. 3.

[0056] Figure 6 A structural schematic diagram of a U6D region of a main chip provided for an embodiment of the present application is shown in FIG. 4.

[0057] Figure 7 A structural schematic diagram of a U6E region of a main chip provided for an embodiment of the present application is shown in FIG. 5.

[0058] Figure 8 A structural schematic diagram of another 5G router circuit provided for an embodiment of the present application is shown in FIG. 6.

[0059] Figure 9 A structural schematic diagram of a pilot lamp circuit provided for an embodiment of the present application is shown in FIG. 7.

[0060] Figure 10 A structural schematic diagram of a power supply circuit provided for an embodiment of the present application is shown in FIG. 8.

[0061] Figure 11 A structural schematic diagram of a DDR3 circuit provided for an embodiment of the present application is shown in FIG. 9.

[0062] Figure 12 A structural schematic diagram of a DDR3 power supply circuit provided for an embodiment of the present application is shown in FIG. 10.

[0063] Figure 13 A structural schematic diagram of a NAND circuit provided for an embodiment of the present application is shown in FIG. 11.

[0064] Figure 14 A structural schematic diagram of a key circuit provided for an embodiment of the present application is shown in FIG. 12.

[0065] Reference signs:

[0066] 1 - main chip; 2 - 5G module circuit; 3 - WIFI module circuit; 4 - PCIE interface circuit; 5 - network interface circuit; 6 - pilot lamp circuit; 7 - DDR3 circuit; 8 - NAND circuit; 9 - key circuit. DETAILED DESCRIPTION

[0067] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below in combination with the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0068] The terms "first", "second", "third", "fourth" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances. For example, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information, without departing from the scope of the present application.

[0069] Depending on the context, the word "if" as used herein can be interpreted to mean "when" or "upon" or "in response to determining".

[0070] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise.

[0071] It should be further understood that the terms "comprise", "comprising", "include", "including", "contain", "containing", "have", "having", and "comprising" indicate the presence of the described features, steps, operations, elements, components, items, kinds, and / or groups but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0072] The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or meaning any one or any combination. Therefore, "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive.

[0073] In the prior art, the 5G module and the WIFI module in the 5G router are connected with the main chip through independent USB interfaces. When the 5G module or the WIFI module receives external data, the 5G module or the WIFI module transmits the received data to the main chip through the USB interface. The main chip decides to select which network (5G or WIFI) to use according to the current network environment (such as network quality, bandwidth demand, signal strength, etc.). Then the processed data is transmitted to the selected target module (5G module or WIFI module). Finally, after the selected target module (5G or WIFI module) receives the data, it will be responsible for forwarding the data through the respective wireless network (5G or WIFI).

[0074] However, due to the limitation of the bandwidth of the USB interface, the transmission efficiency is low, especially in the scene of multi-task or large data flow, the USB interface cannot meet the demand of high efficiency data transmission, which may cause delay and reduce the quality of network connection.

[0075] In view of the above problems, the present application provides a 5G router circuit and a router. Based on the consideration of the low transmission efficiency of the USB interface, the PCIE interface circuit is set. The PCIE interface has higher bandwidth than the traditional USB interface and is suitable for high-speed data transmission. The 5G module circuit is connected directly with the network interface circuit through the PCIE interface circuit to form a data transmission channel. The 5G module circuit can directly forward the received mobile data to the network interface circuit for data forwarding without the need of processing by the main chip, so that the data can be transmitted at a higher speed and the burden of the main chip is reduced. At the same time, the 5G module circuit is also connected with the main chip through an independent interface to form a channel through the main chip, so that the main chip can further process the data or select a suitable network for transmission. Combining the above two channels, the data is transmitted in parallel through the double channels to avoid the occurrence of bottleneck and improve the data transmission efficiency. In addition, the WIFI module circuit is connected with the main chip through the PCIE interface to be responsible for the reception and transmission of wireless data, so that the WIFI module circuit can communicate with the main chip more efficiently and reduce the data transmission delay caused by bandwidth bottleneck.

[0076] The technical solutions of the present application will be described in detail in the following specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0077] Please refer to Figure 1 The embodiment of the present application provides a 5G router circuit, which comprises a main chip 1, a 5G module circuit 2, a WIFI module circuit 3, a PCIE interface circuit 4 and a network interface circuit 5.

[0078] The 5G module circuit 2 is connected with the network interface circuit 5 through the PCIE interface circuit 4 to form a first channel directly connecting the 5G module circuit 2 and the network interface circuit 5.

[0079] The network interface circuit 5 is connected with the main chip 1, and the 5G module circuit 2 is also connected with the main chip 1 through an independent interface to form a second channel between the 5G module circuit 2 and the network interface circuit 5 through the main chip 1.

[0080] The WIFI module circuit 3 is connected with the main chip 1 through the PCIE interface circuit 4.

[0081] 5G module circuit 2, for transmitting received mobile data to network interface circuit 5 for mobile data forwarding through first and second channels in parallel; and receiving data sent by main chip 1 through an independent interface for data sending;

[0082] WIFI module circuit 3, for transmitting received wireless data to main chip 1 through PCIE interface, and receiving data sent by main chip 1 for data sending;

[0083] Main chip 1, for receiving and processing data transmitted by 5G module circuit 2 and WIFI module circuit 3, and then sending the processed data to the corresponding 5G module circuit 2 or WIFI module circuit 3 of the selected network.

[0084] In this embodiment, 5G module circuit 2 receives mobile data and transmits through two channels, including a first channel: transmitting data directly to network interface circuit 5 through PCIE interface circuit 4; a second channel: connecting with main chip 1 through an independent interface, and the main chip processes the data and then forwards it to network interface circuit 5. In addition, WIFI module circuit 3 receives wireless data and transmits it to main chip 1 through PCIE interface circuit 4, and main chip 1 is responsible for receiving data from 5G module circuit 2 and WIFI module circuit 3, processing it, and then sending it to 5G or WIFI module according to the network environment to complete the final data forwarding.

[0085] Among them, the independent interface can be a USB interface, an Ethernet interface, etc. These interfaces have communication capabilities and can realize independent work or data transmission of modules or devices.

[0086] As an example, in the scenario of a smartphone using a 5G network for data transmission, if the phone is browsing a webpage through a 5G network, data is transmitted to the phone through a 5G mobile network. In order to improve the speed and stability of data transmission, the phone can use two channels for data transmission. The 5G module of the phone transmits data directly to the main processing chip (CPU) through the PCIE interface. This channel is used for high-speed, low-latency data transmission, ensuring that data can be quickly transmitted to the main chip for processing. In addition, the phone transmits data from the 5G module to the network interface of the phone through another special interface (such as a wireless interface). This channel can be used for different data streams or backup paths to ensure that even if the first channel is delayed or congested, data can still be transmitted through the second channel. As a result, data can not only be divided into two data streams and transmitted through the two channels to improve data transmission speed, but also can use another channel as a backup channel when a problem occurs in one channel, avoiding network connection interruption or delay.

[0087] It can be understood that the 5G module circuit transmits data through two channels (the first channel and the second channel) in parallel, improves the data transmission efficiency, and avoids the possible bottleneck of a single channel. At the same time, the PCIE interface circuit provides higher bandwidth to ensure fast data transmission and meet high traffic demand. In addition, through multiple channels and interfaces, the burden of the main chip is reasonably distributed, improving the overall performance of the system.

[0088] In some embodiments, the network interface circuit includes 1 WAN interface, 3 LAN interfaces, and 1 Console interface. The WAN interface, the LAN interface, and the Console interface are electrically connected to the main chip, respectively.

[0089] The WAN interface is used to connect to an external network, and the main chip exchanges data with the external network through the WAN interface, responsible for sending and receiving data streams of the external network. The LAN interface is a local area network interface, and the main chip exchanges data with other devices in the local area network through the LAN interface to realize communication of the internal network. The Console interface is a console interface of the device, and the console of the device can be accessed through the Console interface for initial configuration, troubleshooting, or advanced setting operation.

[0090] It can be understood that by integrating the WAN, LAN, and Console interfaces, the device can interact with the external network, the local area network, and the administrator at the same time. This design improves the flexibility and scalability of the device. And because there are multiple LAN interfaces, the device can support concurrent connections of multiple terminals without affecting network speed.

[0091] Please refer to Figure 2 The PCIE interface circuit provided by the embodiments of the present application includes an interface conversion chip U2636 and an interface conversion chip clock circuit.

[0092] The interface conversion chip U2636 is used to convert the received mobile data from a PCIE interface signal to a physical layer signal and transmit it to the network interface circuit.

[0093] The interface conversion chip clock circuit is used to generate, synchronize, and distribute clock signals to make the timing of the PCIE interface circuit and the network interface circuit correspond.

[0094] In this embodiment, the interface conversion chip U2636 first receives the signal from the PCIE interface, converts the received PCIE signal into a physical layer signal, that is, a format suitable for the network interface circuit. In this way, the converted physical layer signal can continue to be transmitted to the network interface circuit. At the same time, the interface conversion chip clock circuit generates and synchronizes the clock signal, ensuring that the timing between the PCIE interface circuit and the network interface circuit is accurately matched to avoid data transmission errors or loss. Then, the converted physical layer signal and the synchronized clock signal are transmitted together to the network interface circuit, completing the transmission of data.

[0095] It can be understood that the interface conversion chip converts the PCIE interface signal into a physical layer signal, so that the data that can only be transmitted on the PCIE bus can be used in the network interface circuit, thereby realizing data conversion and compatibility between different types of interfaces. And by generating and synchronizing the clock signal through the clock circuit, it is ensured that the timing between the PCIE interface circuit and the network interface circuit is accurately consistent during data transmission, avoiding data errors or packet loss due to different timing, and ensuring the stability and reliability of the system.

[0096] In this embodiment, the interface conversion chip clock circuit includes a first crystal oscillator U2637, a first capacitor C5789 and a second capacitor C5790;

[0097] The ground pin of the first crystal oscillator U2637 is grounded;

[0098] The output pin 1 of the first crystal oscillator U2637 is connected to the output pin 28 of the interface conversion chip, and the output pin 1 of the first crystal oscillator U2637 is also grounded through the second capacitor C5790;

[0099] The input pin 3 of the first crystal oscillator U2637 is connected to the input pin 29 of the interface conversion chip, and the input pin 3 of the first crystal oscillator U2637 is also grounded through the first capacitor C5789.

[0100] The ground pin of the first crystal oscillator U2637 is grounded;

[0101] It should be noted that the first crystal oscillator U2637 is a passive crystal and does not distinguish between input and output, so the output pin 1 of the first crystal oscillator U2637 can be connected to the output pin 28 of the interface conversion chip, and the input pin 3 of the first crystal oscillator U2637 can be connected to the input pin 29 of the interface conversion chip.

[0102] In this embodiment, the first crystal oscillator U2637 is used to generate a clock signal, which is generated by an internal crystal element to produce a stable frequency output signal, which is the clock source of the interface conversion chip clock circuit. The clock signal generated by the output pin 1 of the first crystal oscillator U2637 is transmitted to the interface conversion chip through the pin 28, which can be used to synchronize the operation of each part of the circuit, and ensure the consistency of the whole system in timing. The input pin 3 of the first crystal oscillator U2637 is connected with the input pin 29 of the interface conversion chip, providing a feedback or control signal, which helps the coordinated work between the crystal oscillator and the interface conversion chip, and ensures the accuracy and stability of the clock signal. At the same time, the output pin 1 of the first crystal oscillator U2637 is grounded through the second capacitor C5790, and the capacitor C5790 plays a filtering role to help stabilize the clock signal and reduce interference. The input pin 3 is also grounded through the capacitor C5789, so as to remove high-frequency noise and further stabilize the input signal, avoiding noise interference to cause the fluctuation of the clock signal.

[0103] Please refer to Figures 3 to 7 In this embodiment, the main chip includes a main chip clock circuit, which is connected with the crystal input pin P17 and the crystal output pin P18 of the main chip.

[0104] The main chip clock circuit is used to provide a clock signal to synchronize the operation of each circuit.

[0105] In this embodiment, the model of the main chip is MT7621A, which includes U6A, U6B, U6C, U6D and U6E areas. The crystal input pin P17 is the XTAL XI pin, and the crystal output pin P18 is the XTAL XO pin.

[0106] It can be understood that the main chip generates a clock signal through the main chip clock circuit, receives an input signal from an external crystal oscillator through the crystal input pin P17, and the clock circuit inside the main chip amplifies and stabilizes the input signal to provide a 40MHz frequency clock signal for the main chip. Then the clock signal is distributed to each circuit and module inside the main chip through the P18 pin, so as to ensure that they work under the synchronized timing. Through the synchronization of the clock signal, the multiple areas (U6A, U6B, U6C, U6D, U6E, etc.) contained in the main chip can execute instructions and process tasks in coordination.

[0107] Please continue to refer to Figure 3 In this embodiment, the main chip clock circuit includes a second crystal oscillator U23, a first resistor R61, a second resistor R62, a third capacitor C324 and a fourth capacitor C325.

[0108] The ground pin of the second crystal oscillator U23 is grounded.

[0109] The input pin 1 of the second crystal oscillator U23 is connected to the crystal input pin P17 of the main chip through the first resistor R61, and the input pin 1 of the second crystal oscillator U23 is also grounded through the fourth capacitor C325;

[0110] The output pin 3 of the second crystal oscillator U23 is connected to the crystal output pin P18 of the main chip through the second resistor R62, and the output pin 3 of the second crystal oscillator U23 is also grounded through the third capacitor C324.

[0111] The ground pins of the second crystal oscillator U23 are pin 2 and pin 4.

[0112] It should be noted that the second crystal oscillator U23 is a passive crystal and does not distinguish between input and output, so the input pin 1 of the second crystal oscillator U23 can be connected to the crystal input pin P17 of the main chip, and the output pin 3 of the second crystal oscillator U23 can be connected to the crystal output pin P18 of the main chip.

[0113] In the embodiment, the main chip clock circuit generates a clock signal through the second crystal oscillator U23. The input pin 1 of the second crystal oscillator U23 is connected to the crystal input pin P17 of the main chip through the first resistor R61, and is also grounded through the fourth capacitor C325 to form an oscillation loop. The output pin 3 is connected to the crystal output pin P18 of the main chip through the second resistor R62, and is grounded through the third capacitor C324 to stabilize the output signal. The ground pins 2 and 4 of the oscillator U23 ensure stable operation of the circuit, thereby providing an accurate clock signal to ensure timing synchronization of the main chip and stable operation of the system.

[0114] In a possible implementation, the 5G module circuit includes a 5G signal antenna, and the WIFI module circuit includes a WIFI antenna, and the 5G signal antenna and the WIFI antenna are electrically connected to the main chip;

[0115] The 5G module circuit is configured to send and receive 5G signals through the 5G signal antenna.

[0116] The WIFI module circuit is configured to send and receive WIFI signals through the WIFI antenna.

[0117] In this embodiment, the WIFI module circuit and the 5G module circuit each include 4 signal antennas. The 5G module circuit and the WIFI module circuit are electrically connected to the main chip through their respective antennas and are responsible for sending and receiving 5G signals and WIFI signals, respectively. Among them, the 5G module circuit transmits and receives high-speed data through the 5G signal antenna to provide 5G network connection; and the WIFI module circuit processes WIFI signals through the WIFI antenna to realize Wireless Local Area Network (WLAN) connection.

[0118] It can be understood that the 5G signal antenna and the WIFI antenna work independently, but are controlled and coordinated by the main chip to ensure that the device can access 5G and WIFI networks at the same time, meet different communication needs, provide multiple network connection methods, and improve the communication ability and flexibility of the device.

[0119] In a possible implementation, the 5G module circuit further includes a SIM card circuit, and the SIM card circuit is electrically connected to the main chip.

[0120] The SIM card circuit is configured to obtain and verify SIM card information to enable the device to access the 5G network.

[0121] In this embodiment, the Subscriber Identity Module (SIM) card circuit is electrically connected to the main chip. The SIM card circuit includes two SIM card sockets for connecting with SIM cards to provide SIM card communication services, so that the router can support 4G and 5G SIM card communication services. After the device is started, the SIM card circuit reads the stored user information (such as phone number, identity authentication data, etc.) from the SIM card, and the main chip obtains these information through the SIM card circuit, and then performs identity verification to ensure the validity and legality of the SIM card. After verification, the main chip communicates with the 5G network to complete the process of device access to the 5G network.

[0122] It can be understood that by integrating the SIM card circuit, the device can conveniently verify the SIM card information and complete the connection of the 5G network, ensure that the device can access the 5G network through effective identity authentication, and guarantee the security and reliability of communication. And it can support the device to switch between different operator networks and ensure stable 5G network service, improve the networking ability of the device and user experience.

[0123] Please refer to Figures 8 to 10 In this embodiment, the 5G router circuit further includes a power supply circuit and an indicator light circuit, and the power supply circuit is connected to the indicator light circuit.

[0124] The power supply circuit is used for connecting an external power supply, converting a voltage provided by the external power supply into different working voltages, and outputting the working voltages to each circuit in the 5G router circuit.

[0125] The indicator light circuit is used for displaying the working state of the device corresponding to the indicator light through the indicator light.

[0126] In the embodiment, the external power supply can be a battery or a socket power supply, etc. The power supply circuit can convert the voltage provided by the external power supply into different working voltages required by the 5G router circuit, and output the working voltages to each component in the 5G router circuit, for example, output 1.0V, 1.1V, 1.2V, 1.5V and 3.3V working voltages, to ensure the normal working of the device.

[0127] The indicator light circuit is connected with the power supply circuit, and can display the current state of the device through the indicator light of different colors or flashing modes according to the working state of the router (such as booting, connecting, network exception, etc.), thereby helping the user to understand whether the device is normally running.

[0128] Please refer to Figure 9 In the embodiment, the indicator light circuit includes a state indicator light D1, an Ethernet indicator light D2, a 5G network indicator light D3, a 4G network indicator light D4, a WIFI indicator light D5, a fifth capacitor C5725, a third resistor R3871, a fourth resistor R3119, a fifth resistor R3867, a sixth resistor R3868, a seventh resistor R3869 and an eighth resistor R3870.

[0129] The power supply circuit is connected with the input end of the indicator light circuit, and the power supply circuit is connected with the anodes of the state indicator light D1, the Ethernet indicator light D2, the 5G network indicator light D3, the 4G network indicator light D4 and the WIFI indicator light D5 through the third resistor R3871 respectively, and the power supply circuit is grounded through the third resistor R3871 and the fifth capacitor C5725 in sequence.

[0130] The cathode of the state indicator light D1 is connected with the clock signal pin F16 of the JTAG interface on the main chip through the fourth resistor R3119; the cathode of the Ethernet indicator light D2 is connected with the data output pin G17 of the JTAG interface on the main chip through the fifth resistor R3867; the cathode of the 5G network indicator light D3 is connected with the data input pin G16 of the JTAG interface on the main chip through the sixth resistor R3868; the cathode of the 4G network indicator light D4 is connected with the third data transmission pin H1 of the serial communication interface on the main chip through the seventh resistor R3869; and the cathode of the WIFI indicator light D5 is connected with the third data receiving pin H3 of the serial communication interface on the main chip through the eighth resistor R3870.

[0131] The clock signal pin F16 of the JTAG interface on the main chip is JTCLK pin; the data output pin G17 of the JTAG interface is JTDO pin; the data input pin G16 of the JTAG interface is JTDI pin; the third data sending pin H1 of the serial communication interface is TXD3 pin; and the third data receiving pin H3 of the serial communication interface is RXD3 pin.

[0132] In the embodiment, the indicator light circuit monitors and displays the working state of the device through multiple components. The power supply circuit provides the necessary voltage to the indicator light circuit, and the power supply circuit transmits the voltage to the anodes of the status indicator light D1, the Ethernet indicator light D2, the 5G network indicator light D3, the 4G network indicator light D4 and the WIFI indicator light D5 through the third resistor R3871, and the cathodes of each indicator light are connected to the specific pins of the main chip through different resistors. The working state of each indicator light is controlled by the signal change of the chip pin connected thereto. Different pins will send different signals according to the working state of the device (such as whether it is connected to the network, whether it is in the active state, etc.), thereby driving the corresponding indicator light to turn on or off, reflecting the current state of the device.

[0133] As an example, the indicator light in the indicator light circuit is a light-emitting diode, which is used to reflect the working state of the circuit respectively, for example, when the WIFI module circuit operates normally, the WIFI indicator light D5 is turned on to send a signal prompt.

[0134] It can be understood that through different indicator lights, it can be quickly understood whether the device is working normally, whether it is connected to the 5G, 4G or WIFI network, or the Ethernet connection state. The control signal of each indicator light comes from the dedicated pin of the main chip, and through the cooperation of resistors and capacitors, the stable transmission of the signal is ensured.

[0135] Please refer to Figures 10 to 12 In the embodiment, the 5G router circuit further comprises a storage circuit.

[0136] Correspondingly, the power supply circuit comprises a storage power supply circuit, and the storage circuit is electrically connected to the storage power supply circuit.

[0137] In the embodiment, the storage circuit can be a Double Data Rate 3 (DDR3) circuit, which is a dynamic random access memory mainly used for cache and data storage. Correspondingly, the storage power supply circuit is a DDR3 power supply circuit, which provides the required stable voltage for the DDR3 circuit, usually 1.5V or 1.35V.

[0138] When the 5G router is connected to the power supply, in order to ensure that the DDR3 memory can work normally, the power supply circuit provides a stable 1.5V voltage (1.35V voltage if it is 1.35V DDR3) for the DDR3 circuit through the DDR3 power supply circuit, and the DDR3 memory in the DDR3 circuit is responsible for storing data and programs. The main chip exchanges data with the DDR3 memory, and in the process of high-speed network data transmission, the DDR3 memory provides support for data caching and temporary storage, improves the processing speed and efficiency of the system, and can read and write data according to the requirements of the main chip.

[0139] Please refer to Figure 12 In this embodiment, the storage power supply circuit includes a voltage stabilizer U1302, a tenth capacitor C963, an eleventh capacitor C964, a twelfth capacitor C965, a thirteenth capacitor C966, a fourteenth capacitor C967, a thirteenth resistor R21 and a fourteenth resistor R22.

[0140] The input pin 1 of the voltage stabilizer U1302 receives an input voltage, and the input pin 1 of the voltage stabilizer U1302 is grounded through the tenth capacitor C963 and the eleventh capacitor C964 respectively.

[0141] The first output pin 2 and the second output pin 4 of the voltage stabilizer U1302 are connected in parallel to the storage circuit to provide working voltage for the storage circuit; the first output pin 2 and the second output pin 4 are grounded through the twelfth capacitor C965, the thirteenth capacitor C966 and the fourteenth capacitor C967 respectively; the first output pin 2 and the second output pin 4 are also connected to the input pin 1 of the voltage stabilizer U1302 through the fourteenth resistor R22, and grounded through the thirteenth resistor R21.

[0142] In the embodiment, the input voltage of the storage power supply circuit (DDR3 power supply circuit) is 3.3V, which is received by the input pin 1 of the voltage stabilizer U1302, and the voltage is adjusted as needed to ensure that the output stable 1.5V working voltage is supplied to the storage circuit (DDR3 circuit). The input voltage is first grounded through the tenth capacitor C963 and the eleventh capacitor C964 for filtering to eliminate noise in the voltage and ensure that the voltage entering the voltage stabilizer is more stable. At the same time, the first output pin 2 and the second output pin 4 of the voltage stabilizer U1302 are connected in parallel to the storage circuit to convert the input 3.3V voltage into a stable voltage suitable for the DDR3 circuit and provide a working voltage for it. In order to further ensure the stability of the output voltage, the output pin 2 and the pin 4 of the voltage stabilizer U1302 are respectively grounded through the twelfth capacitor C965, the thirteenth capacitor C966 and the fourteenth capacitor C967 for further filtering to remove high-frequency noise in the output voltage and keep the voltage smooth. In addition, the fourteenth resistor R22 connects the first output pin 2 of the voltage stabilizer U1302 with the input pin 1 to form a feedback loop, which helps to stabilize the output voltage. The first output pin 2 and the second output pin 4 are also connected to the input pin 1 of the voltage stabilizer U1302 through the fourteenth resistor R22 and grounded through the thirteenth resistor R21, thereby further stabilizing the working state of the voltage stabilizer U1302 and ensuring that the output voltage will not be affected by unstable factors.

[0143] It should be noted that the DDR3 circuit includes a 16-bit data bus DQ0-DQ15 and a 13-bit address bus, VREFDQ is the reference voltage of the data bus, VREFCA is the reference voltage of the address bus, and VDDQ is the working voltage of the DDR3, which is 1.5V in the embodiment, and the external power supply is converted into a 1.5V working voltage by the power supply circuit to provide the DDR3 circuit.

[0144] It can be understood that the voltage stabilizer provides a stable working voltage for the storage circuit (DDR3 circuit) by precisely controlling the input voltage, ensuring that the storage circuit can work in a stable voltage environment and avoiding memory errors or unstable performance caused by voltage fluctuations. At the same time, the filtering effect of the capacitors C963, C964, C965, C966 and C967 at the input and output ends can effectively suppress high-frequency noise and power supply interference in the voltage and keep the voltage output by the voltage stabilizer smooth. And the feedback effect of the resistors R21 and R22 improves the control accuracy of the voltage stabilizer, ensures the stability of the output voltage, and can cope with the impact of load changes, thereby ensuring the normal operation of the entire circuit.

[0145] Please refer to Figure 13In this embodiment, the storage circuit can also be a negative-AND (NAND) flash memory circuit. The NAND circuit is connected to the main chip and communicates data, wherein the NAND flash chip adopts a TSOT48 package.

[0146] The NAND flash is a non-volatile memory and can be used in storage devices such as solid state disks, USB flash disks, etc. The NAND flash chip communicates data through connection with the main chip.

[0147] The thin small outline transistor 48-lead package (TSOT48) is a small package type mainly used to reduce space occupation and improve product integration. In this embodiment, the NAND flash chip adopting the TSOT48 package can be installed in a smaller circuit board area, thereby adapting to more compact electronic product design.

[0148] It can be understood that the power supply circuit provides a stable voltage for the NAND flash through the voltage stabilizer, and the connection and data communication of the main chip with the NAND flash can realize fast data reading and writing, support more efficient storage management, and complete a large number of data access operations in a short time, thereby improving the overall performance of the storage system. At the same time, the use of the TSOT48 package enables the NAND flash chip to work in a smaller physical space while maintaining high performance, thereby adapting to more compact device design. In addition, the TSOT48 package usually also has lower power consumption, which helps to improve the energy efficiency of the overall system.

[0149] Please refer to Figure 14 In this embodiment, the 5G router circuit further comprises a key circuit electrically connected with the power supply circuit.

[0150] The key circuit is used to detect the key input of the user to realize the control and interaction function of the router.

[0151] In this embodiment, the key circuit is electrically connected with the power supply circuit to ensure that the key circuit can obtain the required power supply to work normally. When the user presses the key on the router, the key circuit senses the state change (such as pressing or releasing) of the key and transmits the input signal to the main chip of the router to control various functions of the router, such as turning on / off WIFI, restarting the router, switching network mode, adjusting settings, etc., thereby realizing the interaction between the user and the router.

[0152] Please continue to refer to Figure 14In the embodiment, the key circuit includes an RST key circuit and a WPS key circuit.

[0153] The RST key circuit includes an RST key S1, a ninth resistor R252, a tenth resistor R2245, a sixth capacitor C2645, and a seventh capacitor C2646.

[0154] One end of the RST key S1 is grounded, and the other end is connected to the power supply circuit through the ninth resistor R252. The RST key S1 is connected to the reset pin G15 of the main chip through the tenth resistor R2245, and is grounded through the sixth capacitor C2645 and the seventh capacitor C2646, respectively.

[0155] The WPS key circuit includes a WPS key S2, an eleventh resistor R2246, a twelfth resistor R2247, an eighth capacitor C2647, and a ninth capacitor C2648.

[0156] One end of the WPS key S2 is grounded, and the other end is connected to the power supply circuit through the eleventh resistor R2246. The WPS key S2 is connected to the test mode selection pin G18 of the JTAG interface of the main chip through the twelfth resistor R2247, and is grounded through the eighth capacitor C2647 and the ninth capacitor C2648, respectively.

[0157] The reset pin G15 of the main chip is the WDT_RST_N pin, and the test mode selection pin G18 of the JTAG interface is the JTMS pin.

[0158] In the embodiment, the power supply circuit can provide 3.3V voltage for the RST key circuit and the WPS key circuit. One end of the RST key S1 is grounded, and the other end is connected to the power supply circuit through the ninth resistor R252, ensuring that the key circuit can obtain power from the power supply circuit. When the user presses the RST key S1, the key circuit transmits a signal to the reset pin G15 (i.e., the WDT_RST_N pin) of the main chip, performs a reset operation, and restarts the main chip. The tenth resistor R2245 connects the key S1 to the reset pin G15, and the sixth capacitor C2645 and the seventh capacitor C2646 serve as filters to remove power noise and suppress interference, ensuring the stability of the reset signal.

[0159] One end of the WPS button S2 is grounded, and the other end is connected with the power supply circuit through the eleventh resistor R2246 to ensure that the key circuit obtains power. When the user presses the WPS button S2, the signal is transmitted to the test mode selection pin G18 (i.e. JTMS pin) of the JTAG interface of the main chip through the twelfth resistor R2247 to select the debugging mode and start the WIFI protected setup (WPS) function. The eighth capacitor C2647 and the ninth capacitor C2648 also have the functions of filtering and denoising to ensure the stable transmission of the key signal and avoid noise interference.

[0160] It can be understood that by pressing the reset (RST) button S1, the internal program of the router can be reset to ensure that the system can recover to normal work when problems occur and avoid system freezing when the system fails. When the WIFI protected setup (WIFI Protected Setup, WPS) button S2 is pressed, the JTAG interface of the main chip can be switched to the WIFI protected setup mode to simplify the setting and security configuration of the home network, that is, to simplify the connection process of the WIFI device, improve the user experience, and facilitate the rapid pairing between devices.

[0161] In a possible implementation, the 5G router circuit further includes an I / O interface circuit.

[0162] The key circuit and the indicator light circuit are connected with the main chip through the I / O interface circuit.

[0163] In the embodiment, the key circuit (such as the RST and WPS key circuit) is connected with the main chip through the I / O interface circuit, and the signal generated after the key is pressed is transmitted to the main chip through the I / O interface circuit. After the main chip receives the key signal, the corresponding function is executed, such as the reset operation (through the RST button) or the start of the WPS pairing (through the WPS button). Among them, the signal transmission and interface conversion are performed through the I / O interface circuit to ensure that the key signal can be correctly and quickly transmitted to the main chip.

[0164] Based on the same concept, the embodiment of the present application also provides a router comprising the above-mentioned 5G router circuit.

[0165] The combination of the 5G module and the WIFI module provides high-speed and high-coverage network connection, supports wider device access, and meets different use requirements. By integrating the DDR3 circuit and the NAND circuit, the router can quickly process and store a large amount of data, improving the overall performance and response speed. The key circuit allows users to simply and intuitively operate the router, such as starting WPS or restarting, improving the user experience. The indicator light circuit allows users to quickly understand the status of the router (such as power supply, network connection), improving the operability and maintainability of the device.

[0166] The router provided by the embodiment of the application can provide fast and stable network services by integrating multiple function modules, and greatly improves user experience through simple user interaction and real-time state feedback.

[0167] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0168] In the description of the present application, it should be understood that the terms "include" and "have" and any variations thereof used herein are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units need not be limited to those clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0169] Unless otherwise explicitly specified and limited, the terms "mount", "connect", "connect", "fix" and the like should be understood broadly, for example, can be fixed connection, can also be detachable connection, or become an integral part; can be directly connected, or indirectly connected through an intermediate medium, can make the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0170] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A 5G router circuit, comprising: The application relates to a chip system. The chip system comprises a main chip, a 5G module circuit, a WIFI module circuit, a PCIE interface circuit and a network interface circuit, wherein the 5G module circuit is connected with the network interface circuit through the PCIE interface circuit, forming a first channel directly connecting the 5G module circuit and the network interface circuit; the network interface circuit is connected with the main chip, and the 5G module circuit is also connected with the main chip through an independent interface, forming a second channel between the 5G module circuit and the network interface circuit through the main chip; and the WIFI module circuit is connected with the main chip through the PCIE interface circuit. The 5G module circuit is used for transmitting received mobile data to the network interface circuit through the first channel and the second channel in parallel for mobile data forwarding and receiving data sent by the main chip through the independent interface for data sending. The WIFI module circuit is used for transmitting received wireless data to the main chip through the PCIE interface and receiving data sent by the main chip for data sending. The main chip is used for receiving and processing data transmitted by the 5G module circuit and the WIFI module circuit, and then sending the processed data to the 5G module circuit or the WIFI module circuit corresponding to a selected network.

2. The 5G router circuit of claim 1, wherein, The PCIE interface circuit comprises an interface conversion chip and an interface conversion chip clock circuit. The interface conversion chip is used for converting received mobile data from a PCIE interface signal into a physical layer signal and transmitting the physical layer signal to the network interface circuit. The interface conversion chip clock circuit is used for generating, synchronizing and distributing clock signals so that the timing of the PCIE interface circuit and the network interface circuit corresponds.

3. The 5G router circuit of claim 2, wherein, The interface conversion chip clock circuit comprises a first crystal oscillator, a first capacitor and a second capacitor. The ground pin of the first crystal oscillator is grounded. The output pin of the first crystal oscillator is connected with the output pin of the interface conversion chip, and the output pin of the first crystal oscillator is also grounded through the second capacitor. The input pin of the first crystal oscillator is connected with the input pin of the interface conversion chip, and the input pin of the first crystal oscillator is also grounded through the first capacitor.

4. The 5G router circuit of any of claims 1 to 3, wherein, The main chip comprises a main chip clock circuit, and the main chip clock circuit is connected with the crystal input pin and the crystal output pin of the main chip. The main chip clock circuit is used for providing clock signals to synchronize the operation of various circuits.

5. The 5G router circuit of claim 4, wherein, The main chip clock circuit comprises a second crystal oscillator, a first resistor, a second resistor, a third capacitor and a fourth capacitor. The ground pin of the second crystal oscillator is grounded. The input pin of the second crystal oscillator is connected with the crystal input pin of the main chip through the first resistor, and the input pin of the second crystal oscillator is also grounded through the fourth capacitor. The output pin of the second crystal oscillator is connected with the crystal output pin of the main chip through the second resistor, and the output pin of the second crystal oscillator is also grounded through the third capacitor.

6. The 5G router circuit of any one of claims 1 to 3, wherein, The 5G module circuit comprises a 5G signal antenna, and the WIFI module circuit comprises a WIFI antenna, both of which are electrically connected with the main chip; The 5G module circuit is configured to send and receive 5G signals through the 5G signal antenna; The WIFI module circuit is configured to send and receive WIFI signals through the WIFI antenna.

7. The 5G router circuit of any of claims 1 to 3, wherein, The 5G router circuit further comprises a power supply circuit and an indicator light circuit, and the power supply circuit is connected with the indicator light circuit; The power supply circuit is configured to connect an external power supply, convert a voltage provided by the external power supply into different working voltages, and output the working voltages to various circuits in the 5G router circuit; The indicator light circuit is configured to display working states of devices corresponding to the indicator light through indicator lights.

8. The 5G router circuit of claim 7, wherein, The indicator light circuit comprises a state indicator light, an Ethernet indicator light, a 5G network indicator light, a 4G network indicator light, a WIFI indicator light, a fifth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; The power supply circuit is connected with an input end of the indicator light circuit, and the power supply circuit is connected with anodes of the state indicator light, the Ethernet indicator light, the 5G network indicator light, the 4G network indicator light and the WIFI indicator light through the third resistor respectively, and the power supply circuit is grounded through the third resistor and the fifth capacitor in sequence; A cathode of the state indicator light is connected with a clock signal pin of a JTAG interface on the main chip through the fourth resistor; a cathode of the Ethernet indicator light is connected with a data output pin of the JTAG interface on the main chip through the fifth resistor; a cathode of the 5G network indicator light is connected with a data input pin of the JTAG interface on the main chip through the sixth resistor; a cathode of the 4G network indicator light is connected with a third data sending pin of a serial communication interface on the main chip through the seventh resistor; and a cathode of the WIFI indicator light is connected with a third data receiving pin of the serial communication interface on the main chip through the eighth resistor.

9. The 5G router circuit of claim 8, wherein, The 5G router circuit further comprises a key circuit, and the key circuit is electrically connected with the power supply circuit; The key circuit is configured to detect key input of a user to realize control and interaction functions of the router.

10. The 5G router circuit of claim 9, wherein, The key circuit comprises an RST key circuit and a WPS key circuit. The RST key circuit comprises an RST key, a ninth resistor, a tenth resistor, a sixth capacitor and a seventh capacitor. One end of the RST key is grounded, and the other end is connected with the power supply circuit through the ninth resistor; one end of the RST key connected with the power supply circuit is connected with a reset pin of the main chip through the tenth resistor, and is grounded through the sixth capacitor and the seventh capacitor respectively; The WPS key circuit comprises a WPS key, an eleventh resistor, a twelfth resistor, an eighth capacitor and a ninth capacitor. One end of the WPS button is grounded, and the other end is connected with the power supply circuit through the eleventh resistor. One end of the WPS button connected with the power supply circuit is connected with the test mode selection pin of the JTAG interface of the main chip through the twelfth resistor, and is grounded through the eighth capacitor and the ninth capacitor respectively.

11. The 5G router circuit of claim 9 or 10, wherein, The 5G router circuit further comprises an I / O interface circuit. The key circuit and the indicator lamp circuit are connected with the main chip through the I / O interface circuit.

12. The 5G router circuit of claim 7, wherein, The 5G router circuit further comprises a storage circuit. Correspondingly, the power supply circuit comprises a storage power supply circuit, and the storage circuit is electrically connected with the storage power supply circuit.

13. The 5G router circuit of claim 12, wherein, The storage power supply circuit comprises a voltage stabilizer, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a thirteenth resistor and a fourteenth resistor. The input pin of the voltage stabilizer receives an input voltage, and the input pin of the voltage stabilizer is grounded through the tenth capacitor and the eleventh capacitor respectively. The first output pin and the second output pin of the voltage stabilizer are connected in parallel to the storage circuit to provide working voltage for the storage circuit; the first output pin and the second output pin are grounded through the twelfth capacitor, the thirteenth capacitor and the fourteenth capacitor respectively; the first output pin and the second output pin are also connected with the input pin of the voltage stabilizer through the fourteenth resistor and grounded through the thirteenth resistor.

14. The 5G router circuit of any of claims 1-3, wherein, The 5G module circuit further comprises a SIM card circuit, and the SIM card circuit is electrically connected with the main chip. The SIM card circuit is used for acquiring and verifying SIM card information to enable the device to access the 5G network.

15. A router, characterized in that, The 5G router circuit comprises the 5G router circuit according to any one of claims 1 to 14.

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