IGBT device
By setting a second trench gate structure on the back of the IGBT device, the conductive channel of the collector region is controlled, which solves the voltage foldback problem when the reverse-conducting IGBT device is turned on in the forward direction, reduces turn-off loss and improves performance.
Patent Information
- Application Number
- CN202423209612.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2034-12-24
AI Technical Summary
Existing reverse-conducting IGBT devices exhibit voltage foldback during forward conduction, leading to increased turn-off losses.
A second trench gate structure is provided on the back of the semiconductor structure of the IGBT device, which runs through the collector region and the field stop layer. The second gate controls the formation of a conductive channel in the collector region, avoiding the unipolar mode during forward conduction, and reduces parasitic capacitance through the shielding gate layer.
This effectively avoids voltage foldback during forward conduction, reduces turn-off losses, and improves the switching performance and current density control of the device.
Smart Images
Figure CN223786400U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the field of semiconductor integrated circuit manufacturing, and relates to an IGBT device. BACKGROUND
[0002] Insulated Gate Bipolar Transistor (IGBT) is one of the most widely used semiconductor power devices today, which has the characteristics of large input impedance, small input capacitance, fast switching frequency, high voltage withstand, large current density, low on-state voltage drop, etc. Generally, an IGBT device needs to be matched with a fast recovery diode (FRD) in anti-parallel application, and an RC-IGBT device realizes the single use of the device by integrating an FRD in the IGBT, thereby saving the cost. However, since the collector of the RC-IGBT is electrically connected to the buffer zone and the drift zone at the bottom of the device through the N+ zone, when the device is forward conducting, the device first enters the unipolar mode, and then when the voltage between the collector and the emitter is greater than the bipolar opening voltage, the device enters the bipolar mode. There is a voltage snap-back phenomenon when the device changes from the unipolar mode to the bipolar mode, which causes the turn-off time of the device to be prolonged and the turn-off loss to be increased.
[0003] Therefore, there is an urgent need to find an IGBT device that can suppress the voltage snap-back phenomenon of the IGBT device. SUMMARY
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present utility model is to provide an IGBT device to solve the problem of large device turn-off loss caused by the voltage snap-back phenomenon of the device reverse conducting IGBT device in the prior art.
[0005] To achieve the above-mentioned purposes and other related purposes, the utility model provides an IGBT device, which comprises:
[0006] A semiconductor structure comprising a second conductive type base region, a first conductive type emitter region, a first trench gate structure, and a first conductive type field stop layer and a first conductive type drift region stacked in layers. The base region is located on the upper surface layer of the drift region, the emitter region is located on the upper surface layer of the base region, and the first trench gate structure penetrates the emitter region and the base region and extends to the bottom surface of the drift region.
[0007] A second conductive type collector region located on the lower surface layer of the field stop layer.
[0008] A second trench gate structure penetrating the collector region from a back surface of the semiconductor structure, the second trench gate structure comprising a back gate trench, a first dielectric layer, a shield gate layer, an isolation layer, a second dielectric layer and a back gate conductive layer, the back gate trench penetrating the collector region, the first dielectric layer covering inner walls and a bottom surface of a bottom of the back gate trench, the shield gate layer filling the bottom of the back gate trench, the isolation layer covering a bottom surface of the shield gate layer, the second dielectric layer covering inner walls of the back gate trench below the isolation layer, the back gate conductive layer filling the remaining back gate trench and having an upper surface higher than an upper surface of the collector region;
[0009] An emitter electrically connected with the emitter region;
[0010] A first gate electrically connected with the first trench gate structure;
[0011] A second gate electrically connected with the back gate conductive layer;
[0012] A collector electrically connected with the collector region and the shield gate layer.
[0013] Optionally, an upper surface layer of the drift region is further provided with a first conductive type carrier storage layer, the base region is located on an upper surface layer of the carrier storage layer, and a bottom surface of the first trench gate structure is lower than a bottom surface of the carrier storage layer.
[0014] Optionally, a doping concentration of the carrier storage layer is greater than a doping concentration of the drift region.
[0015] Optionally, the first trench gate structure comprises a control gate trench, a control gate dielectric layer and a control gate conductive layer, the control gate trench penetrating the base region and having a bottom surface extending into the drift region, the control gate dielectric layer covering inner walls and a bottom surface of the control gate trench, the control gate conductive layer filling the control gate trench, the control gate dielectric layer wrapping side walls and a bottom surface of the control gate conductive layer, and the first gate being electrically connected with the control gate conductive layer.
[0016] Optionally, the base region is further provided with a second conductive type contact region, and the emitter is electrically connected with the contact region.
[0017] Optionally, the IGBT device is further provided with a first interlayer dielectric layer covering an upper surface of the semiconductor structure, the emitter penetrates the first interlayer dielectric layer and is electrically connected with the emitter region, and the first gate penetrates the first interlayer dielectric layer and is electrically connected with the first trench gate structure.
[0018] Optionally, an upper surface of the back gate conductive layer is higher than an upper surface of the field stop layer.
[0019] Optionally, the second trench gate structure further comprises an outlead structure penetrating through the back gate conductive layer and the isolation layer and having a bottom surface electrically connected to the shield gate layer.
[0020] Optionally, the outlead structure comprises a shield gate contact hole, an insulating layer and a conductive connection layer, the shield gate contact hole penetrating through the back gate conductive layer and the isolation layer, the insulating layer covering an inner wall of the shield gate contact hole, and the conductive connection layer filling the shield gate contact hole and having upper and lower ends electrically connected to the shield gate layer and the collector, respectively.
[0021] Optionally, the IGBT device further comprises a second interlayer dielectric layer covering a back surface of the semiconductor structure, the collector penetrating through the second interlayer dielectric layer and being electrically connected to the collector region, and the second gate penetrating through the second interlayer dielectric layer and being electrically connected to the back gate conductive layer.
[0022] As described above, the IGBT device of the present application improves the structure of the device, sets a second trench gate structure on the back surface of the semiconductor structure, the second trench gate structure penetrating through the collector region and the field stop layer, the upper surface of the back gate conductive layer in the second trench gate structure being higher than the upper surface of the field stop layer and being electrically connected to the second gate, and a conductive channel can be formed in the collector region through the control of the second gate, thereby realizing the reverse conduction of the device without the need of connecting a diode in parallel. At the same time, since the collector is only electrically connected to the collector region, the unipolar mode during the forward conduction of the device is avoided, thereby avoiding the voltage foldback phenomenon during the forward conduction of the device and reducing the turn-off loss of the device. The setting of the shield gate layer reduces the parasitic capacitance introduced by the second trench gate structure, reduces the switching loss of the device, makes the current density controllable during the reverse conduction of the device, improves the performance of the device, and has high industrial utilization value. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 Fig. 1 shows a cross-sectional structure schematic diagram of the IGBT device of the present application.
[0024] REFERENCE SIGNS
[0025] 1 semiconductor structure
[0026] 11 field stop layer
[0027] 12 drift region
[0028] 13 carrier storage layer
[0029] 14 base region
[0030] 15 emitter region
[0031] 16 first trench gate structure
[0032] 161 Control gate trench
[0033] 162 Control gate dielectric layer
[0034] 163 Control gate conductive layer
[0035] 2. Collection Area
[0036] 3 Second trench grid structure
[0037] 31 Back grid groove
[0038] 32 First dielectric layer
[0039] 33 Shielding Grid Layer
[0040] 34 Isolation Layer
[0041] 35 Second dielectric layer
[0042] 36 Back gate conductive layer
[0043] 4 First interlayer dielectric layer
[0044] 5 Second interlayer dielectric layer
[0045] 6 emitters
[0046] 7 collectors Detailed Implementation
[0047] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0048] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the drawings only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0049] This embodiment provides an IGBT device, such as Figure 1As shown, it is a schematic diagram of the cross-sectional structure of the IGBT device, including a semiconductor structure 1, a second conductive type collector region 2, a second trench gate structure 3, an emitter 6, a first gate, a second gate and a collector 7. The semiconductor structure 1 includes a second conductive type base region 14, a first conductive type emitter region 15, a first trench gate structure 16 and a first conductive type field stop layer 11 and a first conductive type drift region 12 which are stacked. The base region 14 is located on the upper surface layer of the drift region 12, the emitter region 15 is located on the upper surface layer of the base region 14, and the first trench gate structure 16 penetrates the emitter region 15 and the base region 14 and extends to the bottom of the drift region 12. The collector region 2 is located on the lower surface layer of the field stop layer 11. The second trench gate structure 3 penetrates the collector region 2 from the back surface of the semiconductor structure 1. The second trench gate structure 3 includes a back gate trench 31, a first dielectric layer 32, a shield gate layer 33, an isolation layer 34, a second dielectric layer 35 and a back gate conductive layer 36. The back gate trench 31 penetrates the collector region 2. The first dielectric layer 32 covers the inner wall and the bottom of the back gate trench 31. The shield gate layer 33 fills the bottom of the back gate trench 31. The isolation layer 34 covers the bottom of the shield gate layer 33. The second dielectric layer 35 covers the inner wall of the back gate trench 31 below the isolation layer 34. The back gate conductive layer 36 fills the remaining back gate trench 31 and the upper surface is higher than the upper surface of the collector region 2. The emitter 6 is electrically connected with the emitter region 15. The first gate is electrically connected with the first trench gate structure 16. The second gate is electrically connected with the back gate conductive layer 36. The collector 7 is electrically connected with the collector region 2 and the shield gate layer 33.
[0050] Specifically, the first conductive type includes one of N type or P type, the second conductive type includes one of N type or P type, and the conductive type of the first conductive type is opposite to that of the second conductive type. In this embodiment, the first conductive type is N type, and the second conductive type is P type.
[0051] Specifically, the semiconductor structure 1 is generally the structure of the front electrode of the device to be made, and the size, shape and thickness thereof can be selected according to actual conditions.
[0052] Specifically, the field stop layer 11 is generally a heavily doped substrate, which is generally used for electric field cutoff of the device, optimizes the electric field distribution in the device, reduces the saturation voltage drop and switching loss of the device, and the material thereof includes silicon, silicon germanium, silicon carbide, diamond or other suitable semiconductor materials. Preferably, a silicon layer is used as the substrate (field stop layer 11).
[0053] Specifically, the thickness and doping concentration of the field stop layer 11 can be selected according to actual conditions under the condition of ensuring the performance of the device.
[0054] Specifically, the drift region 12 is usually formed by epitaxy on the surface of the field stop layer 11 (substrate) and is mainly used to ensure the withstand voltage of the device. The thickness and doping concentration of the drift region 12 can be selected according to actual conditions under the condition of ensuring the performance of the device.
[0055] As an example, the upper surface layer of the drift region 12 is further provided with a first conductive type carrier storage layer 13, and the base region 14 is located on the upper surface layer of the carrier storage layer 13. The bottom surface of the first trench gate structure 16 is lower than the bottom surface of the carrier storage layer 13.
[0056] Specifically, the carrier storage layer 13 is usually used to hinder the flow of holes in the drift region 12, improve the injection efficiency of carriers (electrons), and then enhance the conductance modulation effect in the device, thereby reducing the on-state voltage drop of the device.
[0057] As an example, the doping concentration of the carrier storage layer is greater than the doping concentration of the drift region 12.
[0058] Specifically, by making the doping concentration of the carrier storage layer 13 greater than the doping concentration of the drift region 12, a diffusion potential is formed at the junction of the drift region 12 and the carrier storage layer 13, thereby achieving the blocking of the holes flowing to the emitter 6.
[0059] Specifically, the thickness and doping concentration of the carrier storage layer 13 can be selected according to actual conditions under the condition of ensuring the performance of the device.
[0060] Specifically, the base region 14 is usually a normally doped region located on the upper surface layer of the entire carrier storage layer 13. The thickness and doping concentration of the base region 14 can be selected according to actual conditions under the condition of ensuring the performance of the device. Here, the normally doped is relative to the lightly doped and the heavily doped.
[0061] Specifically, the emitter region 15 is usually a heavily doped region located on the upper surface layer of the base region 14. The emitter region 15 can be spaced apart on the upper surface layer of the base region 14, or can cover the entire upper surface layer of the base region 14. In the embodiment, the emitter region 15 is located on the entire upper surface layer of the base region 14.
[0062] Specifically, the contact type between the emitter region 15 and the emitter 6 is ohmic contact. The thickness, size, shape and doping concentration of the emitter region 15 can be selected according to actual conditions under the condition of ensuring the performance of the device.
[0063] As an example, the first trench gate structure 16 includes a control gate trench 161, a control gate dielectric layer 162 and a control gate conductive layer 163, the control gate trench 161 penetrates the base region 14 and extends to the drift region 12, the control gate dielectric layer 162 covers the inner wall and bottom surface of the control gate trench 161, and the control gate conductive layer 163 fills the control gate trench 161, and the control gate dielectric layer 162 wraps the side wall and bottom surface of the control gate conductive layer 163, and the first gate electrode is electrically connected with the control gate conductive layer 163.
[0064] Specifically, the first trench gate structure 16 is used to control the base region 14 part adjacent to the side wall of the first trench gate structure 16 to form a conductive channel, so as to control the turn-off and turn-on of the device during normal operation, and the depth, opening size and opening shape of the control gate trench 161 can be selected according to actual conditions while ensuring the performance of the device; when the upper surface layer of the drift region 12 is provided with the carrier storage layer 13, the distance between the bottom surface of the control gate trench 161 and the bottom surface of the carrier storage layer 13 can be selected according to actual conditions. Here, the depth refers to the distance between the bottom surface of the control gate trench 161 and the opening of the control gate trench 161.
[0065] Specifically, the material of the control gate dielectric layer 162 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0066] Specifically, the thickness of the control gate dielectric layer 162 can be selected according to actual conditions while ensuring the performance of the device.
[0067] It should be noted that due to the process of manufacturing the control gate dielectric layer 162, the control gate dielectric layer 162 formed usually covers the upper surface of the emitter region 15 or the upper surface of the base region 14 between the emitter regions 15, and the upper surface of the control gate dielectric layer 162 exposed later needs to form an interlayer dielectric layer, so the control gate dielectric layer 162 outside the control gate trench 161 can be removed.
[0068] Specifically, the upper surface of the control gate conductive layer 163 is usually flush with the upper surface of the semiconductor structure 1 (i.e. the emitter region 15 or the control gate dielectric layer 162 covering the upper surface of the emitter region 15), and the material of the control gate conductive layer 163 includes polysilicon or other suitable conductive materials. Preferably, the polysilicon layer filling the control gate trench 161 is used as the control gate conductive layer 163.
[0069] As an example, the base region 14 is also provided with a contact region of the second conductive type, and the emitter 6 is electrically connected with the contact region.
[0070] Specifically, the contact region is usually a heavily doped region and the contact between the contact region and the emitter 6 is an ohmic contact, which is used to realize the electrical connection between the emitter 6 and the base region 14. The thickness, size and shape of the contact region can be selected according to actual conditions while ensuring the performance of the device.
[0071] Specifically, when the emitter regions 15 are arranged at intervals, the contact region is usually located between two adjacent emitter regions 15 and is adjacent to the emitter regions 15. When the emitter regions 15 are located on the upper surface layer of the entire base region 14, the emitter 6 usually penetrates the emitter regions 15, and the contact region usually wraps the bottom of the emitter 6 below the emitter regions 15.
[0072] As an example, the IGBT device further comprises a first interlayer dielectric layer 4 covering the upper surface of the semiconductor structure 1. The emitter 6 penetrates the first interlayer dielectric layer 4 and is electrically connected to the emitter regions 15. The first gate penetrates the first interlayer dielectric layer 4 and is electrically connected to the first trench gate structure 16.
[0073] Specifically, the first interlayer dielectric layer 4 is used to realize the insulation between the front electrodes (the emitter 6 and the first gate) of the device and ensure the withstand voltage performance of the device. The thickness of the first interlayer dielectric layer 4 can be selected according to actual conditions while ensuring the performance of the device.
[0074] Specifically, the material of the first interlayer dielectric layer 4 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0075] Specifically, the first interlayer dielectric layer 4 further comprises an emitter contact hole and a first gate contact hole. The emitter contact hole penetrates the first interlayer dielectric layer 4 and exposes at least the emitter regions 15 at the bottom. When the device comprises a contact region, the bottom of the emitter contact hole also exposes the contact region. The first gate contact hole penetrates the first interlayer dielectric layer 4 and exposes the control gate conductive layer 163 at the bottom surface.
[0076] Specifically, the emitter 6 fills the emitter contact hole, and the first gate fills the first gate contact hole. The opening size, opening shape and depth of the emitter contact hole can be selected according to actual conditions while ensuring the performance of the device. The opening size and opening shape of the first gate contact hole can be selected according to actual conditions. Here, the depth refers to the distance between the bottom surface of the emitter contact hole and its opening.
[0077] Specifically, the material of the emitter 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials. The material of the first gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0078] Specifically, the collector region 2 is located at the lower surface layer of the entire field stop layer 11, and the contact type between the collector region 2 and the collector electrode 7 is ohmic contact. The thickness, size and shape of the collector region 2 can be selected according to actual conditions under the condition of ensuring the performance of the device. The thickness here refers to the distance between the upper surface and the lower surface of the collector region 2.
[0079] Specifically, the second trench gate structure 3 is used to form a conductive channel in the collector region 2 adjacent to the second trench gate structure 3. When the device is in reverse conduction, the conductive channel in the collector region 2 is controlled to achieve reverse conduction of the device.
[0080] Specifically, the depth, opening size and opening shape of the back gate trench 31 can be selected according to actual conditions under the condition of ensuring the performance of the device. The depth here refers to the distance between the bottom surface of the back gate trench 31 and the opening of the back gate trench 31.
[0081] Specifically, the material of the first dielectric layer 32 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials; and the material of the shielding gate layer 33 includes polysilicon or other suitable conductive materials.
[0082] It should be noted that after the back gate trench 31 is formed, the material layer of the first dielectric layer 32 covering the inner wall and bottom surface of the back gate trench 31 and the shielding gate material layer filling the back gate trench 31 are usually formed in sequence, and then the shielding gate material layer and the first dielectric material layer are etched back in sequence to obtain the first dielectric layer 32 with the bottom surface higher than the upper surface of the field stop layer 11 and the shielding gate layer 33 filling the bottom of the back gate trench 31. Generally, the bottom surface of the shielding gate layer 33 is not higher than the bottom surface of the first dielectric layer 32, and the first dielectric layer 32 covers the bottom of the back gate trench 31 and wraps the side wall and upper surface of the shielding gate layer 33. Here and in the following, the upper surface and bottom surface of the structures other than the back gate trench 31 are the relative positions shown in the figure. Figure 1
[0083] Specifically, the thickness of the first dielectric layer 32 is greater than the thickness of the second dielectric layer 35, and the thickness of the first dielectric layer 32 can be selected according to actual conditions under the condition of ensuring the performance of the device.
[0084] Specifically, the material of the isolation layer 34 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0085] It should be noted that after the shielding gate material layer and the first dielectric material layer are etched back, the isolation dielectric material layer filling the remaining part of the back gate trench 31 is usually formed, and then the isolation dielectric material layer is etched back to obtain the isolation layer 34. The upper surface of the isolation layer 34 is in contact with the lower surfaces of the first dielectric layer 32 and the shielding gate layer 33.
[0086] Specifically, the lower surface of the isolation layer 34 can be selected according to actual conditions, while ensuring the performance of the device.
[0087] Specifically, the second dielectric layer 35 generally covers the inner wall of the remaining part of the back gate trench 31 and the bottom surface of the semiconductor structure 1, and can also cover the lower surface of the isolation layer 34, while ensuring the performance of the device. The thickness of the second dielectric layer 35 can be selected according to actual conditions.
[0088] Specifically, the material of the second dielectric layer 35 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0089] Specifically, the second dielectric layer 35 wraps the sidewall of the back gate conductive layer 36, and the material of the back gate conductive layer 36 includes polysilicon or other suitable conductive materials.
[0090] As an example, the upper surface of the back gate conductive layer 36 is higher than the upper surface of the field stop layer 11. By making the upper surface of the back gate conductive layer 36 higher than the upper surface of the field stop layer 11, the switching performance of the second trench gate structure 3 can be improved.
[0091] Specifically, the distance between the upper surface of the back gate conductive layer 36 and the upper surface of the field stop layer 11 can be selected according to actual conditions, while ensuring the performance of the device.
[0092] It should be noted that the second trench gate structure 3 is generally located directly below the region between the two adjacent first trench gate structures 16, that is, the first trench gate structure 16 and the second trench gate structure 3 are staggered to obtain better device performance. The position of the second trench gate structure 3 can also be selected according to actual conditions to be arranged at other suitable positions of the lower surface layer of the device, while ensuring the performance of the device.
[0093] As an example, the second trench gate structure 3 further comprises an extraction structure penetrating the back gate conductive layer 36 and the isolation layer 34, and the bottom surface of the extraction structure is electrically connected with the shield gate layer 33.
[0094] Specifically, the contact structure is used to extract the shield gate layer 33 at the bottom of the back gate trench 31, and electrically connect the shield gate layer 33 with the collector 7.
[0095] As an example, the extraction structure includes a shield gate contact hole, an insulating layer, and a conductive connection layer. The shield gate contact hole penetrates the back gate conductive layer 36 and the isolation layer 34. The insulating layer covers the inner wall of the shield gate contact hole. The conductive connection layer fills the shield gate contact hole, and the upper and lower ends of the conductive connection layer are respectively electrically connected with the shield gate layer 33 and the collector 7.
[0096] Specifically, the shield gate contact hole is opened from the bottom surface of the back gate conductive layer 36 and extends upward into the shield gate layer 33. The opening size and shape of the shield gate contact hole can be selected according to actual conditions while ensuring device performance.
[0097] Specifically, the insulating layer is used for insulation between the conductive connection layer and the back gate conductive layer 36. The thickness of the insulating layer can be selected according to actual conditions while ensuring device performance.
[0098] Specifically, the insulating layer wraps the sidewall of the conductive connection layer. The material of the insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0099] Specifically, the conductive connection layer is used for electrically connecting the shield gate layer 33 and the collector 7. The material of the conductive connection layer includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.
[0100] As an example, the IGBT device further comprises a second interlayer dielectric layer 5 covering the back surface of the semiconductor structure 1. The collector 7 penetrates the second interlayer dielectric layer 5 and is electrically connected to the collector region 2. The second gate penetrates the second interlayer dielectric layer 5 and is electrically connected to the back gate conductive layer 36.
[0101] Specifically, the second interlayer dielectric layer 5 is generally used for electrical isolation between the second gate and the collector 7. The thickness of the second interlayer dielectric layer 5 can be selected according to actual conditions while ensuring device performance.
[0102] Specifically, the material of the second interlayer dielectric layer 5 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0103] Specifically, the material of the collector 7 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. The material of the second gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, an aluminum-titanium-nickel-silver composite layer with different thicknesses is used as the collector 7.
[0104] It should be noted that, generally, when the device is forward conducting, the second gate is at zero potential or negative voltage state, at this time, the reverse type layer cannot be formed in the collector region 2, and since the collector 7 and the field stop layer 11 are not electrically connected, the device does not exist in the unipolar mode, thereby avoiding the voltage snap-back phenomenon of the device forward conducting, when the device is reverse conducting, by giving the second gate a forward bias voltage (generally between 10V-20V), under the action of the back gate conductive layer 36 electrically connected with the second gate, the reverse type layer is formed in the region adjacent to the second trench gate structure 3 of the collector region 2, thereby forming a conductive channel, so that the device can be reverse conducting, and considering the delay of the opening and closing of the conductive channel, a bias compensation pulse can be given to the second gate before reverse conducting, thereby improving the switching speed of the device.
[0105] Specifically, by providing the second trench gate structure 3 penetrating the collector region 2 and the field stop layer 11 on the back of the device, and the back gate conductive layer 36 in the second trench gate structure 3 is electrically connected with the second gate, the opening and closing of the conductive channel in the collector region 2 is controlled separately, when the device is reverse conducting, the conductive channel is generated in the collector region 2 by the control of the second gate, thereby realizing the reverse conducting of the device.
[0106] Specifically, since the collector 7 is only electrically connected with the collector region 2, the unipolar mode exists in the process of the device conducting, thereby avoiding the voltage snap-back phenomenon of the device forward conducting, thereby reducing the off-state loss of the device, and by providing the shielding gate layer 33, the parasitic capacitance introduced by the second trench gate structure can be reduced, so that the current density of the device when reverse conducting is controllable, thereby improving the performance of the device.
[0107] In summary, the IGBT device of the utility model improves the structure of the device, provides the second trench gate structure penetrating the collector region and the field stop layer on the back of the semiconductor structure, electrically connects the back gate conductive layer in the second trench gate structure with the second gate, and by the control of the second gate, the conductive channel can be formed in the collector region, thereby realizing the reverse conducting of the device; since the collector is only electrically connected with the collector region, the unipolar mode exists in the process of the device conducting, thereby avoiding the voltage snap-back phenomenon of the device forward conducting, thereby reducing the off-state loss of the device; by providing the shielding gate layer, the current density of the device when reverse conducting is controllable, thereby improving the performance of the device, and reducing the parasitic capacitance introduced by the second trench gate structure. Therefore, the utility model effectively overcomes the shortcomings in the prior art and has high industrial utilization value.
[0108] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. An IGBT device, characterized by, The application relates to an IGBT device. The IGBT device comprises a semiconductor structure, a second-conductivity-type collector region, a second-trench-gate structure and a collector electrode. The semiconductor structure comprises a second-conductivity-type base region, a first-conductivity-type emitter region, a first-trench-gate structure and a first-conductivity-type field-stop layer and a first-conductivity-type drift region which are stacked, the base region is located on the upper surface layer of the drift region, the emitter region is located on the upper surface layer of the base region, and the first-trench-gate structure penetrates the emitter region and the base region and has a bottom surface extending into the drift region. The second-conductivity-type collector region is located on the lower surface layer of the field-stop layer. The second-trench-gate structure penetrates the collector region from the back surface of the semiconductor structure, and comprises a back-gate trench, a first dielectric layer, a shield-gate layer, an isolation layer, a second dielectric layer and a back-gate conductive layer. The back-gate trench penetrates the collector region. The first dielectric layer covers the inner wall and the bottom surface of the bottom part of the back-gate trench. The shield-gate layer fills the bottom part of the back-gate trench.
2. The IGBT device of claim 1, wherein: The isolation layer covers the bottom surface of the shield-gate layer.
3. The IGBT device of claim 2, wherein: The second dielectric layer covers the inner wall of the back-gate trench below the isolation layer.
4. The IGBT device of claim 1, wherein: The back-gate conductive layer fills the remaining back-gate trench and has an upper surface higher than the upper surface of the collector region.
5. The IGBT device of claim 1, wherein: The emitter electrode is electrically connected with the emitter region.
6. The IGBT device of claim 1, wherein: The first gate electrode is electrically connected with the first-trench-gate structure.
7. The IGBT device of claim 1, wherein: The second gate electrode is electrically connected with the back-gate conductive layer.
8. The IGBT device of claim 1, wherein: The collector electrode is electrically connected with the collector region and the shield-gate layer.
9. The IGBT device of claim 8, wherein: The upper surface layer of the drift region is further provided with a first-conductivity-type carrier storage layer, the base region is located on the upper surface layer of the carrier storage layer, and the bottom surface of the first-trench-gate structure is lower than the bottom surface of the carrier storage layer. The doping concentration of the carrier storage layer is greater than the doping concentration of the drift region. The first-trench-gate structure comprises a control-gate trench, a control-gate dielectric layer and a control-gate conductive layer. The control-gate trench penetrates the base region and has a bottom surface extending into the drift region. The control-gate dielectric layer covers the inner wall and the bottom surface of the control-gate trench. The control-gate conductive layer fills the control-gate trench. The control-gate dielectric layer wraps the side wall and the bottom surface of the control-gate conductive layer. The first gate electrode is electrically connected with the control-gate conductive layer. The base region is further provided with a second-conductivity-type contact region, and the emitter electrode is electrically connected with the contact region. The IGBT device is further provided with a first interlayer dielectric layer covering the upper surface of the semiconductor structure. The emitter electrode penetrates the first interlayer dielectric layer and is electrically connected with the emitter region. The first gate electrode penetrates the first interlayer dielectric layer and is electrically connected with the first-trench-gate structure. The upper surface of the back-gate conductive layer is higher than the upper surface of the field-stop layer. The second-trench-gate structure is further provided with an extraction structure penetrating the back-gate conductive layer and the isolation layer and having a bottom surface electrically connected with the shield-gate layer. The extraction structure comprises a shield-gate contact hole, an insulating layer and a conductive connecting layer. The shield-gate contact hole penetrates the back-gate conductive layer and the isolation layer. The insulating layer covers the inner wall of the shield-gate contact hole. The conductive connecting layer fills the shield-gate contact hole. The upper and lower ends of the conductive connecting layer are respectively electrically connected with the shield-gate layer and the collector electrode.
10. The IGBT device of claim 1, wherein: The IGBT device further comprises a second interlayer dielectric layer covering the back surface of the semiconductor structure, the collector electrode penetrates through the second interlayer dielectric layer and is electrically connected with the collector region, and the second gate electrode penetrates through the second interlayer dielectric layer and is electrically connected with the back gate conductive layer.