Longitudinal compact trench gate silicon carbide VDMOS
By designing a vertically compact trench gate structure, the problem of excessive thickness in silicon carbide VDMOS devices was solved, achieving a compact design and high power density, reducing on-resistance and body diode losses, and improving device reliability.
Patent Information
- Application Number
- CN202520099494.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-01-16
AI Technical Summary
Existing silicon carbide VDMOS devices, while ensuring high withstand voltage, low on-resistance, fast switching speed and high reliability, have excessively high thickness requirements, making it difficult to achieve a compact device design.
A vertically compact trench gate structure is adopted. By separating the N-type source region and the P-type source region, the contact resistance between the source metal and the P-type material of the body diode is reduced. An electric field protection region is constructed in the P-type well region. Combined with the N-type low-resistance region, current redistribution is performed to reduce on-resistance and heat concentration.
This achieves a compact device design, reduces device thickness, increases power density, reduces body diode conduction losses, and enhances gate reliability.
Smart Images
Figure CN223786402U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a longitudinal compact type trench gate silicon carbide VDMOS. BACKGROUND
[0002] The silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric automobile, aerospace, power conversion and other fields. For the silicon carbide power VDMOS, the performance requirements of device are different in different fields, and the thickness requirement of the prior art for the silicon carbide VDMOS is higher and higher, under the condition of guaranteeing higher withstand voltage capacity, lower on-resistance, faster switching speed, higher reliability and lower body diode on-resistance, the thickness of the silicon carbide VDMOS is smaller. SUMMARY
[0003] The utility model solves the technical problem, in providing a longitudinal compact type trench gate silicon carbide VDMOS, realize the compact design of device gate structure, reduce the device gate thickness, improve the power density of device.
[0004] In the first aspect, the utility model provides a longitudinal compact type trench gate silicon carbide VDMOS, it includes:
[0005] Silicon carbide substrate,
[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] Low resistance area, the lower side of the low resistance area is connected to the upper side of the drift layer;
[0008] P type source area, the lower side of the P type source area is connected to the upper side of the low resistance area;
[0009] P type trap area, the lower side of the P type trap area is connected to the upper side of the low resistance area, the outer side of the P type trap area is connected to the inner side of the P type source area, the P type trap area is equipped with N type source area, and the P type trap area is equipped with a recess;
[0010] Insulating medium layer, the lower part of the insulating medium layer is located in the recess, the outer side of the insulating medium layer is connected to the inner side of the P type trap area and the inner side of N type source area respectively, and the insulating medium layer is equipped with a trench;
[0011] Gate metal layer, the gate metal layer is located in the trench;
[0012] Source metal layer, the source metal layer is connected to the P type source area, the P type trap area and N type source area respectively;
[0013] And drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.
[0014] The utility model discloses a kind of longitudinal compact trench gate silicon carbide VDMOS, which is characterized by the following:
[0015] I, the utility model discloses a kind of longitudinal compact trench gate silicon carbide VDMOS, which is characterized by the following:
[0016] II, P-type well region is wrapped N-type source region, and the region is simultaneously constructed below insulating dielectric layer, so as to realize the electric field protection of P-type well region to insulating dielectric layer corner, improve the gate reliability of device;
[0017] III, the gate structure of device, P-type well region structure and N-type low resistance area structure are designed compact in longitudinal structure, and device thickness can be reduced from gate structure;
[0018] IV, N-type low resistance area is constructed below device gate structure, and its main effects have two: first, the current from N-type source region is laterally redistributed, and the on-resistance and the problem of heat concentration are reduced, and second, the transition zone of P-type source region to N-type drift layer is constructed, since the doping concentration of N-type low resistance area is higher than the doping concentration of drift layer, so the voltage increase space charge region diffusion of this area is slower, and the device damage caused by electric field abrupt change is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0019] The utility model will be further described below with reference to the drawings in combination with embodiments.
[0020] Figure 1 It is the principle diagram of the utility model of a kind of longitudinal compact trench gate silicon carbide VDMOS.
[0021] Figure 2 It is the process section of the utility model of a kind of longitudinal compact trench gate silicon carbide VDMOS Figure 1 .
[0022] Figure 3 It is the process section of the utility model of a kind of longitudinal compact trench gate silicon carbide VDMOS Figure 2 .
[0023] Figure 4 It is the process section of the utility model of a kind of longitudinal compact trench gate silicon carbide VDMOS Figure 3 .
[0024] Figure 4 It is the process section of the utility model of a kind of longitudinal compact trench gate silicon carbide VDMOS Figure 5 .
[0025] Figure 4This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 5 .
[0026] Figure 6 This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 5 .
[0027] Figure 6 This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0028] Figure 6 This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0029] Figure 8 This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0030] Figure 8 This is a cross-sectional view of the process of a vertically compact trench gate silicon carbide VDMOS according to the present invention. Figure 9 . Detailed Implementation
[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0033] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0034] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly.
[0035] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0036] As Figure 8 shown, the embodiment of the present application provides a longitudinal compact trench gate silicon carbide VDMOS, comprising:
[0037] a silicon carbide substrate 1,
[0038] Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1;
[0039] Low-resistivity region 3, the lower side of which is connected to the upper side of the drift layer 2;
[0040] P-type source region 4, the lower side of which is connected to the upper side of the low-resistivity region 3;
[0041] P-type well region 5, the lower side of the P-type well region 5 is connected to the upper side of the low resistance region 3, the outer side of the P-type well region 5 is connected to the inner side of the P-type source region 4, an N-type source region 51 is provided in the P-type well region 5, and a groove 52 is provided in the P-type well region 5.
[0042] An insulating dielectric layer 6 is provided at its lower part within the groove 52. The outer side of the insulating dielectric layer 6 is connected to the inner side of the P-type well region 5 and the inner side of the N-type source region 51, respectively. A groove 61 is provided within the insulating dielectric layer 6.
[0043] A gate metal layer 7 is disposed within the trench 61;
[0044] Source metal layer 8, which is connected to the P-type source region 4, the P-type well region 5 and the N-type source region 51 respectively;
[0045] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0046] In this embodiment, preferably, the thickness of the low-resistivity region 2 is 300-500 nm.
[0047] In this embodiment, preferably, the distance between the lower side of the insulating dielectric layer 6 and the upper side of the low-resistivity region 3 is 100-200 nm.
[0048] In this embodiment, preferably, the doping concentration of the low-resistivity region 3 is greater than the doping concentration of the drift layer 2, and the doping concentration of the P-type source region 4 is greater than the doping concentration of the low-resistivity region 3.
[0049] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the low-resistivity region 3 are all N-type.
[0050] like Figure 9 Figure 10 Figure 9 Figure 10 Figure 11 Figure 10 Figure 11 Figure 1 Figures 1 to 11 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0051] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9; epitaxially grow drift layer 2 on the upper side of silicon carbide substrate 1;
[0052] Step 2: Form a low-resistivity region 3 by ion implantation into the drift layer 2;
[0053] Step 3, forming a barrier layer a, etching the barrier layer a to form a via, ion implantation to the drift layer 2 to form a P-type source region 4;
[0054] Step 4, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, ion implantation to the drift layer 2 to form a P-type well region 5;
[0055] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, ion implantation to the P-type well region 5 to form an N-type source region 51.
Claims
1. A longitudinal compact trench-gated silicon carbide VDMOS, characterized in that: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a low-resistance region connected to the upper side of the drift layer, a P-type source region connected to the upper side of the low-resistance region, a P-type well region connected to the upper side of the low-resistance region, the inner side of the P-type well region connected to the inner side of the P-type source region, an N-type source region arranged in the P-type well region, a groove arranged in the P-type well region, an insulating medium layer arranged in the groove, the lower side of the insulating medium layer connected to the upper side of the low-resistance region, the outer side of the insulating medium layer connected to the inner side of the P-type well region and the inner side of the N-type source region, a gate metal layer arranged in the groove, a source metal layer connected to the P-type source region, the P-type well region and the N-type source region, and a drain metal layer connected to the lower side of the silicon carbide substrate. The thickness of the low-resistance region is 300-500 nm. The distance between the lower side of the insulating medium layer and the upper side of the low-resistance region is 100-200 nm. The doping concentration of the low-resistance region is greater than that of the drift layer, and the doping concentration of the P-type source region is greater than that of the low-resistance region. The silicon carbide substrate, the drift layer and the low-resistance region are all N-type. 2. A longitudinal compact trench gate silicon carbide VDMOS as described in claim 1, wherein: 3. A longitudinal compact trench gate silicon carbide VDMOS as described in claim 1, wherein: 4. The longitudinal compact trench gate silicon carbide VDMOS of claim 1, wherein: 5. The longitudinal compact trench gate silicon carbide VDMOS of claim 1, wherein: